International Journal of Advances in Engineering Sciences Vol.

1, Issue 2, April, 2011

STUDY AND ANALYSIS OF LOW VOLTAGE

DIFFERENTIAL VOLTAGE CURRENT
CONVEYOR: A NOVEL DESIGN
Kamlesh Kumar Singh1
Ph.D.(Pursuing), Dept. of Electronics,
Dr. R. M. L. Avadh University, Faizabad
Email: kam2k_singh@yahoo.com

Prof.(Dr.) Kalyan. Singh2

HOD, Dept. of Electronics,
Dr. R. M. L. Avadh University, Faizabad

ABSTRACT- This paper presents a novel CMOS

differential voltage current conveyor. The differential
voltage current conveyor exhibits low voltage and a wide
dynamic input range. It is very suitable to use in a voltagemode signal processing, which is continually more popular
than any other technique. The proposed element is realized
in a CMos technology and is examined the performances
through PSPICE simulations. Experimental results show
good agreement with the simulation results and prove the
feasibility of the novel design.

of the output current follows the input current direction with

both currents flowing either into or out of the device. Since the
DVCC exhibits two high input impedance terminals, it shows
itself suitable for handling differential input signals. In
addition, it has the advantage of minimizing the number of
floating elements inherent in many CCII applications.

Keywords: Current-conveyor, differential voltage, current

conveyor, PSPICE.
1. INTRODUCTION
Since its first introduction, by A. Sedra and K. Smith in 1970 ,
the second-generation current conveyor (CCII) has proved to
be a versatile analog building block that can be used to
implement numerous high frequency analog signal
applications. However, when it comes to applications
demanding differential or floating inputs like impedance
converters and current mode instrumentation amplifiers, which
also require two high input impedance terminals, a single CCII
block is no more sufficient. In addition, most of these
applications employ floating elements in order to minimize the
number of used CCII blocks. For this reason and in order to
provide two high input impedance terminals, the differential
voltage current conveyor (DVCC) was proposed in 1997 as a
four terminal device with the following properties [Fig.1]:

0
IY1
I 0
Y 2 1
V X

0
I Z

0
1

0
0

Figure 1: Block representation of the DVCC

In this paper a new CMOS DVCC is proposed. This paper is
organized as follows: In section 2 the proposed Novel low
voltage DVCC circuit is presented. Thereafter, DVCC study
and analysis are discussed in section 3. PSPICE simulations
for proposed circuits are provided.
2. NOVEL DESIGN OF LOW VOLTAGE DVCC
Proposed DVCC is similar as DVCC. But it has multiple
outputs (two Z+ stages and one Z- stage) as shown in Fig.
2.1.The gain of second Z+ stage and Z- stage is three times of
first Z+ stage as defined in equations (2.1, and 2.2).

0
VY 1
0
VY 2

0
I X
0

VZ

While the X terminal voltage follows the voltage difference of

terminals Y1 and Y2, a current injected at the X terminal is
being replicated to the Z terminal. An ideal DVCC exhibits
zero input resistance at terminal X, and infinite resistance at
both Y terminals as well as the Z terminal. The flow direction

Figure 2.1 Schematic Diagram of Modified DVCC

12

International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011

Current and voltage relation for Modified DVCC are as
follows
VX=VY1-VY2

(2.1)

IY1=IY2=0
IZi+=k1IX
IZj-=k2IX
Where: i=1, 2 and j=1
VY1= voltage at node Y1
VY2= voltage at node Y2
VX= voltage at node X

(2.2)
(2.3)
(2.4)

IX = current at node X
IZi+=currents at output node Z+
IZj-= current at output node ZA proposed DVCC incorporates two Z+ stages, one with k1=1
and the other with k1=3. Moreover, it also has a Z- stage with
k2=3 (equation 2.4). As far as modified DVCC
implementation is concerned the required gain (as given in
equation (2.3, 2.4) from X to Z terminal is realized by
maintaining the aspect ratios of different transistors as defined
in equation (2.5 2.6).
(W/L)7, 8 = a;
(W/L)12, 13 = b
(2.5)
(W/L) 9, 15, 16, 17 = 3a;

(W/L)14, 18, 19, 20 = 3b

Figure 2.2 CMOS Realization of Novel DVCC

Figure 3.1 and 3.2 shows the DC characteristic obtained by
simulation. Figure 3.1 proves that equation (2.1) is correct. It
is obtained by fixed VY1 and varies VY2. By making Vin1 fixed
at 0 mV and vary the Vin2, the variation in Vx is obtained
which is shown in figure 3.1. This figure also verifies equation
2.1.

(2.6)

Figure (3.3) shows the current relationship of DVCC. It can be

obtained just putting VY1 as constant and varying VY2. It shows
that device get saturated when -1V > VY2 > +1V

The proposed DVCC uses only 20 transistors as shown in Fig.

2.2.The proposed DVCC is also a versatile building block for
application demanding floating inputs. CMOS realization of
this block is given in figure 2.2.

Figure 3.3 shows output Current relation at terminal Z1+, Z2+

and Z1-. In this case making Vin1 constant and varying Vin2
the current responses can be observed. This clearly shows that
currents variations are linear between -1V to +1V. The gain
of output current at terminal Z2+ and Z1- is three times of
current at X terminal, and the gain of output current at Z1+
terminal is same as the gain of current at X terminal.

All transistors operate in saturation region and the sources are

connected to bulk/substrate. Transistor M5 and M6, work as a
current mirror which are set to drive two differential amplifier
consist of transistors M1, M2, M3 and M4. This forces to give
relation in equation (2.1). Transistor M7 and M12 provide the
necessary feedback action to make the voltage Vx independent
of current drawn from the terminal X. The current through
terminal X is conveyed to the Z1+ terminal with the help of
transistor M7, M8, M12 and M13. And the current through
terminal X is conveyed to the Z2+ terminal with the help of
transistor M7, M8, M9, M12, M13 and M14. By using extra
current mirror the current is conveyed in an inverted manner
to the Z1- terminal.

AC Analysis of Novel DVCC

AC analysis of proposed DVCC has also been done and
simulation result is given in figure 3.4 and 3.5. Figure 3.4
verifies the voltage relation between input nodes. It also shows
the range of frequency suitable for operation, it shows that
frequency up to 200MHz the voltage relationship is fine.

3. Simulation Results of NOVEL DVCC

Figure 3.5 shows that current relationship is also satisfied up

to the frequency of 200 MHz. The gain of output current at
terminal Z2+ and Z1- is three times of current at X terminal, and
the gain of output current at Z1+ terminal is same as the gain of
current at X terminal as given in equations (2.3, 2.4).

DC Analysis of Novel DVCC

PSPICE simulation on the CMOS implemented circuit of
modified DVCC, using level 3 model parameter give the good
agreement with the theoretical results. Figure 3 .1 shows the
DC characteristic of proposed DVCC; it shows that when DC
voltage of 100mV applies at input node Y1 (V1) and 60mV at
node Y2 (V2), it gives the 40mV at node X (V3). In this way it
verifies the voltage relationship of equation (2.1).

Transient Analysis of Novel DVCC

PSPICE simulation is also carried out for sinusoidal inputs.
These results also give a good agreement between theoretical
and experimental results. These results also verify the basic

13

International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011

equation (2.1, 2.3 and 2.4) for DVCC in time domain in Figure
3.6 and 3.7

Author:
Kamlesh Kumar Singh is presently Asstt.Prof. in the
department of Electronics and Communication Engg., Amity
University Uttar Pradesh, Lucknow,India, He is also a
research scholar in Dept. of Electronics, Dr. R. M. L. Avadh
University, Faizabad . He received his M.Tech. Degree in
Electronic Design and Technology from U.P. Technical
University, Lucknow, India, in 2003.Before joining Amity
University, he also worked in Integral University as an Asstt.
Prof.in department of Electronics Engg. In 2000, he also
worked at Central Scientific Instruments Organization (CSIO),
Chandigarh, as an project scholar. He has been actively
involved in the field of Technical Education as Academician,
Researcher, Teacher, Planner and Administrator. He has
guided several M.Tech. and B.Tech. students in Electronics
Engg. discipline. He has also co-ordinated Front End VLSI
design Program

4. CONCLUSION
A new technique is proposed in this paper. A new low voltage
CMOS realization of proposed DVCC has been described. The
circuit is based on voltage and current mirror circuits.
Simulation results using PSPICE program exhibit that the
presented circuit design offers practical alternative solution to
use the CMOS DVCC in application circuits instead of the
DVCC elements. where experimental results show improved
performance in terms of dynamic range and power
consumptions compared with previous solutions .The circuit
provides high performance in terms of Low voltage and
current transferring, frequency response and linearity.

5.FIGURES
100mV
Vy2

Vy1

V
O
L
T
A
G
E

50mV

Vx

0V
0s
V(1)

V(2)

5us
V(3)

10us

15us

20us

Time

Figure 3.1 Various Voltages Responses

1.0V

V
x

0V

-1.0V
-1.0V
V(3)

-0.5V

0V
VIN2

Figure 3.2 Input Voltage Relations with Vx

14

0.5V

1.0V

International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011

400uA
Iz2+

C
U
R
R
E
N
T

Iz1+

0A
Ix

Iz1-400uA
-1.0V
I(R1)

-0.5V
I(R2)
I(R3)

0V

0.5V

1.0V

I(R4)
VIN2

Figure 3.3 Output Current Responses

3.0V
Vy2

Vy1

V 2.0V
O
L
T
A
G
1.0V
E

Vx

0V
1.0Hz
V(1)

V(2)

1.0KHz
V(3)

1.0MHz

500MHz

Frequency

Figure 3.4 Frequency Responses of Voltages

300uA
Iz1-

C 200uA
U
R
R
E
N
T 100uA

Iz2+

Iz1+

Ix
0A
1.0Hz
I(R1)

I(R2)

1.0KHz
I(R3)
I(R4)
Frequency

1.0MHz

Figure 3.5 Frequency Responses of Various Currents

15

500MHz

International Journal of Advances in Engineering Sciences Vol.1, Issue 2, April, 2011

100mV

V
O
L
T
A
G
E

Vy1

Vy2

Vx

0V

-100mV
0s
V(1)

5us
V(3)

V(2)

10us

15us

20us

Time

Figure 3.6 Various Voltages Responses

20uA

C
U
R
R
E
N
T

Iz2+

Iz1-

Ix

Iz1+

0A

-20uA
0s
I(R1)

5us
I(R2)

I(R3)

10us
I(R4)
Time

15us

20us

Figure 3.7 Input/Output Current Responses

[6] S. A. Mahmoud, M. A. Hashiesh, A. M. Soliman, Lowvoltage digitally
controlled fully differential current conveyor, IEEE Trans. on Circuits and
Syst.-I, vol. 52, No. 10, pp. 2055-64, Oct. 2005.
[7] R. Senani, Novel circuit implementation of Current Conveyor using
operational amplifier and OTA, Electronics Letters, vol. 16(1), pp. 2-3,
1980.
[8] . Sedra, and K. C. Smith, A second generation current conveyor and its
applications, IEEE Trans., vol. CT-17, pp. 132-134, 1970.
[9] S. Maheshwari., High CMRR wide bandwidth instrumentation
amplifier using current controlled conveyors, International Journal of
Electronics, vol. 89 (12), pp. 889-896, 2002.
[10] S. S. Gupta and R. Senani, CMOS Differential Difference Current
Conveyors and Their Applications, IEE Proc Circuits Devices Systems,
vol. 148, pp. 335-336, 2001.

6. REFERNCES
[1] K. Smith and A. Sedra, The Current Conveyor-a new circuit building
block, IEEE Proc., vol. 56, pp. 1368-1369, 1968.
[2] S. S. Rajput and S. S. Jamuar. "Low voltage. Low power high
performance current mirror for portable analogue and mixed mode
applications". accepted in IEE Proceedings. Circuits. Devices and Systems.
[3] B. Wilson, Trend in current conveyor and current-mode amplifier
design, Int. J. Electron., vol. 23, pp. 573-583, 1992.
[4] H. 0. Elwan. and A. M. Soliman. "Low voltage. low power CMOS
current conveyors". IEEE Trans. Circuits and Systems-I, vol. 44. 110. 9.
pp. 828-835. Sept. 19973, pp. 573-583, 1992.
[5] D. R. Bhaskar, V. K. Sharma, M. Monis and S. M. I. Rizvi, New
current-mode universal biquad filter, Microelectronics Journal, vol. 30,
pp. 837-839, 1999

16