IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO.

1, JANUARY 2001 147

All-MOS Voltage-to-Current Converter

Bahram Fotouhi, Member, IEEE

Abstract—A new resistorless voltage-to-current converter

utilizing only MOS transistors to achieve voltage-to-current
conversion with less than 0.5% nonlinearity is described. The
circuit uses MOS transistors in linear and saturation regions to
produce an output current linearly related to the input voltage.
The output current is proportional to the carrier mobility tracking
the process variations. This circuit is suitable for submicron tech-
nologies where the availability of a linear resistor with moderate
sheet resistance is not guaranteed. The circuit is fabricated using
0.6- m n-well CMOS technology, consumes less than 200 A, and
occupies 200 mm2 of area.
Index Terms—Resistorless CMOS current reference, VCO,
voltage-to-current converter.

I. INTRODUCTION

I N A CONVENTIONAL voltage-to-current (VTC) con-

verter, an input voltage is impressed across a resistor
through a high-gain operational amplifier (OPAMP) [1], as
shown in Fig. 1. The current in the resistor is sensed and
mirrored by the current mirror MP1/MP2 to generate the
output current. For good linearity, a resistor with small voltage
coefficient such as a poly-silicon resistor should be used. The
variation of the absolute value of the output current tracks
the sheet resistance variation of the polysilicon which could be
as much as 25%. Also, since the polysilicon resistor will not
be exposed to the same process variations as the MOS tran-
sistors in the rest of the integrated circuit chip, some tracking
problems may occur. For example, if the VTC converter is part
of a voltage-controlled oscillator (VCO) in a phased-locked
loop (PLL) circuit, the resistor process variations may cause
the center frequency of the VCO, and thus the lock range of the
PLL, to shift to higher frequencies. Since the MOS transistors
comprising the predivider circuits following the VCO in the
PLL will not experience the same process variations as the
resistor, their maximum operational frequency may be less than
the maximum frequency of the VCO. If the frequency of the
VCO exceeds the maximum frequency of the predivider, the
PLL loses lock and a lock-up condition occurs where the VCO
will free-run at its maximum frequency.
This paper describes a new VTC converter circuit that uses
only MOS transistors. The resistor in the conventional VTC con-
verter is replaced by two MOS transistors, one operating in the
linear region and the other in the saturation region. Although
the drain currents in each of the transistors are nonlinear func-
tions of the input voltage, their sum is made to be linear over
a wide range of input. Since the output current is proportional
to the carrier mobility, its variation with process will also be
Manuscript received April 7, 2000; revised August 29, 2000.
The author is with Advanced Communication Products, EXAR Corporation,
Fremont, CA 94538 USA (e-mail: bahram.fotouhi@exar.com).
Publisher Item Identifier S 0018-9200(01)00445-0.
0018–9200/01$10.00 © 2001 IEEE
Fig. 1. Simplified schematic diagram of voltage-to-current converter using
resistor.
equal to the variation of mobility or about 15%. The all-MOS
VTC converter is suited for submicron digital processes where
large-valued linear resistors may not be available.
The basic theory behind the operation of this new circuit is de-
scribed in Section II. Section III outlines the conceptual circuit.
The final circuit is described in Section IV. The performance
characteristics data of the new VTC converter are reported in
Section V.
II. BASIC THEORY
A previous work on resistorless CMOS current reference [2]
uses a single nMOS transistor in the linear region to generate an
output current. The new VTC converter produces an output cur-
rent which is the sum of the currents in two MOS transistors op-
erating in linear and saturation regions. Although the individual
currents in the two transistors are nonlinear, their combined cur-
rents are designed to be linear. This may best be appreciated by
starting with the mathematical equations describing the current
in the MOS transistors. The drain current of a MOSFET in the
linear region is given by [3]
(1)
where , is the carrier mobility, is the gate
capacitance per square centimeters, is the channel width,
is the channel length, and are the gate-, drain-,

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148 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001

Fig. 2. Conceptual diagram of the new voltage-to-current converter.

Fig. 3. Simplified schematic diagram of all-MOS voltage-to-current converter.

and bulk-to-source and threshold voltages, respectively. is the where is given by

body effect factor and is the surface inversion potential.
Using a Taylor series to obtain a more simplified equation for (3)
drain current in the linear region, a LEVEL 3 model is obtained
[3]. The drain current is then given by The numerical value of is normally between 1.2–1.7. In this
design, a value of was chosen as a good compromise
(2) over process variation.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 149

Fig. 4. Detailed schematic diagram of all-MOS VTC converter.

The drain current of a MOSFET operating in the saturation The current is then as given in (2). Next, is buffered and
region, ignoring the channel-length modulation effect, is given level shifted by , and the resultant voltage is impressed across
by the diode-connected device M15. The current in M15, , is
then as given by (4). M16 multiplies the current in M15 by coef-
(4) ficient . By proper choice of aspect ratios of M19 and M16, the
output current will be linear as given by (6). Since the de-
Adding the currents in (2) and (4) vices M15 and M16 are extremely long channel-length devices,
their drain currents will track in spite of unequal drain-to-source
voltages. From Fig. 2, ,
, and thus .
This gives a value of which was found to be a good
(5)
compromise over process variations.
The simplified schematic of the new VTC converter is shown
Assuming that is equal to the input voltage, , and
in Fig. 3. The source follower transistor M18 forces the input
, and letting , (5) reduces to
voltage at the drain of M19. The voltage at node N17 is
(6) given by

By setting to be a fixed bias voltage, a linear re- (7)

lationship between and is obtained with as the pro-
portionality constant. The condition of can be The OPAMP will force node voltages N17 and N10 to be equal.
met by level shifting by and forcing it across , as Transistor M9 is a device with a large ratio biased by small
explained in the next section. current source so that

(8)
III. CONCEPTUAL IMPLEMENTATION
Fig. 2 shows the conceptual schematic of the circuit imple- Therefore
menting (6). Transistor M19 is biased in its linear region with its
gate at a fixed voltage and its drain-to-source voltage at . (9)

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150
Fig. 5. Schematic diagram of folded cascode OPAMP used in the VTC converter.
Assuming that the body effect of transistor M9 is negligible,
. Using (6) and (7)
(10)
Equation (10) is valid in the range of . . The output of OPAMP2 is thus biased at
The lower limit is set by the threshold voltage of M18 and the
upper limit by that of M9 as its gate approaches . As it can
be seen from (10), is proportional to the carrier mobility.
As explained before, the mobility dependence of is useful
in circuits such as the current-controlled oscillator (ICO). When
such an ICO is used in a PLL system, the mobility will set both
the maximum frequency of the ICO as well as the maximum op-
erational frequency of the digital predivider following the ICO.
This will eliminate the lock-up or free-running condition of the
ICO caused by the predivider inability to function at the max-
imum frequency of the ICO due to process variations.
IV. DETAILED CIRCUIT
To improve the lower limit on the input voltage range, an
OPAMP is used in conjunction with M18 to force at node
N17 without any additional voltage drop due to the threshold
voltage of M18 as given in (7). The complete schematic of
the all-MOS VTC converter is shown in Fig. 4. The gate of
transistor M19 is biased at a fixed voltage by MB5 and cur-
rent source MB3. The voltage is forced across the drain-to-
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001
source of transistor M19 by the source-follower transistor M18
and OPAMP1. OPAMP2 biases the source of M9 at the same
potential as the input voltage. A small current source consisting
of devices M10–M11 biases the large transistor M9 such that
and forced across the gate-to-source of the diode-connected
transistor M15. The ratio of M16 is 1.35 times that of
M15. This is the midrange value for the parameter as given in
(3) necessary to cancel the second-order effect as shown in (6).
Transistors M16, M17 and M20 then sum the currents in M15
and M19 to generate the output current .
OPAMPs 1 and 2 are simple p-channel input cascode ampli-
fiers, shown in Fig. 5, which provide high gain and input voltage
range that extends below the ground potential. This is necessary
to reduce the lower limit on the input range for linear operation.
The remaining transistors provide the necessary biasing for the
entire circuit.
V. EXPERIMENTAL RESULTS
Fig. 6(a) shows the simulation result for the currents ,
, and as well as the experimental data for taken
over 20 samples. Although the experimental data deviates from
the simulated results due to process variation of the , the
linearity of with is preserved. The drain current of
M16 changes quadratically with input voltage until it saturates
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 1, JANUARY 2001 151

(a)

Fig. 7. Large-signal transresistance of the all-MOS VTC converter.

(b)
Fig. 6. (a) Simulation and experimental data for output current versus input
voltage. (b) Plot of the linearity error in the output current of the VTC converter.

at V. The drain current of M19 starts linearly at

V and then saturates as transistor M19 enters its satura-
tion region with increasing . The output current , which
is the sum of drain currents of M16 and M19, increases linearly
starting at V and saturates at V. Also plotted
Fig. 8. Die photo of the all-MOS VTC converter.
in Fig. 6(a) is the output current of an ideal VTC converter given
as whose slope best matches that of
the actual VTC converter. The error between and is The total bias current of the all-MOS VTC converter is 200 A.
shown in Fig. 6(b). The large-signal transresistance defined as Fig. 8 shows the die photo of the VTC converter consuming
the ratio of is shown in Fig. 7. The nonlinearity of the 200 mm of area in 0.6- m n-well CMOS technology.
output current is caused mainly by the body effect factor of
M9 as given by the original equation (1). Figs. 6(a) and 7 show REFERENCES
that the nonlinearity is less than 0.5% over the input range of [1] R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for
0V 1.8 V in spite of the body effect factor . The Signal Processing. New York: Wiley, 1986, p. 450.
value of was changed from 1.4 to [2] H. J. Oguey and D. Aebischer, “CMOS current reference without resis-
tance,” IEEE J. Solid-State Circuits, vol. 32, pp. 1132–1135, July 1997.
1.7 to simulate the process variations. The effective nonlinearity [3] P. Antognetti and G. Massobrio, Semiconductor Device Modeling with
was less than 1.0% which is adequate for most applications. SPICE. New York: McGraw Hill, 1988, pp. 163–185.

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