A High Speed Low Power Pulse Swallow Frequency
Divider for DRM/DAB Frequency Synthesizer
Xuemei Lei1,2
1 1
Institute of RF- & OE-ICs, Southeast University,
Sipailou 2, 210096 Nanjing, China
2 3
Inner Mongolia University,
Daxuexilu, 010021Hohhot, China
nmglxm@sohu.com
ABSTRACT-The implementation of a high-speed low-power pulse
swallow frequency divider for a DRM/DAB frequency synthesizer,
using a 0.18-μm CMOS technology, is described. The frequency
divider employs a divide-by-32/33 dual-modulus prescaler, a five
bits swallow counter, an 11 bits programmable counter, and a control
circuit necessary for the time sequence and operation of the division.
In the pulse swallow frequency divider, the divide-by-32/33 dual-
modulus prescaler consists of a divider-by-4/5 and an asynchronous
divider-by-8 frequency divider, the swallow counter and the
programmable counter consist of static-logic fall edge-triggered
DFFs. The structure is designed to reduce the power consumption.
Post-simulated results show that the programmable divider’s
operation frequency is from 0.5 GHz to 3.5 GHz with a maximum
power consumption of 3.01 mW at 1.8V power supply. The
dimension of pulse swallow frequency divider is 270 μm×110 μm.
Keywords-Pulse Swallow frequency Divider, Prescaler, Swallow
Counter, Programmable Counter, DRM/DAB Frequency
Synthesizer, High Speed , Low Power.
I. INTRODUCTION
Among the blocks found in RF CMOS receivers, the
frequency synthesizer is one of the most important since it
decides the acceptance range of the frequency. In the
frequency synthesizer blocks, the operating frequency is
limited by the frequency divider and the voltage-control
oscillator (VCO), at the same time the VCO and the frequency
divider consume most of the circuit power. Now the wireless
communication scenario is dominated by the simultaneous
presence of a variety of standards covering different
applications and employing a wide range of frequency. The
frequency synthesizer must have a large divider ratio and a
wide frequency range. In consequence, design efforts to reduce
the power consumption and increase the range of frequency
should be a constant concern for the frequency divider and
VCO.
This work deals with the design of a CMOS 16 bits
programmable high-speed and low-power frequency divider
for DRM (Digital Radio Mondiale) [1]/ DAB (Digital Audio
Broadcasting) [2] frequency synthesizers. Dynamic circuit has
been employed in the design since it can work at a high speed
and static circuits have been employed to reduce the power
consumption and increase the range of operating frequency
simultaneously. The circuit is implemented in a 0.18 μm
CMOS technology of SMIC.
978-1-4244-5668-0/09/$25.00 © 2009 IEEE
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Zhigong Wang1,* , Keping Wang1,3 Xiaoxia Wang1
Institute of RF- & OE-ICs, Southeast University,
Sipailou 2, 210096 Nanjing, China
RF-IC&System Engineering Researching Center of
Ministry of Education of China
*Corresponding Author: zgwang@seu.edu.cn
In section II the pulse swallow frequency divider
architecture used to implement the frequency synthesizer is
presented. In section III, the pulse swallow frequency divider
is discussed. Results are shown in section IV, and finally the
conclusions are presented in section V.
II. THEORY OF THE PULSE SWOLLOW FREQUENCY
DIVIDER ARCHITECTURE
The pulse swallow frequency divider consists 4 parts, (see
Figure 1) including a divide-by-32/33 dual-modulus prescaler
(DMP), a 5 bits swallow counter (SC), an 11 bits
programmable counter (PC) and a control circuit (CC).
Figure 1 Architecture of the pulse swallow frequency divider
The operation of the pulse swallow frequency divider is as
follows: Firstly, initialize two counters. The programmable
counter and the swallow counter are initialized with the values
of P and S, respectively, where S < P and their values are
externally controlled. The modulus control (MC) signal is
controlled by the swallow counter, and the programmable
counter, through the swallow counter. Then, the input signal
from the VCO’s output (CLK) is divided by (32+1) through
the DMP. The other two counters count down, using the DMP
output (CLKOUT) signal as the clock. When the swallow
counter reaches zero and simultaneous holds, the MC flips and
the CLK signals in the DMP is divided by 32, at the same time,
the programmable counter still counts until reaching zero.
Then, two counters are reset and MC signal flips, the process
begins again. During the counting process, the DMP divides
the VCO clock S times in (32+1) mode, and (P-S) times in 32
mode. The total division factor of the divider will be N=
33×S+32×(P-S) = 32×P+S. At last, when the synthesizer is
locked, the output frequency of the VCO is: fosc= (32×P+S) ×
fref (fref is the frequency of a reference signal). In this
configuration, the output frequency of the VCO depends on the
programmed value S and P of the swallow counter and the The fractional division ratio of the prescaler is selected
programmable counter. While considering the proposed according to the MC signal value: 32 (MC = high) or 33 (MC
DAM/DAB frequency synthesizer with the nominal frequency =low).
of 3 GHz and the reference frequency of 600 kHz, the suitable
values to configure the divider are as follows: B. Swallow Counter
• The prescaler dividing factor of 32 or 33;
• The programmable counter with P value between 32 and
4095;
• The swallow counter with S values between 0 and 31.
The frequency of the VCO output may contain 64512
frequency points such as 1024×fref, 1025×fref… or 65536×fref,
according to the value of S and P. But in DRM/DAB
frequency synthesizer, the VCO output frequency is equal to

CLK
5000×fref in this case.
Figure 4. Schematic of the swallow counter

III. THE PULSE PULSE SWOLLOW FREQUENCY DIVIDER
IMPLEMENTAION
In this section we will describe the proposed pulse swallow
frequency divider in detail. The blocks of the pulse swallow
frequency divider are: a divide-by-32/33 dual modulus
prescaler, a divide-by-32, 33…4095 programmable counter, a
divide-by-0, 1…31 swallow counter, and a control circuit.
A. Dual-Modulus Prescaler
The swallow counter of this work is implemented with a 5-
bits programmable counter, a combination-logic circuit, and a
sample latch. The 5 bits programmable counter counts the
pulse signal and provides the input signals to NOR gate of 5
input ports. The output signal of NOR gate is sampled by the
latch as MC signal to make the fractional division ratio of the
prescaler is 32 or 33. At the same time the signal gives the
control port of transmission gate as the control signal to give
the clock signals to the programmable counter. The enable
signal controls the time to make the programmable counter
preset the value of S0, S1, S2, S3 and S4. Figure 5 shows the
timing and transition state diagrams of the control signals and
swallow counter.

Figure 2. Architecture of the dual modulus prescaler

The dual-modulus prescaler of this work is implemented

with SCL (source-coupled logic), TSPC (true-single-phase-
clock) [3], and static logic technique. Figure 2 shows the
architecture of the dual modulus prescaler. In this diagram two
blocks can be identified: the first block is composed of three
SCL fall edge-triggered D-flip flops (D-FF) without external
logic gates, which is a synchronous divide-by-4/5 counter. The Figure 5. The timing and transition state diagrams of the control
signals and the swallow counter
second block is composed of one TPSC and two static fall
edge-triggered DFFs, which is an asynchronous divide-by-8 C. Programmable Counter
counter. The Vc signal, generated by the MC signal and the
asynchronous counters output signal through NOR gate of 4
input ports, selects if the divide-by-4/5 counter counts up to 4
PCOUNTER(11bit)

(Vc = high) or up to 5 (Vc = low). Figure 3 shows the timing

and transition state diagrams of the synchronous divide-by-4/5
divider respectively.

Figure 3. The timing and transition state diagrams of the synchronous

divide-by-4/5 divider Figure 6. Schematic of the programmable counter

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 The PC consists of an 11-bit programmable counter,
several combination circuits, and a latch. The programmable
counter is based on a chain of 11-bit asynchronous preset
static-logic divide-by-2 divider. Other circuits contain 2 NOR
gates of 3 input ports, 2 NOR gates of 4 input ports, 2 NAND
gate of 3 input ports, a NOT gate and a latch as shown in
Figure 6. The number of counter can be changed in the
programmable counter by presetting the value of P0, P1…P10
when the enable signal is high as same as swallow counter.
The output signal (COUT) is low when the Q4, Q5…Q9 and
Q10 is low. And the enable signal is high and holds a clock
cycle by the latch when the programmable counter reaches
zero. Figure 7 shows the timing and transition state diagrams
of the enable signals and clock signal.

Figure 9. Transient simulating result of the pulse swallow frequency divider

The layout of pulse-swallow divider used in this work is

shown in Figure 10. And the post-simulation result of transient
is shown in Figure 11.

Figure7. The timing and transition state diagrams of the enable

signal and clock signal

IV. THE SIMULATION RESULT

The principle of the proposed pulse swallow frequency
divider is as mentioned above. The divider factor of the pulse
swallow frequency divider is controlled by the value of the S0,
S1…S4 and P0, P1…P10. If S1, S2, S3, S4, P2, P5 and P6 are
high and others are low, the divider factor of pulse swallow
Figure 10. Layout of the pulse swallow frequency divider
frequency divider is equal to 3294 (32×102+30). When the
frequency of input signal is 3.5 GHz, the result of transient
simulation is shown in Figure 8. When the frequency of input
signal is 0.5 GHz, the result of transient simulation is shown in
Figure 9.

Figure 11. Transient post-simulating result of the pulse swallow

frequency divider

Figure 8. Transient simulating result of the pulse swallow frequency divider
V. CONCLUSION
A high-speed CMOS 16-stage programmable pulse
swallow frequency divider with low power consumption is
presented. The pulse swallow frequency is implemented in
SMIC’s 0.18-μm CMOS technology process. The simulated
results show that the pulse swallow frequency divider has a
range of operating frequency from 0.5 GHz to 3.5 GHz, the

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static power consumption of pulse swallow frequency is 2.14
mW and the average power consumption is 3.01 mW at 3.5
GHz with 1.8 V supply voltage. Among them the average
power consumption of the DMP is 2.51 mW, the average
power consumption of the PC is 0.35 mW, and the average
power consumption of the SC is 0.09 mW. A comparison of
this divider with other recently published results was provided
in Table I. It is shown that the proposed structure has the
lowest power consumption and the largest range of
programmable divide ratio. The presented pulse swallow
frequency divider is particularly suited to multi-standard, ultra-
wideband, low-power consumption frequency synthesizer.
TABLEⅠ. COMPARAISION WITH PUBLISHED RESULTS
Technology Operating Number of Power
process frequency programmable consumption
range (GHz) stage (mW)
0.18μmCMOS[4] 2.4 or 5 9 2.6 or 3.275

0.35μmCMOS[5] 2.6 4 3.39

0.18μmCMOS[6] 3 -- 3.58
This work
0.5-3.5 16 3.01
0.18μm CMOS

REFERENCES
[1] ETSI ES 201 980, “Digital Radio Mondiale (DRM); System
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[2] ETSI EN 300 401, “Digital Audio Broadcasting (DAB) to Mobile,
Portable and Fixed Receivers,” 2001.
[3] Ji-Ren, Y., Karlsson, I., and Svensson, C. A true singlephase-clock
dynamic CMOS circuit technique. IEEE J.Solid-State Circuits, 22, 5
(Oct. 1987), 899-901.
[4] Ko-Chi Kuo , Feng-Ji Wu. A 2.4-GHz5-GHz Low Power Pulse
Swallow Counter in 0.18-μm CMOS Technology. IEEE Asia Pacific
Conference on Circuits and Systems 2006, 214-214.
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A 3.5 mW Programmable High Speed Frequency Divider for a 2.4 GHz
CMOS Frequency Synthesizerprescaler using the extended true-single-
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