201O International Conference on Computer Application and System Modeling (ICCASM 2010)
A Programmable High-speed Pulse Swallow Divide-by-N Frequency Divider For
PLL Frequency Synthesizer
Zhiqiang Gao
Department of Electronic Information Science and
Technology
Harbin Institute of Technology
Harbin, Heilongjiang 150001, China
gao zhiqiang007@126.com
_ xuyuanxu 2008@sina.com
Abstract- The implementation of a high-speed pulse swallow
frequency divider for a PLL (Phase Locked Loop) frequency
synthesizer, using a 0.18,.m CMOS technology and operating
with a 1.8V power supply, is described. The frequency divider is
used as a scalable programmable divide-by-N frequency divider.
It employs a divide-by-8/9 dual-modulus prescaler,
programmable counters, and a control circuit necessary for the
time sequence and operation of the division. In the pulse
swallow frequency divider, the divider circuit is attractive for
the large range of programmable divide ratio from 120 to 400
since the architecture is based on using an original design of
D-type Flip-Flop (DFF) with synchronous number-set and clear.
Post-simulated results show that the programmable divider's
operation frequency is from 0.75 GHz to 2.2 GHz with steep
pulse output wave-form , providing a stable clock edge of the
required frequency for the PLL frequency synthesizer.
Keywords- pulse swallow frequency divider, the large range of
programmable divide ratio, original design of D-type Flip-Flop,
PLL
I. INTRODUCTION
In the past ten years, with the growing development of
techniques in computer, communication, digital TV, G PS,
radar, navigation, aero-space, and telecontrol measure, there
has been an increasing demand for frequency stability,
frequency spectrum purity, frequency range and number of
output frequency in frequency source. In order to improve
stability of frequency, one of the popular methods to generate
frequency of high quality is the Phase-locked Loop ( PLL)
frequency synthesizer. Frequency synthesizer is a crucial unit
in modem electronic system [1,2], which generates one or
many frequencies from one frequency source. Frequency
synthesizer is widely applied in areas of information industry,
for example large-scale digital system such as
microprocessor and video image processor, baseband
sampling circuit and analog front-end circuit in the
communication system, etc, and its market has been growing
explosively.
The development of the applications of PLL frequency
synthesizer brings an increased demand for configurable,
wide-band and multi-frequency output PLL frequency
978-1-4244-7237-6/10/$26.00 ©2010 IEEE
Authorized licensed use limited to: Synopsys. Downloaded on July 09,2021 at 06:11:17 UTC from IEEE Xplore. Restrictions apply.
Yuanxu Xu, Peng Sun, Enyi Yao, Yongshuang Hu
Department of Electronic Information Science and
Technology
Harbin Institute of Technology
Harbin, Heilongjiang 150001, China
_
synthesizers. One of the key parts is the programmable
divider. In this dissertation, an example of programmable
divide-by-N divider for a communication processing system
is designed, whose input frequency ranges from 750MHz to
two 2.2GHz. The divider implements frequency demultiplication
of the input signal from 120 to 400 through software
programming. It provides a stable clock edge of the required
frequency for the PLL frequency synthesizer and meets the
requirements of configuration, broadband and
multi-frequency output eventually.
II. THE DESIGN OF DIVIDE-BY-N FREQUENCY
DIV IDER IN SY STEM
The divide-by-N frequency divider is in the feedback
loop of the Phase-locked Loop frequency synthesizer, thus it
will largely influence the performance of the whole system.
As is shown in Figure.1, the internal structure of the
frequency divider is composed of three parts: a divide-by-8/9
dual-modulus prescale divider, a 3-bit programmable S
counter (frequency divider) and a 6-bit programmable P
counter (frequency divider). It is a typical structure of a
programmable frequency divider. The dual-modulus prescale
divider adopts a pulse swallow technology to improve the
working frequency of the programmable divider. This
technology combines the dual-modulus prescale frequency
divider with a low speed stored program controlled
frequency divider to form a stored program controlled pulse
swallow frequency divider with a higher speed.
The working principal of the divide-by-N frequency
divider is described as follows: C8-CO are the 9 inputs to set
the frequency divider with a range from 120 to 400. The bits
of CO-C2 input the S frequency divider directly, and the bits
of C3-C8 are used to set the P counter. At the beginning, the
divide-by-8/9 dual-modulus prescale divider is at a kind of
high-mode state (divide-by-9), the input signal FVCO is
divided by 9 and output via FOUT, and the S and P counters
count the output of FOUT simultaneously. When S impulses
pass, the S counter reduces to 0, and the output of the S
counter via port CO changes to a low level from a high level.
V6-315
 2010 International Conforence on Computer Application and System Modeling (ICCASM 2010)

Thus the S/9 dual-modulus prescale frequency divider swifts
to a low-mode state (divide-by-S), then the P counter
continues to count. After a period of P-S impulses, a high
level impulse is output to initial the P counter. S counter and P
counter start to count again, and S/9 dual-modulus frequency
divider goes to the original state to start the next new cycle.
The frequency dividing ratio of the divide-by-N frequency
divider is S P+S.
circuits equivalent to some switchers to lock up the signal
and stop the S counter from working after it counts the period
of S and wait the next signal LOAD to stimulate it and make
it work again.
The kernel module of the two parts is the D flip-flop
which can be set and clear synchronously. Its working speed
has a crucial importance to the whole counting circuit. The
contemporary D flip-flop does not have the function to be set.

7VCO
IWSELeLK
8/9
rou,

I -J
eLK
Do l i SCO
And the most widely used D flip-flop is the TSPC D flip-flop
among the varies kinds of D flip-flops reported [4,S]. As is
D, shown in Figure.S, it is a conventional TSPC D flip-flop. This
r-- D,
LAOD design shown in Figure.6 is original to add some gates on the
foundation of the TSPC D flip-flop to enable it to be set and
clear at a high level.
C L-- �
c, VOUT OUT Vdd

£; D,
D,
g. D, liP
C. D;
C, D, QN
C, D, D.o--_--+
-
Figure 1. The Scheme of Divide-by-N Divider Structure CLKo--�-+-I

III. CIRCUIT DESIGN

The schematic of S/9 dual-modulus prescale frequency
Figure.5. The conventional TSPC D flip-flop
divider [3] is shown in Figure.2. It is composed of four D
flip-flops, two NAND gates, a NOR gate with 3 inputs and
three inverters. The first two D flip-flops work in a CLK _____--,

synchronous state, and the other two D flip-flops work in

asynchronous states. Each DFF is a divide-by-2 divider. '--___ �CLK
When SEL is at a low level, the NOR and the NANDS which Q

are connected with the NOR will be locked up, and the last 3 S
LOAD
D flip-flops make up a divide-by-S divider; when SEL is at a
high level, the NOR is unlocked, and then all of the gates and
flip-flops compose the divide-by-9 divider.
Figure.6. DFF with synchronous number-set and clear

The working speeds of different parts of the

eLK

divider-by-N frequency divider are different. It needs to

SEL
Figure 2. The Divide-by-8/9 Dual-modulus Prescaler
As is shown in Figure.1, the S and P counters are two
programmable frequency dividers in fact, which work in
coordination to perform the programmable function of the
divider-by-N frequency divider. The schematics of the S and
P counters are shown in Figure.3 and Figure.4 separately. The
principal of the two parts are the same: A counter, which is
based on the foundation of a subtractor, is set and counts
again after it reduces to O. The two frequency dividing
circuits' outer interconnection wires and ports are different.
The S frequency divider is more complex, which needs some
separate the switching currents reasonably and to design a
best working point for each transistor making it far away
from its saturation region.
Finally, we made a simulation of the N frequency
divider with the frequency dividing ratio from 120 to 400 one
by one covering the lowest frequency of 7S0MHz and the
highest frequency of 2.2GHz. Looking at Figure.7 and
Figure.S, we can see the outputs are the pulse wave at the
frequency of S.SMHz and 6.2SMHz, which has satisfied the
design requirement of the divide ratio from 120 to 400. As is
shown in Figure.9, it can provide an accurate perfect clock
edge drive for the following circuits, such as the D flip-flop.
IV. CONCLUSION
In this paper, a pulse swallow frequency divider for a
high speed is presented along with a new proposed

V6-316

Authorized licensed use limited to: Synopsys. Downloaded on July 09,2021 at 06:11:17 UTC from IEEE Xplore. Restrictions apply.
 2010 International Conference on Computer Application and System Modeling (ICCASM 2010)

architecture of a programmable counter based on an original [2] L.Kyoohyun,et.a1.,A Low-Noise Phase-Lock Loop Design by Loop
Bandwidth Optimization,IEEE, Journal of Solid-State
design of D-type Flip-Flop with synchronous number-set and Circuits,2000,35:807-815
clear. The divider structure is implemented for a size of 9-bit, [3] Zhang Tao, Modeling,Design and Implementation of Phase-locked
which provides varied frequency dividing factors from 120 to Loop Frequency Synthesizer, Wuhan: Huazhong University of

400. The pulse swallow frequency is implemented in Science and Technology, 2006

TSMC's 0.18-J.lm CMOS technology process. The simulated [4] Jan Craninckx and Michiel SJ.Steyaert,A 1.75-GHzi3-V
Dual-Modulus Divide-by-128/129 Prescaler in 0,7-llm CMOS.IEEE,
results show that the pulse swallow frequency divider has a Journal of Solid-State Circuits,1996,31:890-897
range of operating frequency from 0.75 GHz to 2.2 GHz with [5] Q.Huang and RRogenmoser,Speed Optimization of Edge-Troggered
steep pulse output wave-form, providing the perfect edge of CMOS Circuits for Ggahertz Single Phase Clocks.IEEE, Journal of
Solid-State Circuits, 1996,31:456-465
the clock.

REFERENCES
[1] A.Young,et.ai,A PLL Clock Generater with 5 to 110 MHz of Lock
Range for Microprocessors,IEEE, Journal of Solid-State
Circuits,1992,27:1599-1607

VIN
-S
ClK
C --v J::�
�S
ClK
Q
j � rp a,
"'-'" -;::L>-
_ s
Q � �
N
Co

D0-
ID QNl
'I(

I
LOA[

ID I1 LO
�:l ID Ij QNl
lOAD

D,

D2

LOAD
Figure 3. The S Counter

��----�+-----��---+--�--4-�

Figure 4, The P Counter

V6-317

Authorized licensed use limited to: Synopsys. Downloaded on July 09,2021 at 06:11:17 UTC from IEEE Xplore. Restrictions apply.
 2010 International Conference on Computer Application and System Modeling (ICCASM 2010)

Figure.7. The wave of input 2.2GHz, divide-by-400

Figure.8. The wave of input 750MHz, divide-by-120

../"....
I
--+------ ------ -----+--1

-...-___ ..... ......... +-................_.............i_--l........•

....._ ..............._...... .l. _........................... ......... ....••......_......•.

Figure.9. The magnified pulse wave

V6-318

Authorized licensed use limited to: Synopsys. Downloaded on July 09,2021 at 06:11:17 UTC from IEEE Xplore. Restrictions apply.