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Transactions on Computer Science and Technology
December 2013, Volume 2, Issue 4, PP.69-76
The Development of the Digital Oscilloscope
Based on FPGA
Gang Luo
1
, J ie Peng
2

,

Lu Ma
2
, Fei Yuan
2
, Yuanyuan Mao
2

1. Chengdu Technological University, Chengdu Sichuan 611730, China
2. University of Electronic Science & Technology of China, Chengdu Sichuan 611731, China

Email: 737466345@qq.com
Abstract
The system design is based on FPGA digital oscilloscope, using a unified and specified operational amplifier chip A/D converters,
complete conditioning and collection, using Spartan-3E FPGA control chip with high-speed analog-digital high-speed data
acquisition, storage and transmission, using SOPC embedded soft-core form. Seven-segment LED display block with on-board
display of the input signal and the peak frequency value. Since program uses SOPC technology, soft-core processor and
high-speed digital circuits integrated in a FPGA chip to form a programmable system on chip. Thus, the entire system has higher
processing speed, flexible configuration, high reliability, and flexible change of scene.
Keywords: Digital Oscilloscope; FPGA; SOPC; High-speed Acquisition; LED
1 INTRODUCTION
The DSO, short for the digital storage oscilloscope, has been developed a new type of oscilloscope
[1]
with the
development of the digital technology. Digital storage oscilloscope not only applies to the measurement of the
repeated signal, but also applies to the detection of the single transient signal. Because the digital storage
oscilloscope introduced the digital signal processing technology and storage technology, thus making its very
effective for the recording store and researching analysis of the complex single transient signal. However, the
traditional oscilloscopes are difficult to achieve. At present, the digital storage oscilloscope market mainly focus on
foreign technology. With the development of digital storage oscilloscope, the Tektronix Company is in the lead,
followed by the Agilent Company and the LeCroy Corporation. Such as the Tektronix TDS7000 series, the highest
analog bandwidth is GHz 4 , and the highest real-time sampling rate of s GS / 200
[2]
, up to the storage depth of the 32
Mega-samples.
But as a result of high price, digital storage oscilloscope lead to a large market space of the analog oscilloscope,
especially in teaching experiments, and the analog oscilloscope are equipped with M 20 or so. With the rapid
development of high speed universal device, the A/D, FPGA, DSP, CPU and other high speed chip have obvious
improvement on speed and integration, and the price of the device is also greatly reduced, which indicating the
digital storage oscilloscope will have the greater popularity. Therefore, with the adopting of the most advanced
integrated circuit element, as much as possible of the oscilloscope function, especially the digital processing function
design is a very meaningful attempting on the highly integrated programmable chip.
2 THE DESIGN STRUCTURE DIAGRAM OF THE DIGITAL STORAGE
OSCILLOSCOPE BASED ON FPGA
According to the analysis of the system performance, the system design is mainly divided into the following five
parts: the recuperating module of the front signal, signal acquisition module, FPGA control signal sampling
module, storage and transmission module, the real-time display and storage module of the data signal
[7]
. As
shown in figure 1.
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The signal recuperating circuit conduct front-end waveform signal processing by adopting high-speed op-amp
AD811. The high-speed A/D device use of the TLC5510 chip of the TI company, of which highest sampling rate up
to S MSa / 20 . FPGA adopted NEXYS2 device can conduct internal FIFO structure and satisfy the temporary storage
of the sampling signal. Single chip microcomputer controls FPGA by using soft core which leads to conducting
sampling and transmission, and conduct the real-time display of the waveform signal by controlling the LED.

FIG. 1 THE STRUCTURE BLOCK DIAGRAM OF THE DIGITAL STORAGE OSCILLOSCOPE BASED ON FPGA
3 THE MODULE DESIGN OF THE OVERALL CIRCUIT
3.1 A/D Front-end Signal Processing and A/D Circuit Module
According to the sampling theorem, when
in
f
s
f 2 >= , namely, the A/D sampling rate is greater or equal to twice
the signal frequency
in
f , it can only reconstruct waveform without distortion
[4]
.
In order to meet the requirement of the input voltage in the range of the A/D measurement, it must carry on the
front-end signal processing of the input signal, namely, the signal disposal. This design conducts an appropriate
voltage offset and amplifies for sampling signal by sampling of high-speed op-amp AD811, then inputs into the
TLC5510s simulation input after it via the RC low-pass filter, which completes signal acquisition front-end
processing. The AD811 can handle up to MHz 140 bandwidth of the signal, the minimum setup time is 25 ns, and
power supply noise is only Hz nV / 9 . 1 , which is very suitable for using in this design.
Due to the demand of the A/D relied on the signal power is too high, this design carries out on the power supply
filtering by adoptingt type filter network. The measured results indicate that power supply ripple is very small,
which has reached the requirement of the design.

FIG. 2 A/D ACQUISITION CIRCUIT COMPOSED OF TLC5510
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3.2 The FPGA I nternal RTL Circuit Structure
FPGA using NEXYS2 instrument
[8]
, and its crystal vibration frequency up to MHz 50 , and the plate uses
Mbytes 16 high-speed SDRAM and Mbytes 16 Flash ROM, enable it to fully compatible with an embedded processor.

FIG. 3 THE FPGA CONFIGURATION CIRCUIT
Because the data of FPGA is lost without power-fail, it will not saving code after burning off electric. However, we
need to add configuration circuits, which are shown in figure 3.
1) MCU soft core controlling FPGA sampling, display and data storage
The FPGA internal circuits include real-time sampling circuit, the equivalent sampling circuits, sampling way
selected circuit, equal precision frequency measurement circuit, the embedded processor core and other ancillary
logic circuit, etc.
Due to the sequential sampling principle, once the first trigger event comes, it immediately collects the first sampling
point, and puts it in the storage. A second trigger is used to start a timing system, and the timing system will produce
a very small time delay t A . After the t A time delay, it will be again to collect the second sampling point. The time
resolution of the display memory is equal to the small delay time t A , its value directly reflects the sampling rate of
the equivalent sampling. When a third trigger event arrives, the timing system produces t A 2 delay time. Collecting
the third sampling point after this delay time, and proceeding according to this rule. That is to say, the first sample
point is on the left of the screen, and then the vary sampling points in turn form a waveform which displays to the
right. The equivalent sampling rate is: f. In this design, ns t 5 = A , namely, the equivalent sampling rate is 200M. It
is derived from the 4 times frequency of the FPGA internal phase-locked loop
[9]
(PLL). Equivalent sampling circuits
include PLL module, A/D sampling sequence controller module and FIFO memory module. The FIFO memory
module and real-time sampling circuit FIFO are Shared each other and they are used interchangeably by data
selector.
MCU is the main core in this design, it is mainly responsible for the commanding FPGA sampling and making the
sampling data storage into memory, and calling the drawing program so that display sampling signal. When any
touch screen buttons is pressed, according to the value of the pressed key, it turns into corresponding processing
subroutine, the overall application process is shown in figure 4.
2) Parameter measurement
Signal peak-to-peak value measurement: is actually the measurement between the maximum and the minimum of the
sampling data, namely, how many points between their values? and then converting points into the actual voltage
value. Specific algorithm is as follows: MCU loading A/D sampling data from the FPGA is divided into four times
[3]
,
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the first three times, it reads 80 data every time, the last time, it reads16 data, a total of 256 data. To solve the largest
value and minimum value after it reads out every times, put it as the next maximum value and minimum value to be
read. After four times, it can choose the largest value and minimum value of the 256 data. The maximum value
minus the minimum, you can get the points of their difference. Because the vertical resolution is div mv / 150 , it can
calculate peak-to-peak value according to the following formula, i.e.
( ) ( ) | | A
pp
v - = 8 / 255 / min max

FIG. 4 MCU PROGRAM FLOW CHART AS A WHOLE
Among them, Max is the maximum of the waveform data, Min is the minimum of the waveform data, A is the
vertical resolution, unit is div mv / .

FIG. 5 MCU TIMER AND COUNTER MEASURING FREQUENCY PROCESS
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Signal frequency measurement: the signal frequency measurement method of the design adopted the hardware
design measurement. Namely, the input waveform via Schmidt trigger changes into a standard square wave, and the
input to the single chip timer/ counter, then using a timer timing, the meter method of the frequency counter conduct
the frequency measurement of the input signal
[10]
. MCU
0
T is set to counter work way (for 16-bit counter, counter
initial value is set to 0), T1 is set to the timer work way (for16-bit counter, interrupt once every ms 4 ). Then it
calculated the frequency values according to the following formula, i.e.

0
65536 65536
0 0 L
T
H
T
count
T Frequency + + - =
Among them,
count
T
0
is count times of the
0
T ,
0 H
T is high eight value of the
0
T ,
0 L
T is low eight value of the
0
T ,
The software flow chart are shown in figure 5.
4 SINE WAVE GENERATOR HARDWARE DESIGN
4.1 The Design of the Single Chip Microcomputer Minimum System
This design uses AT89S52 single chip micro- computer as main control chip. Single chip micro- computer minimum
system consists of a single-chip microcomputer and reset circuit. The frequency of the oscillation circuit mainly
depends on the crystal oscillator frequency, and the average crystals frequency can choose between MHz 12 2 . 1 , and
we adopt MHz 12 crystal vibration in this design. Capacitor C1, C2 can choose between pf 30 5 , and the size of
the capacitor has a tiny influence on oscillation frequency, which can play a role in frequency fine tuning. Power on
reset is that the single-chip turn on power supply and the single-chip microcomputer is reset. Resistance capacity
parameters of the reset circuit is usually adjusted by the experiment, and the circuit parameters C is generally f 22 ,
R1 take k 1 , but it offer enough high level pulse on the Vpd RST / end, make SCM can reliable on the automatic
reset.
4.2 The Waveform Signal Producing Part of the Circuit Design
The basic principle producing part of the waveform signal: the P1 port of the single-chip microcomputer outputs a
digital signal, then the digital signal becomes continuous current signal
[15]
through the DAC0832. The negative input
terminal of the first stage operational amplifier connect DAC0832
1 out
L end, and the positive input terminal
connect
2 out
L end. The reason for adopting two stage operational amplifiers is that it can realize inverting function,
and it can appear the positive and negative value of the waveform. For example, when the v
ref
v 5 + = , the range of
the output voltage of the
1
A is 05v. When v
out
V 0
1
= , v
out
V 5
2
= . When v
out
V 5 . 2
1
= , v
out
V 0
2
= . When
v
out
V 5
1
= , v
out
V 5
2
+ = . The range of the output
2 out
V : v v 5 5 + . The relationship with
2 out
V and the reference
voltage:
ref
V code digital
out
V = 128 / 128
2
.

FIG. 6 SIGNAL CONNECTION DIAGRAM
The general power supply voltage of the D/A has special requirements, and the choice of the power supply voltage
should meet the certain width of the WR strobe, usually at least ns 500 . However, when v
cc
V 5 + = , it should also
meet the requirements. For example, when v
cc
V 15 + = , the pulse width of the WR needs only at least ns 100 , at this
point, this is the best working state to the device. It ensures that the data entered a valid time status shouldnt be less
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than ns 90 , otherwise, it will latch fault data. The power voltage of the operational amplifier is generally selected v 15 .
The waveform generation circuit diagram is shown in figure 6.
5 THE SINE WAVE GENERATOR DESIGNING SOFTWARE FUNCTIONS
Systems using an external interrupt, and two timer interruption
[4]
. The outputs of the sine wave and triangle wave are
achieved by the look-up table method, and it changes the frequency by changing the output time interval of the
adjacent data points and the count of the output waveform cycle. Pulse output based on a single I/O is assigned "1"
and "0", and it achieves the change of the frequency by changing the high or low level dual time of the I/O output.
The keyboard is a independent interrupt keyboard. Software can through the discriminator of the button, and it calls
different buttons service subroutine so that realizing the output of the waveform.
Initialization
Start
Check number of key
Wait for key
Sine wave output
Key is pressed
Triangle wave
Output function
Sine wave output
function

FIG. 7 D/A CONVERTER TOTAL FLOW CHART FIG. 8 SINE WAVE SUBROUTINE FLOW CHART
As is shown in figure 7, it is the total flow chart for the D/A converter. Final, checking buttons, outputting triangle
wave or sine wave functions. When the 1 = flag , keys is valid. After the initialization, it output Hz 24 sine wave.
Press the sine wave button, the system will output about Hz 100 sine wave, the flow chart as shown in figure 8.
Firstly, turn off the timer
0
T , open the timer
1
T . Then display subroutine value. The finally, according to the process,
it will return when output frequency 5 = s .
6 THE CONCLUSION
This topic adopting SOPC technology, using of the MCU soft core processor embedded in the FPGA, and combined
with hardware circuit design completed the research and design of digital oscilloscope, and realized the main
functions of the digital oscilloscope. Including trigger synchronization, real-time/equivalent two ways, under the two
ways, it produces the single/continuous sampling mode and the equal precision frequency measurement/duty ratio.
Better to complete the function of the most of the digital storage oscilloscope. In the process of debugging,
sometimes, it can appear too high measured peak and frequency error values, and it may be the part problem of the
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operation amplifier. However, this design is only suit for single channel input. For the dual channel or multi-channel
input signal, we should add high-speed electronic switch and other devices in the input end. The input signal range of
the design is Hz 100 to KHz 20 , signs will change if it is greater than this value, and it needs to improve in the later
work.
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AUTHORS
1
Gang Luo is a Professor in the Chengdu
Institute of Technology. He received the
degree of BS in Mechanical Design and
Manufacture Engineering from Changchun
University of Science and Technology in
1991 and the Master degree in Electrical
Control Engineering from the UESTC in
2005. His present interests are embedded system design, electrical
control, and FPGA design.
2
J ie Peng, born in Hunan Province, China. Now he is a Master
research student in the department of Automation Engineering,
University of Electronic Science & Technology. His main
research interest is embedded system design, electrical control.
3
Lu Ma graduated University of Electronic Science &
Technology.



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4
Fei Yuan, born in Sichuan, China in1988. Now, he is a Master
research student in the department of Automation Engineering,
University of Electronic Science & Technology. His main
research interest is Fault-Tolerance Routing and Power on NOC.
5
Yuanyuan Mao, He is a Master research student in the departm-
ent of Automation Engineering, University of Electronic Science
& Technology. His main research interest is the embedded syste-
m design.