A new low power and all-MOS voltage-to-current

converter for current mode ADCs with high

linearity, high bandwidth and rail-to-rail input range
Cleber V. R. Almeida, M.Sc. Eng. Amauri Oliveira, D.Sc. Eng. Raimundo C. S. Freire, D.Sc. Eng.
DEE / Embedded Electronics Dept. Electrical Engineering Dept. (DEE) Electrical Engineering Department
UFBA / SENAI CIMATEC Federal University of Bahia (UFBA) Federal University of Campina Grande
Salvador, Bahia, Brazil Salvador, Bahia, Brazil Campina Grande, Paraı́ba, Brazil
cleber.vinicius@fieb.org.br amauri@ufba.br freire@dee.ufcg.edu.br

Abstract—This work presents a new low power and all-MOS
voltage-to-current (V-I) converter with high linearity (∼
=0.15%),
high bandwidth (∼ =19 MHz) and rail-to-rail input range (from
VSS up to VDD ) to be used prioritarily as a internal building
block of current mode A/D converters. The text includes the
description of the constituent stages of the converter topology,
as well as the static and dynamic simulations results, validating
the proposed converter through the MOS-level implementation
using computing tool Pyxis Schematics from Mentor Graphics,
with XFAB 180 nm technology.
Index Terms—voltage-to-current converter, all-MOS, rail-to-
rail input range, high linearity, high bandwidth
I. I NTRODUCTION
Development of low power and low voltage integrated
circuits (IC) is one of market trends. Search for that led
researchers to design analog circuits in current mode, which
allows decrease the source voltage, increase speed and to
simplify analog internal processing structures. But, since most
of the input and output signals are voltage signals, to process in
current mode a voltage-to-current (V-I) converter is required.
It is a basic building block in many AMS (Analog and Mixed-
Signals) systems designs, such as current mode analog-to-
digital converters (ADCs), an application in which the overall
system performance depends largely on the performance of
the V-I subcircuit [1], mainly concerning characteristics such
as low power, high linearity, high bandwidth and rail-to-rail
input range, unlike [1], [2]. Thus, in this paper is proposed
a new all-MOS V-I converter, unlike [3], with features cited
above, unlike [4], beyond having a high input impedance and
very low current output deviation, to be used prioritarily as an
internal building block of current mode ADCs [5]. This text
is organized on four main sections. Beginning with a brief
introduction, after that an topology elements description, as
well as CMOS implementation, following with the simulations
and results and ending with a conclusion with future subjects.
II. T OPOLOGY AND E LEMENTS D ESCRIPTION
Let: VDD be the highest positive supply voltage of the
circuit; VSS at the lower feed voltage (VSS < VDD ), which
C. V. R. A. thanks SENAI CIMATEC for its support.
may be negative or zero; Vin an analog voltage input signal,
where VSS  Vin  VDD ; IRange a current reference range;
and Iin(min) = Imin a minimum permissible constant current
value for Iin . Is desired that an input electric current corre-
sponding to the conversion of Vin , defined as Iin , normalized
to IRange = ΔI, is:
Iin = f (Vin ) = a × Vin + b (1)
Being angular ‘a’ and linear ‘b’ coeficients:
    
IRange VSS IRange
a= and b = Imin −
VDD − VSS VDD − VSS
Iin starts from a non-zero Imin value, because that con-
tributes to increasing the speed (frequency response) of a
current mirror when applied to its input, decreasing the input
impedance, since the input resistance (Rin ) of this mirror
corresponds to the inverse of the transconductance (gm ), which
is proportional to the root of the MOS device drain current
(ID ). If gm increases, Rin decreases which increases the speed
of the current mirror. Thus, the graph of the function (1) is
shown in Fig. 1.
Fig. 1. Voltage-to-current (V-I) conversion function graph.
Note: Iin in (1) corresponds to Vin converted in a current
signal. It will be the output of the proposed conversion circuit.
Because that, Iin will be called Iout .
Is proposed in this paper to implement (1) with a circuit
topology that behaves like the Fig. 1, constituted by four basic

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elements: a voltage divider or attenuator; a level-shifter circuit;
a PMOS differential pair; and a voltage reference source. All
connected as presented in block diagram on Fig. 2.
Fig. 2. General topology proposed for V-I converter.
All the following structures have been implemented on
Pyxis Schematics tool from Mentor Graphics, to integrated
circuits design, using XFAB 0.18 μm (1.8V) Process Design
Kit (PDK).
A. Differential Pair (DIF AMP PMOS)
The MOS Differential Pair (DIF AMP PMOS) is the stage
that forms the core of the conversion process. Topology of the
circuit is based on a PMOS differential pair according to Fig.
3.
Fig. 3. Proposed topology of the PMOS differential pair as V-I converter.
Drain terminal currents of M p1 and M p2 (ID1 and ID2
respectively) may be attenuated or amplified by mirroring
the VGS voltages of M n1 and M n2 . ID2 is used to gen-
erate the output current at the drain terminal Iout =kID2 ,
where “k = (WM n2 /LM n2 )/(WM n3 /LM n3 )”. In the ter-
minal equivalent to the inverting input, a constant reference
voltage Vref =(VDD +VSS )/2 is inserted. While in the terminal
equivalent to the non-inverting input is inserted the input
voltage signal Vin , which is to be converted into a current
signal. If Vin linearly varying from VSS to VDD , the curves
of the currents ID1 and ID2 are the same as those of the graph
“(a)” in Fig. 4. It is noted that in Fig. 4.(a) a small excursion
band around Vref =(VDD +VSS )/2=0.9V where the variations
of the excursion of ID1 and ID2 are practically linear.
In order to take advantage of this small linear excursion
range of Fig. 4.(a), Vin must have a peak-to-peak ampli-
tude equivalent to the width of the small linear voltage
range of the differential pair and with an offset voltage
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Fig. 4. Operating characteristics curve of the PMOS differential pair topology,
used as V-I converter core.
Vof f set =Vref =(VDD + VSS )/2 according to Fig. 4.(b), result-
ing in ID2 according to Fig. 4.(c). Current ID2 corresponds
to Vin converted on current “Iout ” which can be mirrored,
copied, amplified or attenuated at the output, as shown in Fig.
3, through the drain terminal of M n3 .
A differential pair was adopted using PMOS to reduce noise
and raise the speed by raising the transconductance (gm ) of
NMOS load devices (M n1 and M n2 in Fig. 3) to “common-
source” by reducing the input resistance of the output current
mirror Rin ∼ = 1/gm . Thus, the complete “PMOS Differential
Pair” circuit (“DIF AMP PMOS”) is shown in Fig. 5. The
current source ISS1 of the topology shown in Fig. 3 is
implemented by PMOS M P 3 and sized to be biased by 0.45V
bias voltage (1/4 of VDD =1.8V ).
Fig. 5. DIF AMP PMOS circuit.
In Fig. 5, the output terminals “Iout” and “Iout C” are
the current outputs in the drain and source modes respec-
tively. The terminals “Vb Iout” and “Vb Iout C” are bias
outputs to mirror “Iout” and “Iout C” respectively, if desired.
“Vb p” is the input of the bias voltage, scaled to 0.45V .
“V IN P” and “V IN N” are the non-inverting and inverting
inputs respectively. The input voltage to be converted will
be in the differential mode (Vin(d) =Vin -Vref ), being applied
from the terminal “V IN P” to the terminal “V IN N”.
Vin(d) will be limited to the linear range of the differential
pair set for VDD /36=1.8/36V =50mV . “DIF AMP PMOS”
is designed to generate Imin =Iof f set =100.0μA and an
ΔI=50μA. Thus, the maximum current value will be
Imax =ΔI+Iof f set =50μA+100μA=150μA. The circuit is pre-
sented in Fig. 5 and a symbol has been assigned to it.
1) Output Stage: The differential pair output stage was
performed with a PMOS version of the Wide Output Swing -
Regulated Cascode Current Mirror (WOS-RCCM) [6], giving
greater load resistance of the output current source and a better
dynamic response. This version was obtained by mirroring the
WOS-RCCM’s PMOS and NMOS devices [6]. It was divided
into two subcircuits: one Regulated Cascode Amplifier type
“P” (RCA-P), used as a transistor, and one VBIAS-P, for RCA-
P bias. All of the RCA-P and VBIAS-P designs were carried Fig. 11. Adopted Level-Shifter topology.
out by reversing the WOS-RCCM design and considering
the NMOS and PMOS charge carriers motility ratio (μp /μn ).
Circuit and RCA-P symbol are shown respectively in Fig. 6
In the circuit of Fig. 11, the current source “ISS2 ” was
and Fig. 7. The circuit and symbol of the VBIAS-P are shown
constituted by a composite PMOS transistor and sized to be
respectively in Fig. 8 and Fig. 9.
biased with “V b p = 0.45V ”. Thus, the complete circuit is
shown in Fig. 12 and the symbol in Fig. 13.

Fig. 6. RCA-P circuit Fig. 7. RCA-P symbol.

Fig. 12. Level-Shiffter circuit. Fig. 13. Level-Shiffter symbol.

C. Voltage Divider (VD)

At the Level-Shifter input, the excursion of the input voltage
signal must be in the small approximately linear range of
the differential pair. Voltage Divider (VD) circuit attenuates
Vin , which varies between VSS and VDD , to the linear range
(Figure 14).

Fig. 8. VBIAS-P circuit. Fig. 9. VBIAS-P symbol.

B. Level-Shifter (LS)
For Vin to travel only around the linear range of the
differential pair, it is necessary to add an offset voltage:
“Vof f set = (VDD + VSS )/2”. Therefore, Vin must be DC
level-shifted, as shown in Fig. 10.
Fig. 10. Level-shifting of an input signal, adding a Vof f set = (VDD +
VSS )/2.
In order to obtain this result, a “Source Follower” circuit
or “Common-Drain Amplifier” (Fig. 11) was used as Level-
Shifter.
Fig. 14. Graphic demonstration of the input signal attenuation.
After several topologies tested, the one that presented the
best linearity was the based on “N ” MOS impedances equal
in series, as shown in Fig. 15. In this way, the total input
impedance “Zin (s)” of the proposed final voltage divider will
result in “Zin (s)=N × ZS (s)”, while maintaining the same
cutoff frequency “ω−3dB ” [rad/s] or f−3dB [Hz].
Being in Fig. 15: “r” is the equivalent resistance of a
connected diode PMOS device, given by “r=VDS /ID ; VDS ”
is the voltage drop between the Drain (D) and Source (S)
terminals of a PMOS device; ID is the current passing through
the Drain terminal (D) of a diode connected PMOS device,
operating in the subthreshold region (VGS < VT ), given by (2);
η is the slope factor in the subthreshold region (1 < η < 3);
ID0 is the leakage current from the drain terminal to the source

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Fig. 15. Proposed topology for the Voltage Divider (VD) circuit: resistors
model and MOS implementation.
terminal, when VGS =0; W/L is the aspect ratio of the PMOS
device, consisting of the ratio between the PMOS channel
width “W ” and the length of the “L” channel of the PMOS;
VGS is the voltage drop between the Gate (G) and Source (S)
terminals of a PMOS device; VT is the Threshold voltage of
a PMOS device; rk (k=1, 2, 3, · · · , N ) is the “k”th resistance
“r” of a connected PMOS device as a diode.
  V 
W GS
∼
ID = ID0 e ηVT (2)
L Vin(aten) =Vin(max) /36=1.8V /36=50mV corresponding to the
The voltage divider proposed in Fig. 15 is a passive circuit
that has a voltage at its output (Vout ) as a function of the input
voltage (Vin ) given by Vout = Vin /N . With the MOS voltage
divider (Fig. 15) installed at the input of V-I Converter, the
total input resistance is viewed as the sum of all “N ” resistors
rk , being k = 1, 2, 3, · · · , N . Thus, the total input resistance
will be Rin(total) = N × r.
Topology proposed and presented in Fig. 15 considers
the effects of the parasitic capacitances and the capacitances
resulting from the coupling of the Level-Shifter stage, shown
in Fig. 16.(a), since at high frequencies the input port PMOS
capacitance of the Level circuit -Shifter changes the value
of the last equivalent resistor of the splitter by reducing it
and decreasing the maximum value of the output voltage
of the voltage divider. This coupling (Fig. 16.(a)) can be
modeled as an equivalent resistor in parallel with an equivalent
capacitance, as shown in Fig. 16.(b).
Fig. 16. Determination of the equivalent model of the coupling between
voltage divider and level-shifter.
In Fig. 16, the “gate-source” capacitance of the input PMOS
is represented as “Cin [M p3 ]”. The equivalent resistance of
the PMOS “M pr“N  ” is represented by “r“N  ”. Thus, the
solution was to treat the voltage divider in Fig. 15, not as series
resistors, but rather as serial impedances “ZS (s)”, each series
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impedance being equivalent to a “r” in parallel with a ca-
pacitance “Cin ” (ZC (s)=1/(sCin )), where ZS (s)=r||ZC (s).
Thus, after an asymptotic analysis of ZS (s), a typical behavior
of a ”low pass filter” is observed, with the cutoff frequency
“ω−3dB =1/(r·Cin )” [rad/s] or “f−3dB =1/(2πr·Cin )” [Hz].
The fully MOS version is shown in Fig. 16.(c). In the
diode configuration, seen in Fig. 16.(c) in the device “M pr”,
which exerts the resistance function “r” (Fig. 16.(b)) of it is
“short-circuited”, leaving the “gate-source” and “source-drain”
capacitances in parallel. These will still be added to the drain
capacitance of the “M pc” device (Fig. 16.(c)), which performs
the function of capacitance “C” (Fig. 16.(b)). The circuit of
Fig. 16.(b)) is the basic impedance unit of the voltage divider.
For the final circuit of the voltage divider, 35 units of
Fig. 15 were used in series and another individual PMOS
device, totaling 36 units. The dimensions of all PMOS devices
acting as resistors remained the minimum for the XF AB
0.18μm technology (W = 0, 22μm e L = 0, 18μm). In the
PMOS devices acting as capacitances, L remained the same
as L = 0, 19μm of the Level-Shifter M P 1 device (Fig. 12)
and W = WM P 1 /4 (W = 1, 57μm/4 ∴ W ∼ = 0, 4μm).
Thus, the proposed voltage divider will be able to attenuate
exact linear excursion range of the par-differential. Voltage
of 50mV will be VDS of each PMOS. As VGS < VT , the
transistors will operate in the subthreshold region, according
(2). Thus, the proposed final Voltage Divider (VD) circuit is
shown in Fig. 17 and the symbol in Fig. 18.
Fig. 17. MOS VD (voltage divider) circuit. Fig. 18. Symbol.
With these dimensions, assuming that: N =36 PMOS de-
vices will be used; that the maximum voltage drop in each
PMOS device is VDS =50mV (VGS < VT , “subthreshold
region”); and once in possession of the technology parameters
for the PMOS; from (2), ID = 503.5f A, r = 99.3GΩ
and Zin(total) = Rin(total) = 3.57T Ω is expected. The
calculated approximate value of the Level-Shifter input ca-
pacitance (Cin =∼ = 1.81f F ). Given the high resistance of
the RC network formed by Cin and Rin , one would expect
f−3dB ∼ = 1kHz without impedance balancing. With the
balance, the equivalent capacitance of the circuit (Ceq ) was
minimized, raising significantly f−3dB ∼ = 20.0M Hz, making
W = WM P 1 /4 = 1.57μm/4 ∴ W ∼ = 0.4μm of the PMOS
devices as capacitors of Fig. 16 “(c)”.
D. Voltage References Source (VREF SRC)
Reference voltage generator circuit (“VREF SRC”) is
shown in Fig. 19 and the symbol in Fig. 20. It consists
of a simple voltage divider of the VDD supply, with four
equal PMOS with W = 0.22μm and L = 0.18μm, mini-
mum allowed by the adopted technology, thus reducing the
consumption of the circuit. V REF OU T 1 = VDD /2 and
V REF OU T 2 = VDD /4. All transistors operate in the
subthreshold region. M N 1 and M N 2, both with W = L =
10μm, are NMOS as capacitors.
Fig. 19. “VREF SRC” circuit. Fig. 20. “VREF SRC” symbol.
E. Complete Circuit
Connecting all proposed topologies, the final topology used
for converting the input voltage signal (Vin ) into the output
current (Iout ) is shown in Fig. 21 , with Imin =Iof f set ,
according (1) and whose behavior corresponds to that shown
in Fig. 1.
Fig. 21. Final topology of the proposed V-I converter.
Including WOS-RCCM output stage with RCA-P (Fig. 7)
in the circuit of Fig. 21 and using only symbols of all stages
described previously, the complete circuit of the proposed V-I
converter is shown in Fig. 22.
Fig. 22. Complete V-I converter circuit.
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III. S IMULATIONS AND R ESULTS
All simulations were carried out using Mentor Graphics’
Pyxis software with MOS devices from XFAB 0.18 μm (1.8V)
technology.
A. Test Setup
For evaluation tests, the circuit of Fig. 22 was fed with
VDD =1.8VDC , VSS =0.0VDC (GND). A continuous DC volt-
age source VL was added as load on output Iout , to evaluate
the variation of Iout with VL . Finally, a DC and AC voltage
source was coupled on “V IN ” input to generate signals
between VSS =0.0VDC (GND) and VDD =1.8VDC (compatible
with XFAB 0.18μm technology). Static simulations (DC anal-
ysis and operation point analysis) and dynamics simulations
(transient and AC analysis) were carried out, aiming to:
evaluate the power consumption; evaluate the accuracy of the
converter in generating a current signal with linear variation;
evaluate the frequency response of the drive.
B. Static Simulations
In Fig. 23 is presented the result of a DC analysis simulation
varying linearly Vin from 0.0 VDC to 1.8 VDC . Iout varies lin-
early from Imin =Ioffset=108.3μA with IRange = ΔI=49.5μA
to Imax =Imin +ΔI=157.8μA. That limits corresponded to the
designed values.
Fig. 23. Graph Vin × Iout .
Percentage error (“P ercent Error”) of “Iout” in relation
to its theoretical value is shown in Fig. 24. The maximum
deviation was 0.16%.
Fig. 24. Percentage error variation graph of Iout .
The variation in the angular coefficient of the linear curve
in Fig. 23 is shown in Fig. 25.
Due to the use of the WOS-RCCM as output stage, sweep-
ing load voltage from 0% to 66.67% of VDD (from 0.0VDC

Fig. 25. Graph of derivative of Iout .
to 1.2VDC ), there was a variation of 0.02% of Iout , according
to Fig. 26.
Fig. 26. Variation of Iout with variation of VL from 0% up to 66.67% of
VDD .
The operating point (OP) analysis has resulted in ID =513.11
fA and Rin =3,5 TΩ for Vin =VDD =1.8V, as expected. The total
power dissipated was 1.17 mW at 27o C.
C. Dynamic Simulations
The result of the frequency response analysis (AC analysis)
is shown in Fig. 27, with f−3dB =19 MHz, satisfactorily close
to that expected.
Fig. 27. Frequence response from 0.0 Hz up to 1.0 GHz.
D. Performance and Characteristics Summary
Thus, on Tab. I is presented a summary about the per-
formance and characteristics of the proposed V-I converter,
obtained by the schematics design and the results combination
of the operating point analysis, DC analysis, transient analysis
and AC analysis.
IV. C ONCLUSION AND F UTURE S UBJECTS
This paper presented a new voltage-to-current (V-I) con-
verter with high linearity of the output current around 0.15%,
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TABLE I
P ERFORMANCE AND C HARACTERISTICS
Power supply (VDD ): 1.8V
Total number of transistors: 105
Total estimated effective area: 643 μm2
Total number of passive devices: 0 (all MOS)
Linearity error: 0.15%
Output current range: 108∼158μA
Output current deviation: 0.02% (for 0V VL 1.2V)
Overall power consumption: 1.17 mW
Maximum input impedance: 3.6 TΩ
Input signal linear range: 0∼100% VDD (rail-to-rail)
Bandwidth: ∼
=19 MHz
high input impedance around 3.6 TΩ, very low output current
deviation around 0.02%, low power consumption around 1
mW, high bandwidth about 19 MHz, rail-to-rail input range
(from VDD up to VSS ) and all-MOS (no internal or external
resistors and capacitors is used), to be used prioritarily as an
internal building block of current mode A/D converters. Topo-
logical concepts adopted on this paper were implemented and
validated using XFAB 0.18 μm CMOS technology. Despite of
using a large numbers of transistors and a complex structure,
the proposed V-I converter has a simple working principle,
a low power consumption, an acceptable area occupation and
promising results. In the future, V-I converter chip proposed on
this work will be fabricated using PDK of the same technology.
ACKNOWLEDGMENT
C. V. R. A. thanks SENAI/DR-BA (National Service of
Industrial Learning / National Directory from Bahia, Brazil)
and its unit CIMATEC (Integrated Campus of Manufacturing
and Technology), from Salvador-BA, Brazil, for all its support,
making available licenses of Mentor Graphics IC design tools
and workstations in order to carry out this work.
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