International Conference on Communication and Signal Processing, April 6-8, 2016, India
Implementation of High Speed and Low Power
5T-TSPC D Flip-flop and Its Application
Ashwini. H, Rohith. S, Sunitha. K. A

Abstract—True Single Phase Clock (TSPC) is a general
dynamic flip-flop that operates at high speed and consumes low
power. This paper describes the design and performance analysis
of 5 transistor (5T) TSPC D Flip-flop in comparision with
different TSPC D Flip-flops such as; (i) MS-Negative-edge
triggered TSPC D Flip-flop, (ii) Positive-edge triggered TSPC D
Flip-flop with (a) 13 transistors, (b) 11 transistors, (c) 9
transistors, (d) 8 transistors, (e) 6 transistor TSPC D Flip-flops
with respect to transistor density, power and delay. Finally
Charge Pump with PFD is designed using 5T TSPC D Flip-flop
method and functionality of the circuit is verified through
simulation. A Layout of 5T TSPC D Flip-flop and Charge Pump
with PFD are designed. DRC, ERC, LVS are verified with gpdk
180nm technology. All the circuits used in this paper are designed
and simulated using Cadence Virtuoso Platform, with gpdk
180nm CMOS process using 1.8V supply voltage.
Index Terms—TSPC D Flip-flop; Phase Frequency Detector
(PFD); Charge Pump; Power; Delay Element;
I. INTRODUCTION
Achieving high performance in any Very Large Scale
Integration (VLSI) systems is the most important part and the
demand had increased with the growth of the semiconductor
technology. As technology advances, a Systems-On-a-Chip
(SOC) design contains more number of components that lead
to a higher transistor density and increased power consumption
[1-5]. As well as it needs a faster clock for its operation, that
consumes more power. To improve the frequency of operation
and integration of components of the Very Large Scale
Integration (VLSI) Integrated Circuits (ICs) has been
increased with the advance of Complementary Metal Oxide
Semiconductor (CMOS) technology. The distribution of the
global clock input and the inverse of it results in the clock
skew problems in relation to each other, and also this
consumes more power. Thus to overcome this problem Single
Phase Clocking is very advantageous [6-10]. The True Single
Phase Clock (TSPC) is a broad dynamic flip-flop that operates
Ashwini.H, Department of Electronics & Communication, Nagarjuna
College of Engineering and Technology, Bangalore, Karnataka, India-562110
(ashwinih32693@gmail.com)
Rohith.S, Department of Electronics & Communication, Nagarjuna
College of Engineering and Technology, Bangalore, Karnataka, India-562110
(rohithvjp2006@gmail.com).
Sunitha.K.A, Department of Electronics & Communication, Nagarjuna
College of Engineering and Technology, Bangalore, Karnataka, India-562110
(sunithaka1990@gmail.com)
978-1-5090-0396-9/16/$31.00 ©2016 IEEE
0275
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 17:51:42 UTC from IEEE Xplore. Restrictions apply.
at high speed and with low power consumption. It uses one
phase clock for synchronization. Many researches has shown
TSPC method has small area, no clock skew problem and even
higher clock frequencies can be achieved thereby improving
the performance of the digital systems. It is used in various
applications like digital VLSI clocking system,
microprocessors, buffers, wireless communication systems etc
[7].
In many applications such as wireless communication
systems, digital circuits, and receivers, Phase Lock Loop
(PLL) is one of the most important blocks. The intention of
PLL is to generate a signal, such that the phase is equal to the
phase of the reference signal. Some of the applications of PLL
are frequency synthesis, clock generation, carrier (clock)
recovery, and skew reduction, jitter and noise reduction. Phase
Frequency Detector (PFD) / Charge-Pump and Voltage
Control Oscillator (VCO) are the important components
present in PLL. PFD is a circuit that can detect both phase and
frequency errors, based on this it will generate output signals
“UP” and “DOWN”. A PFD is usually built using a state
machine with memory element such as D Flip-flop. In order to
make the PFD circuit simpler and reduce the dead zone there
are several methods. TSPC D-Flip-Flop is used more as a D-
Flip-flop in designing PFD, which provides low area and high
speed of operation [5].The main principle of Charge Pump is
to change the logic states of the phase frequency detector into
analog signals that is appropriate to control the VCO.
In [1], the design of a 3-V 300MHz Low-Power 8-b×8-b
Pulse triggered TSPC Flip-flops, with the concept of True
Single Phase Clocking, a new pulse triggered TSPC Flip-flop
(PTTFF) that comprised of five transistors is implemented.
Using this PTTFF and with the 14-transistor pseudo- NMOS
full adder an 8-b×8-b pipelined multiplier is designed using
0.6μm CMOS process. In this, power analysis is performed for
low power pipelined multiplier. Using TSPC D Flip-flop
method the multiplier is designed and analysis is performed on
power consumption with different supply voltage. The design
and implementation of A 5.8 GHz Wideband TSPC Divide-
by-16/17 Dual Modulus Prescaler discusses about improving
the speed by incorporating a new pseudo divide-by-2/3
Prescaler and reducing delay to increase speed of operation.
By using the concept of TSPC D Flip-flops the power and
delay analysis is carried out using 0.18μm CMOS technology
with 1.6 supply voltage and frequency range of 2MHz in [2].
The structures of different dividers for high frequency wireless
 systems are discussed in [3]. A CMOS divider family for high input=0 then m1 and m2 transistors are ON while m3 is OFF
frequency wireless localization systems. In this, using TSPC this turns ON m5 producing the output LOW. That is during
and CMOS logic the analysis on low power consumption and ON period of clock signal whatever the value of the input is,
high speed of operation for various dividers in comparision the output follows the input. On the other hand when clk=0,
with other dividers is performed using 130nm CMOS the output follows the previous value of the output.
technology with 10GHz to 22GHz maximum operating
frequency and also it is shown that TSPC logic based divider
is better in performance in comparision with CML logic. It is
discussed in [6], the design of A new N-Fold Flip-flop
exploiting the clock gating technique for both output enabling
and power saving, using TSPC logic an octal flip-flop was
built and compared to the main octal flip-flop with respect to
performance in terms of power, area and digital noise. Fig. 1. Circuit of 5T TSPC D Flip-flop [6]
Implementation and simulations is performed using
STMicroelectronics 65nm technology process with 1.1V
TABLE I
power supply.
In this paper the performance comparision among different TRUTH TABLE OF 5T TSPC D FLIP-FLOP
TSPC D Flip-flops with respect to transistor density, power
and delay is done for the following TSPC D Flip-flops; MS- Clk D M1 M2 M3 M4 M5 Q
Negative-edge triggered D Flip-flop, Positive-edge triggered
13 transistor, 11 transistor, 9 transistor, 8 transistor, 6 1 0 ON ON OFF OFF ON 0
transistor, and 5 transistor TSPC D Flip-flops. Out of these
TSPC D Flip-flops one flip-flop was found better in 1 1 OFF ON ON ON OFF 1
performance i.e. 5T TSPC D Flip-flop [11-13]. This 5T TSPC 0 0 ON OFF OFF OFF ON 0
D Flip-flop method is used for the implementation of Charge
Pump with PFD. And also 5T TSPC D Ff and Charge Pump 0 1 OFF OFF ON OFF ON 0
layout is designed and verified with the schematic view. All
the circuits used in this paper are designed and simulated and
the respective output of each circuit is taken using Cadence III. PROPOSED WORK
Virtuoso platform using gpdk 180nm CMOS process. The
Using (Master-Slave) MS-5T TSPC D Flip-flop method
performance comparision is made for all the circuits in terms
the Charge Pump with PFD is implemented. The Circuit of
of power dissipated and delay.
MS-5T TSPC D Flip-flop with reset input is shown in Fig. 2. It
Rest of the paper is discussed as follows, in Section II, the uses active high reset i.e. a high on reset pin will reset the flip-
design of 5T TSPC D Flip-flop is discussed. In Section III, flop to the initial value. The operation of MS-5T TSPC D Flip-
Application of TSPC Flip-flop in PFD and Charge Pump with flop is illustrated as shown in Truth Table II.
PFD is discussed. In Section IV, simulation results and
analysis are shown. Finally in Section V, the conclusion is
given.

II. DESIGN OF 5T TSPC D FLIP-FLOP

A. 5Transistor (5T) TSPC (True Single Phase Clocking) D

Flip-flop
Fig.1 and Table I shows Circuit and Truth table of positive
edge triggered 5 transistors TSPC D Flip-flop respectively. 5T
TSPC D Flip-flop is constructed using 3 NMOS and 2 PMOS
transistors. This flip-flop uses single clock phase signal for
synchronization. It consumes less area since it uses only 5
transistors, which signify low transistor count and it also
consumes less power. Thus the performance of this design is
improved. The working principle of this flip-flop is as
follows: When clock and input signal is HIGH i.e. clk=1, D
input=1 then the NMOS transistors m2 and m3 is ON while
PMOS transistor m1 is OFF this in turn turns ON PMOS
transistor m4 and turns OFF NMOS transistor m5 thus pulling
the output to HIGH i.e. Q=1. Similarly when clk=1 and D
Fig. 2. Circuit of MS-5T TSPC D Flip-flop with reset input
The Circuit of Charge Pump shown in Fig. 3, it consists of two
current sources idc and idc1 which are identical, UP and
DOWN are the output signals of PFD which is given as an
input to charge pump. Based on the three conditions of PFD
i.e. based on error signal generated by the PFD the charge
pump is controlled. That is whenever UP or DOWN signal of
PFD is raised to HIGH it provides (+/- Vp) charge pump
voltage or charge pump current (+/-Ip). When both UP and

0276
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 17:51:42 UTC from IEEE Xplore. Restrictions apply.
 DOWN output signals from PFD are off i.e. LOW output III shows comparision table interms of power, delay, and no of
remains constant. transistors used for different TSPC D Flip-flops

TABLE II

TRUTH TABLE OF MS-5T TSPC D FLIP-FLOP

Clk D m1 m2 m3 m4 m5 m7 m8 m9 m10 m11 Q

1 0 on off off on on on on off off on 0

0 0 on off on on off off off on off on 0
1 1 off on off off on off on on on off 1
0 1 off on on off off off off on on off 1

Fig. 6. Waveform of Positive-edge triggered 5T TSPC D Flip-flop

Fig. 3. Circuit of Charge Pump[11]

Fig. 7. Layout of Positive-edge triggered 5T TSPC D Flip-flop
The block diagram of Charge Pump with PFD is shown in Fig
4. Based on the two input clock signals i.e. ref and div the
output signals UP and DOWN of the PFD are generated which TABLE III
are then fed as an input to the Charge Pump. Based on the
error signal produced by PFD the Charge Pump is controlled. COMPARISION TABLE OF DIFFERENTTSPC D FLIP-FLOP
Supply
Power Dissipated
voltage=1.8v No of Current
Delay
Width=2μm Total Static Dynamic transistor (nA)
(ns)
Channel power power power s used
length=180nm (μw) (μw) (μw)
MS-Negative
edge triggered 7.321 0.1303 7.19074 51.07 11-basic 72.3675
D Flip-Flop
Positive-edge
triggered 13T 8434458.
6.472 15182.0 15175.5 40.10 13
TSPC D Flip-
Fig. 4. Block Diagram of Charge Pump with PFD flop
Positive-edge
triggered 11T 11986195.0
5.064 21575.2 21570.08 0.098 11
TSPC D Flip-
IV. SIMULATION RESULTS AND ANALYSIS flop
Positive-edge
The different TSPC D Flip-flops such as MS-Negative triggered 9T 17857944.0
3.165 32144.2 32141.1 19.91 9
edge triggered D Flip-flop, Positive edge triggered 13 TSPC D Flip-
flop
transistor, 11 transistor, 9 transistor, 8 transistor, 6 transistor, Positive-edge
triggered 8T 17730345.0
and 5 transistor TSPC D Flip-flops are designed, simulated TSPC D Flip-
39.21 31914.6 31875.41 22.36 8

and the respective output of each circuit is taken using flop

Positive-edge
Cadence Virtuoso 180nm CMOS technology with 1.8V triggered 6T
2.604 0.0117 2.5922 39.55 6
6.53600
supply voltage. DE-TSPC D
Flip-flop
Positive-edge
triggered 5T 1.116 0.0012 1.1148 39.54 5 0.66582
TSPC D FF

Fig. 5. Schematic of Positive-edge triggered 5T TSPC D Flip-flop

Fig.5, 6, and 7 show schematic, waveform and layout of

positive-edge triggered 5 transistors TSPC D Flip-flop. Table Fig. 8. Schematic of MS- 5T TSPC D Flip-flop with reset input

0277
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 17:51:42 UTC from IEEE Xplore. Restrictions apply.
 The schematic of positive-edge triggered MS-5T TSPC D In the third case as shown in Fig. 12, if the reference signal is
FF is shown in Fig. 8. in phase with the feedback signal the loop is in the locked state
The block diagram of PFD using AND-Gate and MS-5T producing small pulses at the output of PFD.
TSPC D Flip-flop is shown in Fig 9. The circuit consists of
two Positive-edge triggered MS-5T TSPC D Flip-flops with
their D inputs tied to logic 1 and AND-Gate in reset Path. The
Ref and Div inputs serve as clocks of the flip-flops. The UP
and DOWN are the outputs of PFD which is given as input to
the AND-Gate, when both inputs to AND-Gate is HIGH, its
output is raised to HIGH which pre-sets the PFD to the Initial
value.

Fig. 12. Waveform of PFD using AND-Gate and MS-5T TSPC D Flip-flop
(ref in-phase with div)

The schematic of Charge Pump with PFD is shown in Fig. 13.

Charge pump is the subsequent block to the PFD. The output
signals UP and DOWN produced by PFD are given as an input
to the Charge Pump i.e. the UP and DOWN signals are
combined by charge pump into the single output to drive the
LPF.
Fig. 9. Schematic of PFD using AND-Gate and MS-5T TSPC D Flip-flop

The simulated output of PFD using AND-Gate and MS-5T

TSPC D Flip-flop (ref leads div) is as shown in Fig 10. From
figure we can see that when ref signal f1 leads div signal f2
then the output UP signal is asserted on the rising edge of the
reference signal, while the small pulse is generated at the
DOWN output, whose delay is equal to the delay through reset
path and logic gates.

Fig. 13. Schematic of Charge Pump with PFD

The Simulated output of Charge Pump with PFD is shown in

Fig. 14. Analog Design Environment in cadence is used for
simulations.

Fig. 10. Waveform of PFD using AND-Gate and MS-5T TSPC D Flip-flop
(ref leads div)

In the second case, when the ref signal f1 lags the feedback
signal div f2 then the DOWN output signal is produced
indicating the phase difference between the two clock signals
as shown in Fig. 11.

Fig. 14. Waveform of Charge Pump with PFD

The Layout of Charge Pump with PFD is as shown in Fig.

15. The DRC, ERC, and LVS are verified for the designed
layout.
Fig. 11. Waveform of PFD using AND-Gate and MS-5T TSPC D Flip-flop
(ref lags div)

0278
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 17:51:42 UTC from IEEE Xplore. Restrictions apply.
 circuits are designed and simulated using cadence virtuoso
180nm CMOS process with 1.8V supply Voltage. The total
power consumed by proposed method is 99.5μw and it less
compared to the conventional method with total power
consumption of 99.52μw.

VI. REFERENCES
[1] Jinn-Shyan Wang, Po-Hui Yang, and Duo Sheng, “ Design of a 3-V 300
MHz Low Power 8-b×8-b Pipelined Multiplier using Pulse Triggered
TSPC Flip-flops”, IEEE Journal of Solid Circuits, Vol.35, No.4, April
2000.
[2] Wenrui Zhu, Haigang Yang, Tongqiang Gao, Fei Lui, Dandan Zhang,
Fig. 15. Layout of Charge Pump with PFD and Hongfeng Zhang, “A 5.8 GHz Wideband TSPC Divide-by-16/17
Dual Modulus Prescaler”, IEEE transactions on very large scale
Table IV shows dynamic, static, total power dissipation of integration (VLSI) systems, January 2015.
Charge pump with PFD. From table it is clear that it consumes [3] Melanie Jung, Georg Fischer, Robert Weigel and Thomas Ussmueller,
less power compared to conventional Charge Pump with PFD. “A CMOS divider family for high frequency wireless localization
systems”, Institute for Electronics Engineering, Friedrich Alexander
University of Erlangen-Nuremberg, Cauerstrasse, Erlangen, Germany
© IEEE 2012.
TABLE IV
[4] Manthena Vamshi Krishna, Manh Anh Do, Kiat Seng Yeo, Chirn
Chye Boon, Wei Meng Lim, “Design and Analysis of Ultra Low Power
DYNAMIC, STATIC, TOTAL POWER AND CURRENT OF CHARGE PUMP WITH True Single Phase Clock CMOS 2/3 Prescaler”, IEEE transactions on
PFD circuits and systems – Regular papers, VOl. 57, No.1, January 2 2010.
[5] Behzad Razavi, “RF MicroElectronics”, University of California, Los
Supply Angeles, Published by Dorling Kindersley (India) Pvt. Ltd., licensees of
voltage=1.8v Power Dissipated Current Pearson Education in south Asia, Copyright © 1998 by Prentice Hall
Width=2μm Total Static (μA) PTR Prentice-Hall, Inc.
Dynamic
Channel power power [6] Mounir Zid, Carlo Pistritto, Rached Tourki and Alberto Scandurra, “A
power (w)
length=180nm (μw) (μw) new N-fold flip-flop with output enable”, Electronics and Micro-
Electronics Laboratory, Faculty of Sciences of Monastir, Tunisia,
Charge pump International Journal of Embedded Systems and Applications(IJESA)
99.5 10195.3 919.75
with PFD 566.25 Vol.3, No.2, June 2013.
[7] Priyanka Sharma and Rajesh Mehra, “True Single Phase Clocking
The Schematic of conventional TSPC D Flip-flop is shown Based Flip-flop Design using Different Foundries”, Department of
E.C.E, International Journal of Advances in Engineering and
in Fig 16. Using this conventional TSPC D Flip-flop in the Technology, May 2014.
implementation of Charge Pump with PFD the total power [8] Sunita Arvind Rathod, Siva Yellampalli, “Design of Op-amp,
consumed was 99.52μw which is more than the proposed Comparator and D flip-flop for Fifth Order Continuous Time Sigma-
method. delta Modulator”, Published by: Blue Eyes Intelligence Engineering and
Sciences Publication Pvt. Ltd, International Journal of Innovative
Technology and Exploring Engineering, Volume-4 Issue-2, July 2014.
[9] Priyanka Sharma and Rajesh Mehra, “True Single Phase Clocking Flip-
flop Design using Multi Threshold CMOS Technique”, Department of
E.C.E, International Journal of Computers Applications Volume 96-
No.11, June 2014.
[10] Melanie Jung, Joerg Fuhrmann, Alban Ferizi, Georg Fischer, Robert
Weigel, and Thomas Ussmueller, “Design of a 12 GHz Low-power
Extended True Single Phase Clock (E-TSPC) Prescaler in 0.13μm
CMOS Technology”, Institute for electronics Engineering, Friedrich-
Alexander University Erlangen-Nuernberg Cauerstrasse, Erlangen,
Germany, Proceedings of the Asia-Pacific Microwave conference 2011.
[11] Kashyap K. Patel1, Nilesh D. patel2, “Phase Frequency Detector and
Charge Pump for DPLL using 0.18μm CMOS Technology”, L.C
Fig. 16. Schematic of Positive-edge triggered Conventional TSPC D Flip-flop Institute of Technology, Bhandu, International Journal of Emerging
Technology and Advanced Engineering 2008.
[12] H. Shin, “A 1-V TSPC dual modulus prescaler with speed scalability
V. CONCLUSION using forward body biasing in 0.18 μm CMOS,” IEICE Trans.
Electron., vol. E95-C, no. 6, pp. 1121–1124, Jan. 2012.
This paper discusses about implementation of different
[13] V. K. Manthena, M. V. Do, C. C. Boon, and K. S. Yeo, “A low-power
TSPC D Flip-flops and its comparison in terms of transistors, single-phase clock multiband flexible divider,” IEEE Trans. Very Large
power and delay, from comparison result and analysis it was Scale Integr. (VLSI) Syst., vol. 20, no. 20, pp. 376–380, Feb. 2012.
seen that 5T TSPC D Flip-flop is better in performance with
less power consumption compared to other flip-flops. Thus 5T
TSPC Flip-flop method is used for implementation of the
Charge pump with PFD and the simulated results are verified.
And also layout for 5T TSPC D FF and Charge Pump with
PFD is designed and extraction results are obtained. All these

0279
Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY KHARAGPUR. Downloaded on June 20,2022 at 17:51:42 UTC from IEEE Xplore. Restrictions apply.