LAB 10: Design of Finite State

Machines

By: Daniel Stumpp

Performed: 3/6/2019
Written: 3/9/2019
I. Purpose
The purpose of this lab was to design and test a finite state machine using synchronous design
techniques. Using Quartus Max+Plus II, the design was then simulated to ensure proper function
and then optimized using an iterative design process. Once optimized using simulation, the
design was realized on a breadboard. A LogicPort Logic Analyzer was then used to create timing
diagrams showing the function of the circuit. These timing diagrams were then compared to the
ones produced by the Quartus Max+Plus II simulation. Any anomalies between the two
waveforms were identified and the reason for the discrepancy was determined. The differences
between the simulated circuit and the physical implementation were identified and discussed.

II. Procedure
1. A mealy style finite state machine state transition diagram was created such that the
desired duty cycles of the output, Y, as outlined in Table 3.1 would be achieved. The
resulting finite state transition diagram is shown in Figure 3.1.
2. The state transition table shown in Table 3.2 was then created.
3. The state transition table was then extended to show the inputs required for each of the
three D flip-flops to be used. This change can be seen in Table 3.3. This process revealed
that the state transition table was that of a synchronous 3-bit counter.
4. Once the inputs D0, D1, and D2 were determined for each state, a Karnaugh map was
used to determine the Boolean expression for each input. This process is shown in Figure
3.2.
5. After determining the external logic required for the counter part of the circuit, the output
of each state needed to be determined. This combinational logic was to be tied to the
inputs of an 8-to-1 multiplexer. The multiplexer’s selectors would then be driven by the
counter.
6. Before determining the external logic feeding the multiplexer, it was determined that
because the output was designed to drive an internal load, the order of the outputs
should be rearranged in such a way that the frequency of discrete pulses was highest. This
would produce a waveform perceived by the load to be smoother. After some trial and
error, the output sequences shown in Table 3.4 were determined to be optimal.
7. Once the output sequence was optimized for each value of the inputs (A and B), Karnaugh
maps were used to determine the Boolean expression for each output in terms of the
inputs A and B. This process is shown in Figure 3.3.
8. A Quartus Max+Plus II schematic was then created using the following specifications as
shown in Figure 3.4:
a. The 7474 Dual D flip-flop IC chip was chosen to create the counter and was wired
as follows:

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 i. All clocks were connected directly to one clock input. This is required of a
synchronous design. Otherwise each output will not change
simultaneously as required.
̅̅̅̅ was connected to D0. This causes the output Q0 to change during each
ii. 𝑄0
state change, a characteristic of the binary counting sequence. This can be
seen on the right 7474 chip in Figure 3.4.
iii. The input logic for D2 and D1 was created pursuant to the transition
equations determined in step 4.
iv. All preset and reset pins are connected directly to Vcc. This is because
there is no need to reset or set the output values of the counter. Because
these inputs are active low, we pull them up to Vcc to disable them.
b. The 74151 8-to-1 multiplexer IC chip was chosen to act as the selector to
determine which of the 8 outputs will be displayed during a given clock cycle. It
was connected in the simulator as follows:
i. The least significant bit of the synchronous counter (C0) was connected to
the least significant selector of the multiplexer (A). Likewise, C1 and C2
were connected to B and C respectively.
ii. The 8 data inputs of the multiplexer were connected pursuant to the
Boolean expressions determined in step 7.
iii. The output of the multiplexer is the output of interest, Y, for the circuit.
9. After the schematic was created, Quartus Max+Plus II was used to create the simulated
waveform outputs for each combination of values for A and B.
10. Once the output was determined to be correct, the process of optimizing the circuit
through an iterative design process began.
11. The initial design required 6 total packages, not including the 555-timer IC package. Three
of these chips, the two 7474 D flip-flops and the 7486 Quad XOR, were dedicated to the
counter. To reduce the number of packages used to realize the synchronous counter, the
74193 4-Bit synchronous up-down counter was used. By only utilizing the three least
significant bits, the output of a 3-bit synchronous counter can be created.
12. Once this optimization possibility was recognized, the changes were made to the Quartus
Max+Plus II schematic as shown in Figure 3.5.
13. After the changes were reflected in the diagram, the output waveforms of the circuit were
again simulated, and it was confirmed that they were correct by comparing it to the
expected results as done in step 9.
14. Even with the substantial reduction of two packages, the circuit shown in Figure 3.5 still
required 4 packages to be realized.
15. In order to further optimize the circuit, it was determined that both the AND gate and the
OR gate needed for the combinational logic tied to the 8-to-1 multiplexer could be
realized using one package of 2-to-1 multiplexers.
16. This change was reflected in the Quartus Max+Plus II schematic using a 74157 IC chip as
shown in Figure 3.6.
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 17. Again, this new design was tested using the waveform simulator to ensure that the circuit
was still outputting the desired result.
18. After this final optimization, all external logic has been eliminated, and thus the number
of packages required has been minimized.
19. Once the circuit was minimized, the physical realization of the circuit on the breadboard
was required.
20. The first step of breadboard realization was to create a circuit to produce a clock signal.
This was achieved using the 555-timer IC chip. The characteristic equations shown in
Figure 3.9 were used to create a clock period of 2.079 ms. Both resistors selected were 1
kΩ and the capacitance of the two capacitors were .01 µF and 1 µF. A large capacitor was
chosen in order to reduce voltage ripple and produce a cleaner clock signal.
21. To create the inputs A and B on the breadboard, a DIP switch package and two 1kΩ
resistors were utilized to create two inverted logic sources.
22. The rest of the circuit was implemented as it was in the Quartus Max+Plus II schematic.
The completed circuit can be seen in Figure 3.6.
23. Once constructed, a LogicPort Logic Analyzer was used to confirm the proper operation
of the circuit based the expected results and the waveforms that were generated by the
Quartus Max+Plus II simulations. The steps used to create the LogicPort waveforms are
as follows:
a. The dedicated clock and ground pins were connected to clock and ground on the
breadboard.
b. The inputs D0 and D1 on the logic analyzer were connected to A and B on the
breadboard.
c. The input D2 on the logic analyzer was connected to the output, Y, on the
breadboard.
d. Then the logic analyzer was set to trigger on the rising edge of the clock signal.
This ensured that every state change could be seen because the states changed
on the rising edge of the clock signal.
e. The sampling frequency was set to 50kHz. This value was relatively low because
of the relatively high period of the clock signal used.
f. The input value AB = 00 was set and the logic analyzer was started. The waveform
was then viewed on the computer. This step was then repeated for each
combination of inputs A and B and proper function was confirmed. These
waveforms can be viewed in Figures 3.13(a-d).

III. Results
Design and Simulation
When determining how to implement the finite state machine, modifying the output pattern was
one of the first things considered. Because the requirement was that the circuit produce an

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output with a specified duty cycle of 1/8, 3/8, 5/8, or 7/8, it does not matter what order the
output bits were arranged in. They were arranged therefore in a way that created the highest
frequency of discrete pulses as shown on the right of Table 3.1.
Table 3.1: Original output pattern (left) and optimized output pattern (right)

Using this output pattern, the state transition diagram created in step 1 of the procedure is as
shown below in Figure 3.1.

Figure 3.1.
Mealy style state transition diagram using a 3-bit counting sequence to represent each state.

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Once the state transition diagram in Figure 3.1 was complete, the transition table shown in Table
3.2 below was created.
Table 3.2: Mealy style state transition table
Y
PS NS
AB = 00 AB = 01 AB = 10 AB = 11
000 001 0 0 0 0
001 010 1 1 1 1
010 011 0 0 0 1
011 100 0 1 1 1
100 101 0 0 0 1
101 110 0 1 1 1
110 111 0 0 1 1
111 000 0 0 1 1

In Order to implement this finite state machine, a 3-bit synchronous counter had to be created.
To do this it was required that the equations for D0, D1, and D2 of the D flip-flops be found. The
transition table shown in Table 3.2 was modified to include the values of D and Q for each D flip-
flop as shown in Table 3.3. The present states and next states are represented in decimal form
and the outputs are omitted for clarity.
Table 3.3: Transition table expanded to include inputs and outputs of the D flip-flops
PS Q2 Q1 Q0 NS D2 D1 D0
0 0 0 0 1 0 0 1
1 0 0 1 2 0 1 0
2 0 1 0 3 0 1 1
3 0 1 1 4 1 0 0
4 1 0 0 5 1 0 1
5 1 0 1 6 1 1 0
6 1 1 0 7 1 1 1
7 1 1 1 0 0 0 0

The values in Table 3.3 were used to create Karnaugh maps for each input, D2, D1, and D0. These
K-maps and the equations derived from them are shown below in Figure 3.2.

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 D2 D1 D0
Q2 Q2 Q2
Q1Q0 0 1 Q1Q0 0 1 Q1Q0 0 1
00 0 1 00 0 0 00 1 1
01 0 1 01 1 1 01 0 0
11 1 0 11 0 0 11 0 0
10 0 1 10 1 1 10 1 1

̅̅̅̅ + 𝑄1(𝑄2 ⨁ 𝑄0)

𝐷2 = 𝑄2Q1 𝐷1 = 𝑄1 ⨁ 𝑄0 𝐷0 = ̅̅̅̅
Q0
Figure 3.2
K-maps and derived equations for the inputs of each D flip-flop in a synchronous 3-bit counter

The final set of equations required to begin simulating and realizing the circuit is for the
combinational logic determining the output of each state transition. Table 3.3, a modified version
of the right of Table 3.1 shows the relationship between the outputs Y0-Y7 and the value of the
input AB.
Table 3.4: Each output of a cycle based on the value of the input
AB Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
00 0 1 0 0 0 0 0 0
01 0 1 0 1 0 1 0 0
10 0 1 0 1 0 1 1 1
11 0 1 1 1 1 1 1 1

From observing Table 3.4, Y0 = 0, Y1 = 1, and Y6 = A. Furthermore, it is clear that Y2 = Y4, Y3 = Y5

and Y7 = Y6. Therefore, to find the Boolean expressions for each output value we need to use
two K-maps, one for Y2 and one for Y3. These K-maps and all the derived equations are shown in
Figure 3.3.

Figure 3.3
Boolean expressions for each output state along with required K-maps

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With the design analysis complete, the design was built in Quartus Max+Plus II using packages
that were available to use, specifically 7400 series IC chips. The resulting design is shown below
in Figure 3.4.

Figure 3.4
First iteration of the Quartus Max+Plus II design

This first iteration of the design was not optimized. If the design in Figure 3.4 were to be
implemented it would have required a total of six packages as outlined in the Table 3.5 bellow.

Table 3.5: Packages required for the implementation of the circuit in Figure 3.4
Package Number
7474 Dual D flip-flop 2
74151 8-to-1 Multiplexer 1
7408 Quad 2-In AND Gate 1
7486 Quad 2-In XOR Gate 1
7432 Quad 2-In POS OR Gate 1
TOTAL 6

Further optimization focused on reducing the number of packages required to implement the
synchronous 3-bit counter. The first design iteration shown in Figure 3.4 has three packages used
solely for the counter. To eliminate two of these packages, a 4-bit counter chip, the 74157 was
converted to a 3-bit counter by only using the three least significant bits. This change is reflected

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in the second iteration of the design as shown in Figure 3.5. The data inputs of the counter were
not needed and thus they were grounded as seen in the schematic.

Figure 3.5
The second design iteration in Quartus Max+Plus II

The second design iteration still required two packages to create the 8-to-1 multiplexer’s external
logic. The third design iteration shown below in Figure 3.6 uses one Quad 2-In multiplexer to
create all external logic for the 8-to-1 multiplexer.

Figure 3.6
The third and final design iteration in Quartus Max+Plus II

Table 3.6 below shows the packages required for the final iteration of the design. When
compared to Table 3.5 it shows a 50% reduction in the number of packages required to
implement the design. This will allow for a smaller, more compact design.

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 Table 3.5: Packages required for the implementation of the circuit in Figure 3.6
Package Number
74193 4-bit UP/DOWN Counter 1
74151 8-to-1 Multiplexer 1
74157 Quad 2/1 Data Selector 1
TOTAL 3

Throughout the iterative design process and upon completion, Quartus Max+Plus II was used to
simulate the circuit and produce waveforms of the outputs as shown below in Figures 3.7(a-d).

Figure 3.7a
Simulated output waveform with AB = 00

Figure 3.7b
Simulated output waveform with AB = 01

Figure 3.7c
Simulated output waveform for AB = 10

Figure 3.7d
Simulated output waveform for AB = 11

As expected, the waveforms show output duty cycles of 1/8, 3/8, 5/8, and 7/8 when AB is 00, 01,
10, and 11 respectively. These waveforms confirm that the chosen implementation of the circuit
works properly. One unexpected anomaly that can be observed in Figure 3.7d is a brief drop in
the output Y. This behavior is indicated with a red circle in Figure 3.8. This behavior can be
explained by the fact that although the counter designed is synchronous, meaning each flip-flop
is driven by the same clock, each input has a discrete and different amount of gate delay. This
can be seen in Figure 3.4 where each D flip-flop has a different number of gates creating the input
logic. There is no gate delay for D0, a one gate delay for D1, and four gate delay for D2. The

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instance depicted in Figure 3.8 occurs on the fourth rising edge of the clock, meaning the
counter’s output is transitioning from 011 to 100. The transition of the two least significant bits
from 1 to 0 occurs more quickly than the most significant bit’s transition from 0 to 1. This creates
the brief intermediate state of 000 which causes the output Y to fall to 0 temporarily. It should
be noted that this behavior is only observed when AB = 11 because for all other values of AB the
output Y is designed to fall to 0 when the state changes to 100.

Figure 3.8
Focused image of simulated waveform anomaly

Implementation
To create a clock signal for the physical implementation of the circuit, a 555-timer chip was used.
The duty cycle of the circuit will not change due to a change in the period of the circle because
the duty cycle for this design represents the percent of time that the output is high over 8 clock
periods. Because of this, the large period chosen in procedure step 20 will not affect the
operation of the circuit. The calculations to determine the clock period are shown below. The
characteristic equations used come from the 555-timer reference sheet shown in Figure 3.9.
The values Rta = Rtb = 1kΩ and Ct = 1 µF were chosen and the period was calculated as follows:
𝑇 = .693 ∗ (𝑅𝑡𝑎 + 2𝑅𝑡𝑎 ) ∗ 𝐶𝑡
𝑇 = .693 ∗ 3(1000) ∗ 1 × 10−6
∴ 𝑇 = 2.079 𝑚𝑠

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 Figure 3.9
555-timer reference sheet [1]

Once the physical circuit was implemented on the breadboard as shown in Figure 3.10
verification of proper function was required.

Figure 3.10
Physical breadboard implementation of finite state machine design

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Verification
A LogicPort Logic Analyzer was used to analyze the output of the circuit for each combination of
AB. When first analyzed, an unexpected result was observed when the A = 1. This anomaly can
be observed below in Figure 3.11 indicated by a red arrow.

Figure 3.11
Unexpected output observed using logic analyzer when AB = 10

This anomaly consistently occurred during every other cycle through the eight output bits. The
change of Y on the falling edge of the clock should never occur. This behavior caused the finite
state machine to operate incorrectly. The output of the counter revealed that the clock was
unexpectedly changing on the falling edge of the clock signal when the outputs reset from 1111
to 0000. This caused the observed anomaly every other cycle because the designed circuit was
driven by the three least significant bits of the counter, hence two output cycles are observed for
every cycle of the counter. This anomaly does not occur when AB = 00 or AB = 01 because the
output is already low as the counter transitions from 1111 to 0000.
To correct this issue the 4-bit counter was converted into a 3-bit counter. To do this the master
reset was connected to Q3. This resets the counter to 0000 every time the value of Q3 switches
from 0 to 1, preventing the counter from counting from 8 to 15 and eliminating the undesirable
behavior observed during the transition from 1111 to 0000. As can be observed in Figure 3.10,
pin 7 was connected to pin 14 as specified by the pin configuration of the counter shown in Figure
3.12. A 1kΩ resistor was connected between pin 14 and ground to allow the reset to be pulled
high when Q3 is high.

Figure 3.12
Pin configuration for 74193 4-bit UP/DOWN Counter [2]

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Once this modification was made, the logic analyzer was again used to verify proper function of
the circuit. The waveforms produced by the circuit are shown below in Figures 3.13(a-d). It can
be seen in Figures 3.13(c-d) that the unexpected behavior of the output when AB = 10 and AB =
11 was resolved and the circuit functioned correctly for all values of AB.

Figure 3.13a
Output waveform when AB = 00

Figure 3.13b
Output waveform when AB = 01

Figure 3.13c
Output waveform when AB = 10

Figure 3.13d
Output waveform when AB = 11
IV. Conclusions
The completion of this lab revealed some interesting behavior of finite state machines and
provided excellent practice designing, simulating, and realizing a finite state machine. After
resolving the anomaly observed when A = 1 the circuit operated as expected. The optimization
through an iterative design process produced what I believe to be the most optimal realization
of this circuit with the packages provided. That process of optimization revealed techniques that
can often be used to minimize the number of packages used. For example, the use of 2-to-1
multiplexers can greatly reduce the number of packages required because they are universal logic
gates. The iterative design process used also allowed for the optimal design to be reached by
focusing on optimizing a single part of the circuit during each step instead of trying to find the

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best solution in one shot. Doing that would have likely resulted in missed opportunities for
optimization.
Another important lesson learned during this lab was that the physical implementation of a
circuit will not always match the simulation exactly. Simulators like Quartus Max+Plus II are
excellent tools for designing and optimizing solutions, however, they cannot always perfectly
replicate the behavior of the actual components. This was seen by the unexpected behavior of
the 4-bit counter when the circuit was realized on the breadboard. Even the datasheet gave no
indication that that behavior would occur. This shows that while datasheets and simulations
should be relied on heavily for design, the final implementation of a circuit may produce
unexpected behavior, and critical thinking and problem solving is required to eliminate that
behavior.

V. References
[1] 555-timer Reverence Sheet, http://www.engrclasses.pitt.edu/electrical/faculty-
staff/akjones/0501/web-docs/2019/spring/main.html
[2] Up/down binary counter with separate up/down clocks 74F193 Datasheet, Phillips
Semiconductors, http://www.engrclasses.pitt.edu/electrical/faculty-staff/akjones/0501/web-
docs/2019/spring/main.html.

Additional Sources
A. K. Jones, Lab 10: Design of Finite State Machines, http://www.engrclasses.pitt.edu/
electrical/faculty-staff/akjones/0501/web-docs/2019/spring/main.html.
A. E. Peiffer, Lab Partner.

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