Q1.

(Covers Block 1)
(a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11. Assuming the same machine to
be used for execution of the following three consecutive instructions:
LOAD C ; Loads the content of Memory location C into the Accumulator Register.
ADD B ; Adds the content of memory location B in the Accumulator Register.
STORE A ; Stores the content of Accumulator register AC in memory location A.
The following are the details about the instructions, data and registers:
 Each word of memory is of 32 bits in length. Each instruction is also 32 bits long.
 Main Memory has 256 words.
 The three consecutive instructions as shown above starts from memory location (1F)h; A is at
location (FD)h and contains a value (1000)h, B is at location (FE)h and contains a value (FF3B)h
and C is at location (FF)h and contains a value (2A2F)h.
 The AC, IR and MBR registers are of size 32 bits, whereas PC and MAR registers are of size
8 bits. The initial content of PC register is (1F)h
Draw the diagrams showing addresses and content of memory locations and Registers.
Show how the content of memory locations and registers will change with the execution
of the three instructions. Show all the addresses and values in hexadecimal notations You
must also perform the necessary arithmetic using signed 2's complement notation and
show the results indicating overflow, if any. Also explain the process of execution of the
instructions.

The above machine instructions are stored in three consecutive memory locations 1F,20 and 21
and the PC contains a value (IF), which in turn is address of first of these instructions. (Please
refer to figure .

Then the execution of the instructions will be as follows:

Fetch First Instruction into CPU:

Step 1 : Find or calculate the address of the first instruction in memory: The next instruction
address is contained in PC register. It contains 1F, which is the address of first instruction to be
executed.
Step 2: Bring the binary instruction to IR register.
For this the content of PC is passed to Memory Address Registers so that the instruction
pointed to by PC is fetched. That is location 1F’s content is fetched.CPU issues "Memory read"
operation, thus, brings contents of location pointed by MAR (1F in this case) to the MBR
register.Content of MBR(LOAD C) is transferred to IR. In addition PC is incremented to point to
next instruction in sequence (20 in this case).
Execute the Instruction
Step 3: The IR has the instruction LOAD C, which is decoded as "Load the content of address C
onto accumulator register".
Step 4: The address of operand “C” is FD, is transferred to MAR register.
Step 5: The content of memory location FD specified by MAR(2A2F) is transferred to MBR.
Step 6: The content of MBR (2A2F) is transferred to Accumulator Register.Thus, the
accumulator register is loaded with the content of location C, which is 2A2F.Now the instruction
1 execution is complete, and the next instruction that is 2 in location 20 indicated by PC is
fetched and PC is incremented to 21. This instruction is ADD B,which instruct CPU to add the
contents of memory location B(FF3B) to the accumulator(2A2F). On execution of this
instruction the accumulator will contain the sum of its earlier value that is C and the value stored
in memory location B.On execution of the instruction at memory location 21, PC becomes 22;
the accumulator results are stored in location C, that is FF, and IR still contains the third
instruction.

b) Perform the following conversion of numbers: (2 Marks)

i) Decimal (3412454512)10 to binary and hexadecimal
ii) Hexadecimal (FEDCBA9)h into Octal.
iii) String “In file name % means blank.” into UTF 8
iv) Octal (7766432)O into Decimal
(c) Assuming that inverse is represented as ' , simplify the following Boolean functions:
F= ((A' + B)' + (A'+B')')'
(d) Simplify the following function using K-map: F(A, B, C, D) = Σ (0, 2, 6, 8, 10, 14)
Draw the circuit using NAND gates. (2 Marks)
(e) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1.
Explain how this circuit will perform subtraction, if the value of A is 1111 and B is 1100.
You must . list all the bit values including Cin and Cout and overflow condition.
(f) Explain the functioning of a 2× 1 Multiplexer. You must draw its truth table and explain its
logic diagram with the help of an example input. (2 Marks)

A 2-to-1 multiplexer consists of two inputs D0 and D1, one select input S and one output Y.
Depends on the select signal, the output is connected to either of the inputs. Since there are two
input signals only two ways are possible to connect the inputs to the outputs, so one select is
needed to do these operations.

If the select line is low, then the output will be switched to D0 input, whereas if select line is
high, then the output will be switched to D1 input. The figure below shows the block diagram of
a 2-to-1 multiplexer which connects two 1-bit inputs to a common destination.
 The truth table of the 2-to-1 multiplexer is shown below. Depending on the selector switching
the inputs are produced at outputs , i.e., D0 , D1 and are switched to the output for S=0 and S=1
respectively . Thus, the Boolean expression for the output becomes D0 when S=0 and output is
D1 when S=1.

From the truth table the Boolean expression of the output is given as

D0s’+D1s

From the above output expression, the logic circuit of 2-to-1 multiplexer can be implemented
using logic gates as shown in figure. It consists of two AND gates, one NOT gate and one OR
gate. When the select line, S=0, the output of the upper AND gate is zero, but the lower AND
gate is D0.
Thus, the output generated by the OR gate is equal to D0. Similarly, when S=1, the output of the
lower AND gate is zero, but the output of upper AND gate is D1. Therefore, the output of the
OR gate is D1. Thus, the above given Boolean expression is satisfied by this circuit.

(g) Assume that a data value 1111 was receviced as 1011. Explain how use of Hamming's
Error-Correcting code will send this data value from source and correct error at the
destination. (2 Marks)
(h) Explain functioning of S-R flip flop with the help of logic diagram, characteristic table
and excitation table. (2 Marks)
R-S Flip flop - The graphic symbol of S-R flip-flop is shown in Fig . It has three inputs, S (set), R (reset) and
C (for clock). The Q(t+l) is the next state of flip-flop after the occurrence of a clock pulse. Q(t) is the present
state, that is present Q value
1) If no clock signal i.e. C=O then output can not change irrespective of R & S
values
2) When clock signal changes from 0 to 1 and S=l, R=O . output Q=l & Q’ =O (Set)
3) If R=l S=O & clock signal C changes from 0 to 1 then output Q=O & Q’ =I (Reset).
4) During positive clock transition if both S & R become 1 then output is not defined, as it may become 0 or 1
depending upon internal timing delays occurring in circuit.
(i) Explain the functioning of Asynchronous and Synchronous counter. Explain how are
they different from each other. (2 Marks)
A countor is a register, which goes through a predetermined sequence of states when clock pulse is
applied. In principle, the value of countem is incremented by 1 module the capacity of register i.e.
when the value stored in a counter reaches its maximum value, the next increment4 value becomes
zero.
Counters can be classified into two categories, based on the way they operate: Asynchronous
and synchronous counters. In Asynchronous counter, the change in the state of one flipflop
triggers the other flip-flops. Synchronous counters are relatively faster because the state of all
flip-flops can be changed at the same time,

Asynchronous Counters : This is more often referred to as ripple counter, as the change, which
occurs in order to increment the counter ripples through it from one end to the other. Fig shows an
implementation of 4-bit ripple counter using J-K flipflops. This counter is incremental on the
occurrence of each clock pulse and counts from 0000 to 1 1 11 (i.e. 0 to 15). The input line to J & K of
all flipflops .is kept high i.e. logic1. Each time a clock pulse occurs the value of flipflop is complemented
.The clock pulse is given only to first flipflop and second flipflop onwards, the output of previous flipflop
is fed as clock signal. This implies that these flipflops will be complemented if the previous flipflop has a
value 1. Thus, the effect of complement will ripple through these flipflops.

The major disadvantage of ripple counter is the delay in changing the value. The delay is
proportional to the length of the counter. Therefore, to avoid thisdisadvantage of ripple counters,
synchronous counters are used in which all flip-flops 'change their states at same time. Fig 4.19 shows 3-
bit synchronous counter.
The operation can be summarized as

i) . The first flip-flop is complemented in every clock cycle

ii) The second flip-flop is complemented on occurrence of a clock cycle if the current state of first flip-
flop is 1.
' iii) The third flip-flop is fed by an AND gate which is connected with output of first and second flip-
flops. It will be complemented only when first & second flip- flops are in Set State.

(j) Differentiate between fixed point numbers and floating point numbers? Explain the
representation for Zero in IEEE 754 single precision standard. Represent (-32.25)10 and
(0.000125)10 in IEEE 754 single precision format
Q2. (Covers Block 2)
(a) Reference Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of a
64×8 RAM. Also answer the following:
(i) How many data input and data output lines does this RAM needs? Explain your answer.
(ii) How many address lines are needed for this RAM? Give reason in support of your answer. (2
Marks)
(b) A computer has 16 MB RAM and has a word size of 32 bits. It has cache memory having
16 blocks having a block size of 64 bits. Show how the main memory address (17F0AB)h
will be mapped to cache address, if
(i) Direct cache mapping is used
(ii) Associative cache mapping is used
(iii) Two way set associative cache mapping is used.
You must clearly identify tag, index, main memory block address and offset etc. in your answer.
(3 Marks)

(c) Explain the process of Interrupt handling and Return from interrupt with the help of a

diagram. You must answer this question in your own words. (2 Marks)
(d) Differentiate
between the working of DMA and I/O processor. Explain the DMA

configurations and I/O channel structures. (3 Marks)

(e) Assume that a disk has 2000 tracks with each track having 256 sectors and each sector is of
size 2M. A file having the name openUni.txt is of size 32 M. Assume that disk has 16 free -
continuous clusters of 4 sectors each at different locations on the disk. How can this file be
allotted space on the disk? Also show the content of FAT after the space allocation to this file.
You may make suitable assumptions. You may assume the cluster size as 4 sectors, if needed. (4
Marks)
(f)

Explain the following giving their uses and advantages/disadvantages.

(Word limit for answer of each part is 50 words ONLY) (6 Marks)

(i) SCSI and IDE in the context of Interfaces

(ii) Scanner and its resolution
(iii) Scan codes in the context of keyboard
(iv) Access time on disks
(v) Virtual Memory
(vi) RAID level 0, 3 and 5

In order that devices manufactured by independent

vendors can be used with different computer manufacturers, it is important that the controllers follow some
drive interfacing standard, Following are the commonly used
drive interface standards:
IDE (Integrated Disk Electronics) Pevlces
IDE devices art connected to the PC motherboard via a 34-wire ribban cftble,
The common drive used today for workstations h~c~apsac ities of 4QMB to
lOOOMB and ratation speed 72QORPM. The contraller is embedded on the disk
drive Itself, It is an interface between the disk controller and an adopter located
on the motherboard. It has good access time of 20ms and data transfer rates of
about 1 Mbps under ideal conditions, Drives are reasonably cheap, The latest
version of the IDE specification enables four IDE channels: each one Is capable
of supporting two JDE devices.

SCSI (Small Compwter Systems Interface)

The other popular way Ls to attach a disk drive to a PC via a SCSTr interface. The
common drive choice for servers or hlgh-end workstatinns with drive capacities
rangas from 100MB to 20GB and rotation speed 7200RPM, It is w common 110
interface between the adapter and disk drives or any other peripheral, I.@., CP;
ROMs drives, @pe drives, printers etc.
SCSI (pronounced "scuzzy") Is arl interesting arld important variation ~f the separate
device controller idea for each device. It uses a generic device eontroller (called
SCGI controller) on the computer system wnd allows sny devloe with an SC61
interface to be direcltly conpected to the $@91 bus of the SCSl oontroller. The SCSI
interhe of a devios contains all ~1rcuitryth at the device needs to operate with the
computer system.
As shown in Figure 3, a SCEc~o ntroller cmnects dlrectly to the eomguter bus on one
side asd contr~lasn other bus (called SCSI bus) on the other @id&S.L nce the SCSI
controllel: is connected to the computer's bug on ope side and to the- SCST bus on the
@her side, it Carl communicated with the praGessor and memory and can also control
the devjces cannected ta the SCSI bu4. The SCSI bus is a bus design@d fnr connecting
devices t0 a cornputer in a uniform way,
These drives have fast access tine and hlgh data rates but &re expensive. Orlg
advantage of these drives is that a single 8CSI controller can cornmusicate
simultaneously with up to seven 16-bit PCfiT devices or up ?a 15 Wlde or Ultra-Wid@
devices. Each device myst be assigned a unique SCSI id~ntlfi~atiobrel tween Q and 7
(or 15).

The versions of SCSI:

The SCSI-1 calls for a cable with 8 data wires plus one for parity.
The SCSI-2 enables the use of multiple cables to support 16- or even 32-bit data
transfers in parallel.
The SCSI-3 enables the use of ~nultiplec ables to support 32- or even 64-bit data
transfers in parallel.
o With fast SCS1, it is possible to transfer 40MB ofdata per second on a single
SCSI cable.
A Scanner is a device that allows you to capture drawings or photographs or text from
tangible sources (paper, slides etc.) into electronic form. Scanners work by detecting
differences in brightness of reflections from an image or object using light sensors.
These light sensors are arranged in an array across the whole width that is scannable.
This packing determines the resolution and details that can be scanned.

1.1 Resolution
Rptical Resolution
Qptical resolution or hardware resolution is the mechanical limit on resolution of the
Scanner. For scanning, the sensor has to advance after each line it scans. The
smallness of this advancement step gives the resolution of the Scanner. Typically,
Scanners may be avqilable with mechanical resolutions of 300,600, 1200 or 2400 dpi.
Some ~pecials canners even scan 2 10,000 dpi.
tnterp~latedR esolution
Each Scanner is accompanied by a s~ftwwe. This software can increase the apparent
resol~tiono f the scan by a tecbniqye called Interpolation. By this technique,
additional dots are interpolated (adqed) between existing dats. This gives a higher
resolution and smoother picture but without adding any additional information. The
added dots will howeyer lead to larger file sizes.

Scan Codes
A scan code is the code generated by a microprocessor in the keyboard when a key is
pressed and is unique to the key struck. When this code is received by the computer it
OPERATOR issues an interrupt and looks up the scan code table in the BIOS and finds out which
keys have been pressed and in what combination. Special memory locations called
status bytes tell the status of the locking and toggle keys, e.g., Caps lock etc. Each
keypress generates two different scan codes - one on key-push down called Make code, another on its
popping back called Break code.This two-key technique allows
the computer to tell when a key is held pressed down, e.g., the ALT key while
pressing another key, say, CTRL-ALT-DEL.

There are three standards for scan codes: Model (83-key keyboard PC, PC-XT),
Mode2 (84-key AT keyboard), Mode3 (101 -key keyboard onwards). In Model Make
and Break codes are both single bytes but different for the same key. In Mode2 and
Mode3, Make code is a single byte and Break code iv t\\ o 17). IC\ (byte FO(Hex) + the
make cod
Q3. (Covers Block 3)
(a) A computer has a single core processor having 16 General purpose registers and 4 additional
special purpose registers. The machine has 1MB RAM. The size of each register and memory
word is 32 bits each. An instruction of the machine is of fixed length and is equal to one memory
words. Each instruction of the machine can have two operands – one memory operand and
second register operand (register operand can be in General purpose registers only). Memory
operand either uses direct addressing or is an immediate operand; however, register operand can
use either register direct or register indirect addressing. (Please note that if register operand uses
indirect addressing, then stated register contains the address of the operand in the memory.) An
instruction of a machine consists of operation code bits, two addressing mode bit, one register
operand and one memory operand. The addressing mode bits specifies addressing mode as:

Addressing mode bit Register Operand Memory Operand

00 Indirect Direct
01 Direct Direct
10 Indirect Immediate Operand
11 Direct Immediate Operand

The special purpose registers are - Program Counter (PC), Memory Address Register (MAR),
Data Register (DR) and Flag registers (FR). The First register of the General purpose registers
can be used as Accumulator Register. The size of Integer operands on the machine is 32 bits and
it may be assumed to be of equal to size of accumulator register. In order to execute instructions
the machine has an additional Instruction Register (IR) of size 32 bits as each instruction is of
this size. Perform the following tasks for the machine.
(i) Design suitable instruction formats for the machine. Specify the size of different fields that
are needed in the instruction format. Also indicate how many different operations can be coded
for this machine. Give reasons in support of your answer. (3 Marks)
(ii) Put some valid values in registers and memory locations and demonstrate

examples of different addressing modes of this machine. (1 Mark)

(iii) Assuming that the instructions are first fetched to Instruction Register (IR) and memory
operands is brought to DR register; indirect operand is brought to Accumulator register; and
result of operation is stored in the Accumulator register; write and explain the sequence of
micro-operations that are required for fetch and execute cycles of an instruction which performs
subtraction of two operands having addressing mode bits as 00. Please note that one of the
operand is Indirect Register Operand and the second is a direct memory operand. Make
and state suitable assumptions, if any. (6 Marks)
(b) Assume that you have a machine as shown in section 3.2.2 of Block 3 having the
microoperations as given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are
8 bit registers and contains 11000011 and 11100101 respectively. What will be the values of
select inputs, carry-in input and result of operation (including carry out bit) if the following
micro-operations are performed? (For each micro-operation you may assume the initial value of
R1 and R2 as given above) (2 Marks)
(i) Add R1 and R2 with carry
(ii) Decrement R1
(iii) Shift right R1 twice
(iv) AND R1 and R2
(c) What is the role of Control Signal in execution of an Instruction? Block 3, page number 68-
70, explains the timing sequence for execution of ISZ instruction. Explain execution of an
ADDITION instruction with the help of micro-operations and timing sequence. (3 Marks)
(d) What is the role of micro-programmed control Unit? How a micro-program is executed?
Explain with the help of a diagram. (2 Marks)
(e) List and explain the characteristics of RISC machines. A RISC machine has 256 registers
out of which 64 registers are reserved for the Global variables and 64 for Instruction related
tasks. This machine has been designed to have 12 registers for storing three input parameters,
three output parameters and six local variables for a function call. Explain with the help of a
diagram, how the overlapped register window can be implemented in this machine for
function/procedure calls. You must explain how the parameters will be passed when a function
calls another function. How many levels of procedural calls, such a machine can support? (3
Marks)
Q4. (Covers Block 4)
(a) Write a program using 8086 assembly Language (with proper comments) that accepts an
input of ten characters from the keyboard and store them in the memory. It then converts all the
lower case alphabets of this stored string to uppercase alphabets. Make suitable assumptions, if
any. (7 Marks)
(b) Write a program using 8086 assembly Language (with proper comments) that find the sum
and average of 10 byte numbers stored in two different arrays of size 5 each. (7 Marks)
(c) Explain the following in the context of 8086 Microprocessor (6 Marks)
(i) Use of Segment Registers
(ii) Use of Interrupts in Input/output
(iii) .com and .exe programs