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Philippines Fiasco, pg. 16
PRINTED CIRCUIT
DESIGN & FAB
pcdandf.com
circuitsassembly.com
November 2016
Fill the Void

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NOVEMBER 2016 VOL. 33 NO. 11
FIRST PERSON
6
PRINTED CIRCUIT
DESIGN & FAB
CAVEAT LECTOR
Plugging the leaks.
Mike Buetow
MONEY MATTERS
15 ROI
FEATURES
20
THERMAL MANAGEMENT
Cybersecurity is all fogged up.
How AC Currents Affect PCB Trace

Temperatures, Part 2
Peter Bigelow
Past articles looked at the relationship between trace current and temperature for pulses that propagated through the
trace. A look at the slightly more complicated topic of analog
16
FOCUS ON BUSINESS
waveforms to see if the same conclusions apply.
Making sense of the Philippines.
by DOUGLAS G. BROOKS, PH.D. and

DR. JOHANNES ADAM
Mike Buetow
18
24
PCB MATERIALS
GLOBAL SOURCING
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Newly developed treatment technology for copper foil
by OSAMU SUZUKI, AKITO YOSHII, HIRONOBU TSUBURA, MAKIKO SATO,

NAOKI OBATA and YOSHINOBU KOKAJI
Greg Papandrew
TECH TALK
ON THE COVER
BTC voiding on a 64-pin
QFP. (Photo courtesy Alpha
Assembly Solutions)
30
EMS
Jabil Steps Up
Move over Nike: A new plant in a new market has one of the worlds top ODM/EMS companies
19
walking on air over its prospects.
DESIGNERS NOTEBOOK
For reference or not?
by MIKE BUETOW
32
Duane Benson
38
Timothy ONeill
40
GETTING LEAN
Shedding light on wastes in
LED assembly.
Dennis McNamara and Yousef Heidari
of comparative results. Observed were the effects with both high-voiding and low-voiding pastes.
by BROOK SANDY-SMITH
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ONLINE AT CIRCUITSASSEMBLY.COM
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by ACS INDUSTRIAL SERVICES
Investing in the future of test.
43
DEFECTS DATABASE
Spitting it out.
Extending the Life of Printed Circuit Boards

Printed circuit boards don't last forever even the most expensive ones. But plenty of
TEST AND INSPECTION
Robert Boguski
How Can the IoT Be a Solid Rock to Build Products and Profits On?
by JON HOWES

42
How Stencil Design and Reflow Profiles Affect Variation in QFN Voiding
Data: A Case Study
A review of several cases where changing the stencil design or reflow profile dialed in the variation
TECH TIPS
Getting to the bottom of
void problems on QFNs.
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NOVEMBER 2016
CAVEAT LECTOR
Industry Leaks and What to Do

MIKE
BUETOW
EDITORIN-CHIEF
T didnt take the dumping of hacked emails from

politicians or a trove of government secrets on
Wikileaks for those in IT to know that cybersecurity is a really big deal. In the rush for the world
to connect its digital systems, however, it seems more
than a few others have lost their bearings.
But cybersecurity is just one aspect of the
frightening holes in the defense industry these days.
Foreign nationals own big stakes in some major US
defense suppliers. The divided loyalties that come
with such holdings generally get a pass with the
Defense Department, Im told. If we cant protect
our most important secrets at Lockheed or Booz
Hamilton or Boeing from outsiders, however, it
strains logic to believe they cant or wont be
compromised from the inside.
Such administrative indifference affects the
entire supply chain. According to the Department of
Commerce, the US is down to 202 merchant bare board
plants spread across 185 fabricators. Thats a staggering
drop in number from just 15 years ago. More to the
point, the capacity of key technologies is even slimmer.
This fall the DoC, with help from the Naval
Surface Warfare Crane Division, completed initial
analysis on a comprehensive study of the US PCB
industry. Speaking at PCB West in September, Mark
Crawford, senior trade and industry analyst at
the Commerce Departments Office of Technology
Evaluation, noted the growing disconnect between the
needs of the US government and the ability of the US
supply chain to meet them. According to his survey,
DoD spending on PCBs was $544 million in 2015,
of which 54% was supplied by shops with revenues
of $10 million to $40 million. In other words, the
majority of these custom components are coming
from companies whose annual sales are less than
what Mark Zuckerberg earns per week.
While it didnt take a survey to know there
are a grand total of three shops certified to MILPRF-31032 with microvia capability and four listed
to the high-frequency slash sheet, the DoC data add
a government agency stamp to what has long been
known by insiders: US shops are getting eaten alive.
Clearly the industry is under stress from offshore
competitors that dont have to play by the same
rules, Crawford said.
If the survey was intended to generate convincing
data that the US lacks sufficient critical military PCB
capacity, Id say it succeeded. Its long past time this
was made a priority. What should be done? Heres
one editors suggestions:
US defense contractors need a closed intranet

system, one accessible only by a relative handful of
key and highly vetted players. Such a network has
been suggested before; funding and implementation
are long overdue.
Educate lawmakers as to what a PCB is and its
importance to US defense. This means handpicking
articulate industry spokespersons, rather than
turning scores of well-meaning but uninformed
company execs loose in D.C. for the day. Ive been
to enough industry lobbying days to know the
intentions are good, but the execution is wanting.
Too many (read: all) legislators look at boards as
just another component, and not a particularly
critical one at that. Its time to send in the pros.
Get the top 10 suppliers of bare boards of critical
technologies to the DoD for a day-long meeting.
Round up as many key Congress members on
defense and appropriations as possible. Define for
those buyers what each shop does, and underscore
the financial state of each company relative to
importance of the product.
Consolidate procurement and regulations. ITAR is
administered by the State Department. Purchasing
(Defense Procurement and Acquisition Policy) and
inventory control (Defense Logistics Agency) are
overseen by various arms of the DoD. There are too
many teams with too many competing missions.
And get some help to DSCC, which has no chance
of properly auditing and certifying board suppliers
on a skeleton crew that cant leave the office.
Designate a point person for industry to share its
concerns over IP theft (or the potential thereof) and
other found weaknesses in the electronics supply
chain. And make public that persons name, so that
whistleblowers know whom to call.
As Peter Bigelow suggests in ROI this month, the
US defense supply chain should stay out of the
cloud, at least until such time those servers and
all related access points can be properly secured
(never, probably).
Stop with the overarching emphasis on price.
When the US is paying $250 million for each F-35B
fighter plane, its offensive to try to save 10 cents on a
critical component.
In the 80s, I recall my high school social studies
teacher mocking the US government for paying
$7,500 for a coffee maker. Those were the days. With
IP and military security on the line, its time for a
return to the past.
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EDITED BY MIKE BUETOW
AROUND THE WORLD
PCD&F People
Photomachining named Mathew Hannon
laser applications engineer.
Seacole Specialty Chemical named Walt
Forgacs printed circuit board account
manager.
Taiyo named Alyssa Orellana customer
service representative.
Ventec appointed Denis McCarthy Jr. technical sales account manager - USA.
PCD&F Briefs
Altium completed its acquisition of Transfer
BV, a longtime reseller of Altiums PCB
CAD tools. The acquisition includes a combination of cash, plus additional payments
based on sales performance over the next
three years.
Dassault Completes CST Acquisition

VELIZY-VILLACOUBLAY, FRANCE Dassault Systmes on Oct. 3 announced the
completion of its previously announced acquisition of CST - Computer Simulation
Technology for 220 million euro ($243 million).
Dassault will integrate CSTs software into its portfolio of PLM and related
software tools.
EM simulation is an essential part of the development of connected products
to ensure the performance, reliability and safety of their interactions with their surrounding environment. With the integration of CST, Dassault will offer full spectrum EM simulation of autonomous cars, connected homes, medical equipment,
wearable electronics and other smart objects, the company said.
Dassault first announced the deal on July 21. Dassault paid cash for CST, and
the transaction will be immediately accretive to earnings.
CSTs 2015 revenue was about 47 million euro ($52 million). MB
Abstracts Sought for PCB West
Mentor Graphics announced it has joined

the Wide Band Gap Integration (WBGi)
power electronics consortium.
ATLANTA UP Media Group seeks abstracts for PCB West 2017, to be held Sept.
12 - 14 in Santa Clara, CA. The event includes a three-day technical conference and
one-day exhibition to be held at the Santa Clara Convention Center.
PCB West annually provides a conference and exhibition focused on the design
and manufacture of PCBs, HDI, electronics assembly and circuit board test. The
September 2016 event attracted nearly 2,000 attendees.
Papers and presentations of the following durations are sought for the technical
conference: one-hour lectures and presentations; two-hour workshops; and halfday (3.5 hour) and full-day seminars.
Papers and presentations must be noncommercial in nature and should focus on
technology, techniques or methodology.
Abstracts of 100 to 300 words and speaker biographies should be submitted to
UPMG atpcbwest.com/submit-an-abstractby Feb. 3.
Anyone may submit an abstract to present a course at PCB West 2017, and
presenters may present more than one paper or teach more than one course. A separate abstract must be submitted for each course. If selected, a detailed presentation
outline and final paper or presentation is due Jul. 25. MB
Nano Dimension will form a new subsidiary and will transition its 3D printing activities to the new entity.
PCB West Attendance Best Since 2001
Arena Solutions has teamed with Altium

to deliver a bidirectional integration leveraging EDAConnect for Altium/Arena. The
integration creates a direct flow of parts
metadata between Arena PLM and Altium,
along with transparent BoM publishing
from Altium to Arena PLM.
BotFactory has raised $1 million toward
expanding sales and marketing efforts
and product development of its Squink
PCB printer.
CST acquired Aurora Software and testing
(Aurorasat).
Solo-Labs announced the 5,000th download of its SoloPCB-Designer 2.0 free PCB
design software.
Zentech Manufacturing in September
acquired Interconnect Design Solutions,
a Charleston, SC-based electronics design
engineering company. IDS founder Mike
Brown will remain with Zentech as vice
president of engineering services.
CA People
Benchmark
Electronics
announced Paul J. Tufano as
president and chief executive officer. Tufano was CFO of
Alcatel-Lucent from 2008-2013,
and was CFO of Solectron. He
replaces Gayla Delly, who resigned as both
the top executive and as a member of the
board to pursue other interests.
ATLANTA PCB West 2016 show attendance rose 3% year-over-year, to nearly 2,000
attendees, UP Media Group announced. It was the annual PCB industry trade shows
highest turnout since 2001.
Registration for the 25th annual show was up 6% from 2015, added UPMG.
Overall, nearly 2,000 printed circuit board designers, fabricators and electronics
assemblers, managers and suppliers attended the September trade show, UPMG said.
It was the seventh straight year both show registration and actual attendance
figures have climbed.
Technical conference registration rose more than 20% year-over-year. Attendees
gravitated toward sessions on resolving fundamentals and practical solutions to engineering and design problems. More than 24 designers underwent IPC certification
during the conference as well.
The sold-out show floor featured more than 100 companies occupying 110
booths, and exhibitors were outwardly pleased about their leads from the consistently busy show.
It is remarkable how, after 25 years, the demand for printed circuit board
knowledge continues unabated, said Mike Buetow, editorial director of UPMG.
This years show was our largest ever in terms of the number of exhibitors, with
twice the number we had just five years ago. And the technical conference just keeps
growing, too.
NOVEMBER 2016
youtube.com/user/aimsolderaim
EDITED BY MIKE BUETOW
AROUND THE WORLD
ERSA North America hired

Gustavo Perez to its field
service engineering team in
Mexico. Perez has been in
the industry for more than
10 years, most recently with
Seho, where he worked on wave, reflow
and selective soldering machines.
Kulicke & Soffa appointed Fusen Chen
president and CEO.
Libra Industries promoted William Redmon to design manager. He has been with ACD,
now Libra, for more than 11
years, previously as senior
systems analyst.
Plexus promoted Steve Frisch
to executive vice president
and chief operating officer.
He joined Plexus in 1990 as
a design engineer, and has
held roles as executive VP and
chief customer officer, regional president
EMEA, and led Plexus Global Engineering
Solutions unit.
Simplimatic
Automation
named John Artman vice
president of business development, assembly sales, and
marketing and Shawn Semer
as vice president of packaging
sales to aid in further promoting the companys rapid sales
growth and development.
SMS named Robert Colclough
UK sales manager and appointed Graham Shaw chief of operations.
SMTA announced Jeff Kennedy as its new
president, superseding Bill Barthel.
SolderStar named Chris Williams business development
manager. He has 15 years
experience in electronics, most
recently UK distribution and
OEM manager at BOFA.
Universal Instrumentsappointed Dr. Sean
Lu general manager, Asia.
CA Briefs
AIM Solder added Alfatec Indstria e Comrcio as a licensed manufacturer of AIMs line
of solder assembly materials in Brazil.
Asteelflashinstalled four Fuji NXT IIIs and
one Fuji XPF component mounter at its
manufacturing facility in La Soukra, Tunisia.
Creation Technologiesinstalled two Ace
Production Technologies Kiss-102IL selective soldering systems in Mexicali, Mexico.
Enics Schweizwill cut up to 25% of its
workforce in Turgi, Switzerland.
10
PCB West 2017 will take place Sept. 12-14 at the Santa Clara (CA) Convention
Center. MB
Deal Struck for Atotech Sale

COURBEVOIE, FRANCE Total has agreed to sell its Atotech plating chemicals
business for $3.2 billion to a private equity firm, according to published reports.
In sealing the deal, Carlyle Group reportedly beat out other private equity
firms, including CVC Capital Partners and Cinven.
Berlin-based Atotech has annual sales of $1.1 billion. Carlyle reportedly
says it expects continued growth for Atotech, but hasnt divulged its plans for
the company.
In May,Total announced it was putting Atotechon the block,saying the
unit no longer fit Totals strategic vision. CD
Survey to Assess Fine Circuit Pattern Inspection

HERNDON, VA iNEMI is conducting an industry survey to assess measure-
ment and inspection capabilities for fine circuit pattern substrates used in high
bandwidth applications.
Integrated silicon packages such as SiP are becoming more popular as electronic packaging solutions, and this technology is driving the need for finer and
finer circuit pattern designs. However, optical inspection methodologies are
reaching their limits in detecting defects efficiently at these smaller dimensions.
This potential technology gap could negatively impact yield performance and
quality validation of the substrates or boards used for integrated SiP packages.
The lack of inspection capability for fine lines and spaces (<5m) on the
panel size substrates/boards used to fabricate SiP carriers supporting high I/O
or high bandwidth memory or other components could have a negative impact
on yield performance or reliability, iNEMI says.
As such, the consortium is conducting a survey to assess the measurement
and inspection capability for the substrates. This problem is defined as a technical gap in the iNEMI package roadmap as 2m/2m line space design
rules, and iNEMI is planning to make recommendations in this area relative to
product requirements and process/material capabilities needed to close the gap.
To participate, visit surveymonkey.com/r/WPLBCLJ. CD
Nan Ya to Take Full Ownership of PFG

PITTSBURGH Nan Ya Plastics will acquire the remainder of its ownership
interests in its two PFG Fiber Glass joint ventures from PPG. Nan Ya and PPG
currently each hold a 50% stake in the JVs.
The transaction is expected to close by the end of 2016. Financial terms
were not disclosed.
PFG manufactures yarn fibers for laminates and fiber-glass reinforcement
materials for automotive applications. It has production facilities in Chia Yi,
Taiwan, and Kunshan, China.
The companies formed the joint venture in 1987 to establish the Taiwan
plant. In 2001 it formed a second JV to create the China site. MB
Researchers Develop Counterfeit Parts

Image Database
GAINESVILLE, FL A group of professors at the University of Florida have
formed a new counterfeit IC image repository aimed at giving industry a solution for identifying fake parts.
NOVEMBER 2016
Move Forward Faster.

CONFERENCE: September 12 14, 2017
EXHIBITION: Wednesday, September 13
Santa Clara Convention Center, CA

pcbwest.com
AROUND THE WORLD

Europlacer appointed Bergen Associates
distributor for India.
Foxconn has struck a deal to reopen a
Nokia manufacturing plant in India, pending government approval.
HansaMatrix has begun implementation of
a 350,000-euro upgrade to its EMS plant in
Ventspils, Latvia.
IEC Electronics has signed an agreement
to sell its manufacturing facility in Albuquerque for an aggregate purchase price of
$5.75 million. The company will continue to
perform EMS work at the site after the sale.
IEC also confirmed a workforce reduction
of approximately 73 full-time employees at
its NY facility.
The ITC is investigating whether imports
of certain memory modules are infringing
existing patents.
Juki presented Horizon Sales with three
of its Representative of the Year awards
for 2016.
Libra Industriesinstalled an Omron CDK
VP5200-V SPI.
Mycronic received orders for several
MY600 jet printers from a high-volume
Asian customer.
Nordson won the SMTA Corporate Partnership award.
NTS expanded its test and inspection facility in Chicago.
PanasonicFactory Automation announced
the opening of innovation centers in
Bangkok, Hanoi, and Chicago, aimed at
showcasing its manufacturing technologies and equipment.
Rehm Thermal Systems welcomed almost
150 attendees to its annual technology day
on Sept. 29.
Scanfil has entered mandatory negotiations to restructure its EMS operations in
Vantaa, Finland.
Selcom installed an AAT Aqua Rose cleaner
and tester.
Sinbon Electronics has broken ground on a
new plant in Miaoli, Taiwan, where it plans
to conduct R&D and assembly.
EMS firm Target Corp. has filed for courtsupervised protection and is up for sale.
UKC is expanding its Hanoi plant from
component assembly to include resin
manufacturing.
Universal Instruments opened its newly
renovated Asia Advanced Technology Center in Shanghai, featuring an expanded
product demonstration and training area
and several equipment lines.
12
Located atcounterfeit-IC.org,the database contains images illustrating

defects found through physical inspection for a large number of electronic
components.
Counterfeit electronics are a prevailing supply chain issue, which have continued to become more widespread in recent years. Since most of the chips in
the market are not equipped with mechanisms to aid in counterfeit detection,
physical inspection is the most relied upon counterfeit detection approach.
Physical inspection requires a wide range of imaging modalities (optical,
SEM, x-ray, etc.), materials characterization tools, and other tests to extract
defects (anomalies) on the inside and outside of a components package,
chip leads, ball grid, etc. Any research that could reduce the time and cost
associated with physical inspection would be an immense help to industry and
government, but is held back in large part by a lack of data.
The new site is a resource for learning about counterfeit defects and what
they look like; compiling information about the frequency and correlation
of defects found from optical inspection of ICs; optimizing tests and reducing the inspection time/cost; and developing automated defect detection and
counterfeit IC classification based on image processing and machine learning.
Currently, the repository contains optical images obtained by the FICSR team
only, with x-ray and SEM images to be added in the future. The website also
possesses the capability for registered users to add their own defect content
and images.
The project is maintained by The Florida Institute for Cyber Security
Research and sponsored by the National Science Foundation. MB
SAE Releases Counterfeit Parts

Mitigation Guidelines
DETROIT SAE in September released ARP6328, a new guideline for implementing a counterfeit mitigation program in accordance with AS5553.
The document provides definitions and guidelines for developing a counterfeit electronic parts avoidance, detection, mitigation and disposition system.
The document is intended to supplement requirements of a higher-level
quality standard: for example, AS9100 and other quality management system
documents. MB
Fabrinet Acquires Exception Global

CEM Solutions
BANGKOK Fabrinet acquired UK-based Exception Global CEM Solutions for
approximately $13.5 million in cash.
Exception provides contract electronics manufacturing services, with
approximately 80% of its revenue derived from customers in Europe.
Fabrinet has enjoyed exceptional growth over the past several years, primarily with customers in the US and Japan, and there are tremendous opportunities for growing our business in Europe, said Tom Mitchell, chairman and
CEO. With this acquisition, we are establishing a strong foothold in Europe,
which will allow us to grow our business with European customers, and give
them access to our advanced low-cost manufacturing services in Thailand,
particularly in our new facility in Chonburi that is coming online and ramping
in the next several months.
Exception operates a single manufacturing plant in Calne, Wiltshire, UK.
Fabrinet anticipates the transaction will have an immaterial impact on revenue and net income in the first quarter of fiscal 2017. MB
NOVEMBER 2016
Something BIG
is About to
BE REVEALED
NPI Awards 2017

NEW PRODUCT INTRODUCTION AWARD
REGISTRATION NOW OPEN.
pcdandf.com/pcdesign/index.php/editorial/npi-award
EDITED BY CHELSEY DRYSDALE
MARKET WATCH
METALS INDEX
DATE
MILITARY CHATTER
Trends in the U.S. electronics equipment market (shipments only).

% CHANGE
JUNE JULY AUG. YTD%
Computers and electronics products
0.4
2.4
0.2
-6.2 7.7 -0.7 -25.2
Storage devices
-3.4
21.6
-12.4
4.2
Other peripheral equipment
-7.0
5.2
-1.7
-20.0
Nondefense
communications equipment
4.3
15.0
-7.7
A/V equipment
-0.6
1.7
1.6
44.8
Components1
-1.7 2.6 2.4 12.4
Nondefense search and

navigation equipment
3.2
2.0
-1.8
10.1
Defense search and

navigation equipment
0.7
3.9
-4.2
1.2
-0.5
2.5
0.5
6.8
Medical, measurement and control

rRevised.
nearly 22 million by 2021, increasing from seven million in

2016, according to ABI Research. The devices are migrating
out of the gym and into the office, with the wearable scanner
market experiencing rapid expansion, says the firm.
Wearable ring scanners, such as those from Honeywell
and Zebra, rely on a ring barcode scanner that connects to
55.7 57.0 56.9 49.1 55.1
Production
52.6 54.7 55.4 49.6 52.8
Inventories
45.0 48.5 49.5 49.0 49.5
Customer inventories
50.0 51.0 51.0 49.5 53.0
Backlogs
47.0 52.5 48.0 45.5 49.5
Sources: Institute for Supply Management, Oct. 3, 2016
14
$0.74
$0.82
$0.81
$0.88
$0.96
$2.17
$2.20
$2.09
$2.19
Shipments of wearable devices reached 22.5 million in

the second quarter, according to IDC, up 26.1% yearover-year.
DRAM contract prices continued to grow in August,
with prices for 4GB modules reaching as high as $14,
according to DRAMeXchange.
German PCB manufacturers grew 4.1% year-over-year
in June, ZVEI said.
Conformal coatings sales will grow 4.7% compounded
annually between 2016 and 2021 to $12.28 billion on
demand for PCBs and automotive products. In 2015,
acrylic conformal coatings accounted for the largest
share by type in terms of volume as well as value, followed by epoxy.
LONDON Enterprise wearable scanner shipments will reach
New orders
LME Cash Seller and

Settlement for Lead
Hot Takes
Wearable Scanner Shipments

Looking Good
51.3 53.2 52.6 49.4 51.5
$9.21
year-over-year in the second quarter to $167.8 million.

The four-quarters moving average for PCB & MCM,
comparing the most recent four quarters to the prior
four quarters, increased 0.2%, said the Electronic System
Design Alliance (formerly EDAC).
Overall electronic design automation industry revenue
increased 5.6% in the second quarter to $2.01 billion. The
four-quarters moving average increased 3.6%.
Computer-aided engineering revenue ticked up 0.8%
to $662.4 million. The four-quarters moving average for
CAE decreased 1.3%.
PUNE, INDIA The global medical electronics market is

expected to reach $4.41 billion by 2022, growing at a CAGR
of 5.4% between 2016 and 2022, says RnR Market Research.
Monitoring devices are expected to grow at the highest rate because of the increasing use of patient monitoring
devices in outpatient care departments, ambulatory care centers, and home care settings.
North America is considered the largest market for
medical electronics, driven in part by an improved health
care infrastructure. The APAC market is expected to grow
at the highest rate during the forecast.
PMI
$8.75
SAN JOSE PCB and MCM design software sales rose 8.1%
Healthy Growth for Medical Electronics
MAY JUNE JULY AUG. SEPT.
$8.10
Q2 PCB CAD Revenue Up 8%
*Preliminary.
semiconductors. Seasonally adjusted.
Source: U.S. Department of Commerce Census Bureau, Oct. 5, 2016
$7.90
a wearable computer and allow the user to access and

update information about the scanned product. Ring
barcode scanners, glove scanners and smartglasses are the
most popular forms.
1Includes
US MANUFACTURING INDICES
$7.11
LME Cash Seller and $2.33

Settlement for Copper
6.0 -6.1 1.0 -0.1
Defense communications equipment -1.1
LME Cash Seller and

Settlement for Tin
Handy and Harman $227.89 $284.75 $296.27 $280.81 $282.12

Silver (COMEX Silver)
3.5
Computers
10/5/15 7/4/16 8/1/16 9/5/16 10/3/16
KEY COMPONENTS
Book-to-bills of various components/equipment.

Semiconductor
APR. MAY JUNE JULY AUG.

equipment1
Semiconductors2
PCBs3 (North America)
1.09 1.09 1.00 1.05 1.03

-6.21% -7.27% -5.67% -2.83%r 0.54%p
1.02
1.01
0.98
0.94
1.02
Computers/electronic products4 5.93 5.92 5.91 5.83 5.82

Sources: 1SEMI, 2SIA (3-month moving average growth), 3IPC, 4Census Bureau,
ppreliminary, rrevised
NOVEMBER 2016
In the Clouds
Cybersecurity can seem like a dense fog that threatens commerce.
ANYONE WHO TOUCHES an electronic device has
been introduced to the cloud. In recent months

I have seemingly been surrounded like a fog by
opportunities, issues and potential problems pertaining to the cloud. Frankly, I yearn for the good old
days when all we wanted was a clear sky.
First, the good. For technically challenged folk
like me who often screw up something on our home
PCs, to the chagrin of screaming family whose priceless file or picture we just lost, I am frequently saved
by the backup in the cloud. The ease and speed in
which that priceless file can be resurrected is nothing short of amazing. Truly there is value to not having to own a separate server to back up data, regardless of how important they are or aren't.
The bad, at least in my opinion, is that software
programs are now hosted more and more in the
cloud. This trend has a double whammy impact.
First, the cost of the software is almost always significantly more expensive than in the past, when you
could purchase a seat outright. The offset is the most upto-date version of software will always be immediately
at your disposal. That convenience is usually not worth
the added cost, however; yet it is becoming increasingly
difficult to find tools that are not cloud-based.
The second whammy is automagic software
updates may not be all that convenient, as the update
schedules can no longer be managed. If an upgrade is
significant, the unexpected and unplanned learning
curve may be extremely time-consuming, and might
come right when you cannot afford to invest the time.
Its the dark side of the cloud that has me most
concerned, however, and like most dark things there
are multiple and conflicting aspects that make it so.
Specifically, Im referring to data security.
Given recent headlines, from the drum beat of
WikiLeaks to the hacking of retail customer and credit
databases, the risk is clear that what is transmitted and
stored in the cloud may not be as safe as we desire.
Clearly, cloud storage of sensitive data is a big concern.
Of equal concern is the transmission of data to and
through the cloud, even if ultimately it is stored in a
dedicated server in your own facility on terra firma!
And this is where this problem becomes so baffling.
Most of banking, commerce and manufacturing are
pushing the cloud as the host of choice for everything
from an individuals music, pictures and banking to corporate cash management, personnel records and intellectual property. The cloud today is the protocol of choice
for most to handle the majority of their data storage and
management activities. On the other hand, a growing
chorus of hold on is being sung by individuals and
companies, especially in the defense industry as well as
government that only want secure and encrypted
systems to be used for data storage and transmission.
NOVEMBER 2016
The conundrum is, where are those systems and

how costly are they to install and maintain?
While talking with a number of people about
how to upgrade to a secure system for my company, it has become evident theres no consensus
definition of secure, and even if the technology is
available to achieve it at some level, it will require
constant upgrading at a level and speed most cannot
digest. It will also require companies such as Apple
and Microsoft to admit their cloud-based programs
may not be as secure as they boast.
Case in point: You have a secure, well-encrypted
server on the premises, with backup in a controlled
environment offsite, but the e-mail systems used
to transmit data back and forth from customers to
subcontractors may be suspect. Or, your cloud-based
Excel and Word documents may not be secure. Or,
the e-mail encryption might need to be updated/edited/rewritten frequently to stay current on all systems/servers in the communications chain. Throw
in increased use of password and security codes transmitted as text or voice over cellphones as an added
security, and the layers of computers in service that
are not current technology, and it all becomes almost
impossible to manage, to say nothing of safe.
Part of me wishes the solution were as simple as
going back to a paper system that does not rely on
electronic data being transmitted and stored. Clearly
that is not feasible. What does need to take place is
for knowledgeable people to first debunk the myths
of cybersecurity what is real vs imagined; what is
important vs. just desirable and then to understand
that industry resources are limited. Whatever solution,
results must be deemed necessary, not just desirable,
to ensure data security can be established and maintained. And the solution must be affordable by companies large and small, not just national governments.
Everyone wants confidence their data, be it family pictures or classified IP, are safe and secure where
stored and when transmitted. With the heightened
concern over cybersecurity, many private and public
sector organizations are diligently working to come
up with solutions that will protect what is important.
I just hope that, when a solution is developed, common sense is part of the equation. Common sense in
what is needed vs. what might be considered ideal.
Common sense as to how many layers of communication and storage are involved by commerce and
industry when producing a product or providing a
service. And common sense as to what is affordable
by commerce and industry, stakeholders that do not
have limitless budgets.
Hopefully, the pursuit of cybersecurity will not
make the cloud a fog that threatens industry
commerce. PCD&F
PETER BIGELOW
is president and CEO
of IMI (imipcb.com);
pbigelow@imipcb.
com. His column
appears monthly.
15
FOCUS ON BUSINESS
Crises in Southeast Asia

The region is struggling with drugs and new leaders coming online. What does this mean for EMS?
Mike Buetow is
editor in chief of
PCD&F/Circuits
Assembly; mbuetow@
upmediagroup.com.
16
THE LATE LEADER of Intel Andy Grove once wrote

only the paranoid survive. Id add that their
chances of survival are measurably enhanced when
theres an army at their disposal.
Paranoid is one word to describe the recent
actions of Rodrigo Duterte, the Filipino president
since May. He assumed office after a long career
as a lawyer and then politician, during which time
he became known for supporting if not leading vigilante militias reportedly responsible for
thousands of deaths of drug pushers and users in
and around Davao City, where he served as mayor
for two decades.
Since taking office, Duterte has shown no signs
of toning down his act. The extrajudicial killings
continue, and he has made verbal attacks on leaders in Europe, the UN, the US, even the Pope.
If the unpredictable side of Dutertes personality weren't enough, he then announced a severing
of military and economic ties with the US.
This move has sent shivers down the spines of
companies doing business in the Philippines. US
businesses alone have pumped nearly $5 billion
into investments in the country. Once the dust has
settled, its possible the Philippines will adopt a
more neutral global stance. Indeed, immediately
after Dutertes announcement, the Philippine trade
minister tried to walk back his statements. But the
Philippine leader is pushing ahead by engaging
China as a key trading partner.
The situation unfolding in the Philippines,
while extraordinary, is not unique to Southeast
Asia. Bhumibol Adulyadej, Thailands king since
1946, just passed away. Although the country
has been run by a military junta since 2014, the
military has recognized the monarchys place in its
society, and the respect has been returned.A new
charter passed by referendum in August and an
election scheduled for late next year could return
some level of democracy to the country, or it could
result in even greater tension between civilians and
the military.
India may be an outlier in its approach, as
its prime minister, Nehandra Modi, remains UScentric. That said, the Indian leader has hedged
his bets by holding recent talks with heads of Brazil,Russia and China, among others.
This turbulence, some of it unintended, some
of it calculated, is surprising only in the sense that
it all seems to be happening at once. Certainly,
leaders can be expected to try to broaden the markets for their respective nations. More shocking
has been the approach, which at times has been
tactless and, in Dutertes case, highly personal.
One industry observer noted to me that the situation recalls the rise to power of Lee Kuan Yew, the
founding father of Singapore. When Lee took over,
he made his mission the scrubbing of antisocial
behavior, especially drug use. Drug lords and traffickers were put to death after quick trials. Other
lawbreakers were dealt with harshly as well. He
also declared Singapore open for business, and the
city-state has become the 20th largest exporter in the
world. Its possible, this observer says, the new crop
of leaders are taking a page from Lees playbook.
Supply chain effects. Every national leader has
an obligation to improve the lot of their constituents. Its not at all obvious, however, that each
of these leaders is acting rationally. The political
unrest, to say nothing of the violence, cant be
good for business.
Many of these nations, of course, have deep
ties to the electronics supply chain. Any country
that seeks to become a major player in electronics will end up doing considerable business with
the US.
Contacts in the Philippines indicate great discomfort with the positions of Duterte. OEMs that
want to move programs from China due to IP or
other concerns now suddenly find themselves in
the awkward position of not knowing whether
their preferred landing spot will be any better. And
while there has been no immediate outward impact
to the bottom line, given the long lead times in
electronics, the better indicator will come 12 to 18
months from now.
To put all this in context, perhaps rather than
Singapore, a more timely comparison is with
Mexico. Mexico has suffered enormous casualties
from the drug wars. Kidnappings and murders
have been par for the course, and non-nationals
are often advised not to travel outside in certain
cities after 5 pm. Talk on returning programs to
North America has been noticeably muted of late.
Is the safety factor at play? If so, is the heavyhanded approach of these Southeast Asian nations
the smart long-term play, even if it means a loss
of business in the short run? And despite its blind
eye toward IP and ever-changing regulations, will
Chinas relative stability make that nation the
beneficiary? CA
NOVEMBER 2016
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GLOBAL SOURCING
Tightening the Chain

Why the supply chain begins with the manufacturer.
WHETHER THE ORDER comes from a domestic or inter-
GREG
PAPANDREW is
a PCB sales and
marketing advisor;
greg@ledlogistics.com.
18
national source, the PCB supply chain begins with the

manufacturer. For cost-conscious PCB buyers with a
consistent annual buy using technology that doesnt
necessarily push the envelope, working directly with
offshore manufacturers is actually the best option.
Its funny how things come full circle. Over 10 years
ago, I wrote a column for Circuits Assembly discussing
pros and cons of using a broker versus a direct relationship with an offshore manufacturer. What I wrote then
still applies when trying to establish a direct relationship with any manufacturer. But now, you dont have
to be nearly as big a fish to be successful. You still must
choose wisely, of course, and be wary of gimmicky
slogans. When Swimming with Sharks (the title of
another of my columns), you will inevitably get bit.
So how does a PCB buyer successfully go direct
to an offshore manufacturer? As hundreds of OEMs
and contract manufacturers in North America have
found, the vetting process is not all that different
from any other new manufacturer selection, offshore
or domestic. And it can be done without that 14-hour
flight from LAX.
Start by asking questions of colleagues from
within the industry. Find out who they use, and why.
Theres nothing better than a customer who gives a
positive testimonial about a manufacturer. Ask hard
and probing questions about communication and
delivery, as well as how the manufacturer in question
has handled quality problems, as issues will occur,
just as with any other supplier.
Then, take an honest look at your annual PCB
spend and determine which of your part numbers
have a forecast available. Dont confuse forecasting
with high runner, as offshore builds far smaller
production lots than it did 10 years ago. However,
the more orders you have that are consistent runners,
the better your price negotiation power will be.
It is okay to have more than one vendor, and it
may make sense to keep an order produced domestically or with a broker. No one board house can do
everything; having multiple manufacturers vying for
your business helps keep pricing in check.
Check out a potential vendor by studying its website and reviewing its quality credentials (such as UL and
ISO certifications). Ask overseas vendors to fill out a
new vendor survey form and request a Quality Control
manual that includes an organizational chart. Request
domestic references and call those references, asking
pointed questions. Ask the vendor questions specific to
your operation, and make sure all potential manufacturers understand your technology and scheduling needs.
Communication with offshore has greatly
improved from 10 years ago. The ability of offshore
vendors to converse in English, spoken and written,

gets better every year. More important, the learning
curve on both sides of the world has become much
flatter, allowing for good back-and-forth communication concerning the quality and technical challenges
of most PCB orders. A good inside sales contact is
needed, either through a local rep, a person in the
vendors US office (if they have one) or direct with
the offshore factory. Make sure you have at least one
contact on either continent.
If prospective vendors seem promising, send test
quotes and make sure they respond in a timely manner.
Check that the price quoted is a landed price, meaning
freight is included. This is very important. See if the
delivery time and payment terms are acceptable. If all
looks good, have a test part number built and review
the order process from engineering to receipt. Did the
vendor have too many engineering questions? Did the
order come in on time? Was it packaged well, and did
it contain all the required paperwork? More important, how do the boards look?
Working directly with an offshore manufacturer
can have its payment challenges. Years ago, most offshore vendors wouldnt offer immediate terms. Find a
manufacturer that will offer terms and/or accept a local
check. Working with a broker does make the payment
process a bit easier, but the cost for that service can far
exceed the cost of an international wire transfer.
Dont let retooling costs get in the way of moving forward with the qualification process for either
you or the prospective overseas manufacturer. If you
have done your homework and understand your
annual PCB buy, you might be able to convince the
vendor that your companys potential sales justify
waiving tooling costs, or at least get a contingency
purchase order issued. A contingency PO awards the
production order, as long as the sample board built
is accepted according to the print. Just as you want
to ensure quality, the manufacturer wants follow-up
orders. Both parties are happy this way.
Is it necessary to travel halfway around the world
to see the vendor? Maybe. Socializing with your vendor is an important part of the offshore cultures way
of building a strong relationship. But travel should be
done as business increases. And when you go, look
for other prospective manufacturers as well.
Working directly with an offshore manufacturer
does require upfront work, but the rewards can be
well worth the effort, as it removes a costly link in
your companys supply chain. For every job, PCB
buyers should ask themselves whether going direct to
an overseas vendor would give them the same quality service at significant savings. No risky swimming
with sharks required. PCD&F
NOVEMBER 2016
What to Do If You Cant Have Reference Designators

Are they still needed in the age of machine assembly?
IF YOU CANT have reference designators, what
for the top and one for the bottom. Call this document
should you do?
assembly drawing and include it in the files sent in to
The first answer will probably be along the lines
be manufactured.
FIGURE 1shows agood assembly drawing format.
of, Put them on the board.
It has reference designators and polarity marks.
But, sometimes you cant have reference designaOne might ask why reference designators are
tors on the board. Maybe its too densely populated
needed whenall the surface-mount parts aremachineand there isnt room. Maybe, for aesthetic reasons,
assembled. First, any through-hole parts are handyou chose to leave them off. With some products,
assembled. Their locations and board side need to be
like development boards, its sometimes necessary to
clear for the people stuffing them.
use the space for instruction or functional identificaSecond, CAD systems dont
tion, and reference designators would
always have 100% accurate
confuse customers.
information. If the center point
Its always best to put reference
of the footprint is off, surface
designators as close to the part as posmountmachines (ours and anyone
sible, and on the same side as the part,
elses) will center the part where
but if thats not possible, you can still
the file says to put it, which, in this
create an assembly drawing. When
case, would be the wrong spot.
laying out the board, put the referThe reference designators are
ence designators in a different layer
also part of quality control. Its
than the text you want in silkscreen.
another opportunity to remove
Then, create a PDF thathas all the FIGURE 1. The ideal assembly
ambiguity. Ambiguity bad. Certainty
component outlines in their place drawing will show reference
good. PCD&F
with reference designators. Make one designators and polarity marks.
DUANE BENSON
is marketing
manager at
Screaming Circuits
(screamingcircuits.
com); dbenson@
screamingcircuits.com.
The CIRCUITS ASSEMBLY

DIRECTORY OF EMS COMPANIES
Build your EMS database Unrestricted use

2,900+ facilities worldwide Includes contact info, no. of lines,
markets served and more!
Sortable in Excel
circuitsassembly.com/dems
NOVEMBER 2016
19
THERMAL MANAGEMENT
How AC Currents Affect PCB

TEMPERATURES, Part 2
TRACE
Do analog waveforms follow the same relationship as other

signals? by DOUGLAS G. BROOKS, PH.D. AND DR. JOHANNES ADAM1
In a recent article,2 we looked at the relationship between

trace current and temperature for pulses that propagated
through the trace. That type of circuit was relatively easy
to construct because a constant current was either applied
to the trace or it wasnt. That is, it was switched on and
off. In effect, the test currents were digital, switched
currents.
The results were not unexpected:
1. The effective current applied by the switched pulse was
the RMS (root mean square) current, and
2. The temperature was independent of frequency (at least
over the tested range).
But a question still remains: What about analog AC
currents? What about sine or triangular waveforms? This
article looks at the slightly more complicated topic of
analog waveforms to see if the same conclusions apply.
Test circuit. The first problem is how to apply an analog signal of known, repeatable current level through a
trace at a significant enough current to heat the trace.
To accomplish this, the circuit shown in FIGURE 1 was
created. A waveform generator applied one of three signal types to the base of the Darlington transistor. That
FIGURE 1. Test schematic.

20
resulted in a current through the trace controlled by the

current through the collector. That current was supplied
by a 10.0V constant voltage generator through a 1.05
resistor (with a very low temperature coefficient). The
current through the trace is derived as:
Current = (10.0 - voltage at collector)/1.05
The waveform generator settings were extremely flexible. The output voltage could be set from 0.0 to 10.0V.
The frequency could be set from 0.01Hz to over 20MHz.
And the signal DC offset could be set from -10.0 to
+10.0V DC. Three waveforms were employed during this
analysis: sine, triangle (actually sawtooth) and square.
The duty cycle for the square and triangular waveforms
could be set from 0.0 to 99.9%. The duty cycle for the
triangular waveform was set at 99.9% (sawtooth), and the
duty cycles for the square waves were set at 50%, 75%
and 99%. Output levels were set to result in large output
currents, but not large enough to switch the transistor off,
nor to bring it into saturation. Samples of the waveform
generator output waveforms are shown in FIGURE 2. The
generator waveforms exhibited no measurable distortion.
FIGURE 2. Waveform generator outputs.

NOVEMBER 2016
THERMAL MANAGEMENT
RMS signal levels. Next, we need
to consider how to calculate the
rms values of the signals.3 There
are some reference lines drawn on
Figure 2:
A1
Peak voltage
A0
Minimum voltage
Am Average voltage; i.e., Am = (A1-A0)/2)
If we ignore any DC offset, the

rms value of a simple square wave
is simply its peak voltage, shown
as (A1-Am) in Figure 2. But if the
square wave has a duty cycle other
than 50%, it looks more like the
pulse train in Part 1 of this series.2
The rms value of the pulse train
is its peak value multiplied by the
square root of the duty cycle, or
(A1-Ao)*SQRT(duty cycle).
Similarly, if we ignore any
DC offset, the rms voltage of a
simple sine wave is .707*peak,
or .707*(A1-Am) in Figure 2.
And, ignoring any DC offset, the
rms value of a simple triangu- FIGURE 3. Sawtooth voltage waveform vs time at the collector.
lar (or sawtooth) waveform is
0.577*peak, or .577*(A1-A0) in
Figure 2.
If there is a DC offset, the rms values are calculated
as follows:
Let rms = the rms value of the simple waveform.
Let dc = the dc offset (Am for the simple square wave and the sine
wave, Ao for the sawtooth wave and the pulse train.)
Then the rms value of the offset waveform is
rmsoffset = rms 2 + dc 2
HALL B4, STAND 351
Nonlinearities. But there can be a problem in a practical

circuit. The circuit (transistor) is non-linear over the range
of current applied here. For example, FIGURE 3 shows the
resulting sawtooth waveform. The degree of non-linearity
is obvious.
The oscilloscope used in this analysis was a PicoScope
model 2204A digital scope whose output can be saved to
a computer file. The scope also has the ability to calculate
the True RMS voltage (as well as the DC average, and
many other measures) of the waveform under evaluation.
Therefore, we are freed from having to manually calculate
the rms value.
But then, there is another problem. In our circuit,
high voltages at the collector correspond to low currents
through the trace, and low voltages at the collector correspond with high currents through the trace. The rootmean-square calculation tends to bias the results to the
higher values, in this case the opposite of what we want.
Fortunately, the scope can output a data file, which can be
imported into an Excel spreadsheet. The data can be corrected and the rms value calculated by the spreadsheet.4
NOVEMBER 2016
21
THERMAL MANAGEMENT
TABLE 1. Summary Results of Testing
PEAK V
TROUGH V
RMS CURRENT (A)
TRACE TEMP C
Sine
7.5
2.1
5.39
65.5
Sawtooth
7.15
5.68
68.5
Sq. 50%
2.25
5.11
62
Sq. 75%
7.68
2.25
6.12
75
Sq. 99%
7.9
2.25
7.27
97
Results. The trace used in this analysis

was one of the traces on a test board
used in a previous study.5 It was a 100
mil wide, 0.5oz., 6" long trace. The
resulting summary data are shown in
TABLE 1 and graphed in FIGURE 4. These
results were obtained at a frequency of
100Hz.6 The black line in Figure 4 is the
current/temperature relationship for the
trace with DC current applied. These
results are consistent with prior results;
i.e., the effective current for current/
temperature analyses of ac waveforms
is the rms value of the current.
When applying the signals to the
trace, we also varied the frequency
from 0.5Hz to 1,000Hz. The temperatures remained constant with frequency within the measurement accuracy of
the study (as expected). (At frequencies
significantly above 5,000Hz, our test
setup became unstable.)
Douglas G. Brooks and Johannes

Adam, How AC Currents Affect
PCB Trace Temperatures, PCD&F,
September 2016.
3. See https://en.wikipedia.org/wiki/
Root_mean_square.
4. There are approximately 900 data
samples per cycle in our waveforms.
The Excel formula for calculating
rms is = SQRT(SUMSQ(A1:A10)/
COUNTA(A1:A10)), where A1:A10
is the data range of interest.
5. Douglas G. Brooks, Empirical
Results of Fusing Tests, PCD&F,
January 2016.
6. At frequencies above about 10Hz,
the thermal inertia is such that the
temperature does not change much
within the cycle.
2.
Conclusions
We conclude the results of this analysis
are consistent with the prior results:
1. The effective current of an analog
ac waveform is the RMS (root mean
square) current, and
2. The temperature of an analog ac
waveform is independent of frequency
(at least over the tested range). PCD&F
Acknowledgments
The empirical measurements could not
have been done without the help and
support of Prototron Circuits (Redmond, WA, and Tucson, CA).
Notes
1.
Douglas G. Brooks and Johannes

Adam, PCB Trace and Via Temperatures and Currents: The Complete
Analysis, CreateSpace Independent
Publishing Platform, March 2016.
DOUGLAS BROOKS, PH.D., is owner

of UltraCAD Design, a PCB design
service bureau and author of PCB
Currents: How They Flow, How
They React; doug@ultracad.com.
DR. JOHANNES ADAM, PH.D., CID,
is founder of ADAM Research, a
technical consultant for electronics
companies, a software developer,
and the author of the Thermal Risk
Management simulation program.
FIGURE 4. Graph of summary results.

22
NOVEMBER 2016
PCB MATERIALS
Nano Anchoring Copper Foil for NextGeneration PRINTED WIRING BOARDS

A newly developed treatment technology for copper foil enables ultra-low
profile surfaces. BY OSAMU SUZUKI, AKITO YOSHII, HIRONOBU TSUBURA, MAKIKO
SATO, NAOKI OBATA AND YOSHINOBU KOKAJI
24
Subtractive and semi-additive processes are widely used for

circuit pattern formation in high-volume PWB manufacturing. In a subtractive process, copper is removed from an
entirely copper-laminated board to expose the wiring pattern.
Dry-film resist is applied as an etching resist. The dry film is
exposed, and then developed, which removes the unexposed
parts. When resist is stripped, copper traces appear. The
advantage of the subtractive process is its (low) cost and
excellent mass producibility.
In semi-additive processing, the wiring pattern is

electroplated onto a copper layer. A dry-film resist is
applied as a plating resist. Unlike a subtractive process,
the negative/positive part of the resist is reversed. Additional copper is plated on the unmasked areas. Then the
dry-film resist is stripped away, and a brief etching step
removes the exposed thin copper layer from the board. The
advantage of the semi-additive process is it can provide
finer lines than subtractive processes. To improve plating
FIGURE 1. Manufacturing process comparison of subtractive

and semi-additive processes.
FIGURE 3. SEM images for profile comparison.
FIGURE 2. SEM images for surface comparison.
FIGURE 4. SEM images for morphology of nanoscale noduled

copper foil.
NOVEMBER 2016
PCB MATERIALS
adhesion, a desmear treatment is
used by modifying the resin surface
roughness. It seems there is difficulty
removing contamination from electroless plating on the desmear surface. FIGURE 1 illustrates the process
comparison of subtractive and semiadditive processes.
FIGURE 5. SPM images for morphology comparison.
FIGURE 6. 3D images for trace after etching.
TABLE 1. Etch Factor

CONVENTIONAL CU FOIL
NANO-SCALE PROFILE CU FOIL
Top
18.3m
17.8m
Bottom
26.7m
20.9m
EF
2.8
5.9
FIGURE 7. SEM images for the comparison of fine line formation.

NOVEMBER 2016
Conventional copper foil. Two types

of copper foils are used in PCBs1:
ED (electrodeposited) and RA (rolled
annealed). The most common foil
used in PCBs is ED. ED foil is produced through an electrochemical process. As ED foil is formed, the rotation
speed determines the resulting foil
thickness. Typically, copper is plated on a cylindrical drum. Then, the
smooth surface (shiny side) is achieved
from drum side. Better coplanarity
and less wave undulation is achieved
on the drum side. Topological modification is widely used by plating copper to increase the surface area. Nodules are formed on the outer surface
of the copper foil. When nodules are
formed on the drum side of the copper foil (called reverse-treated foil),
it is easier to maintain the profile of
copper. The advantage of nodule formation is improved adhesion, thanks
to a strong anchoring effect. This is
needed to meet reliability requirements. The rough surface is called
the matte side. FIGURE 2 compares
surfaces of shiny and matte sides.
Various sizes of nodules are available
for various applications; FIGURE 3
demonstrates this by means of top and
cross-sectional views. Then additional
plating is applied over the nodules for
thermal barriers using zinc, nickel, etc.
Anti-rust agents or adhesion promoters are also applied to the surface of
nodules. These improve the copper
foils adhesion and tarnish properties.
These coatings can prevent reductions in adhesiveness after thermal
or chemical degradation through the
PCB assembly process as well.
Nanoscale profile copper foil. The
profile size of copper foil has become
a more important consideration for
PCBs. The smaller profile size is a
key factor in next-generation PCBs.
In terms of fine pattern formation,
copper foil surface roughness is a key
factor for improving etching behavior.
25
PCB MATERIALS
From an electrical point of view, a flat
surface is desired for high-speed applications with high-frequency signals.
A nanoscale profile copper foil has
been developed, which shows wellbalanced etching capability and adhesion. An acid cleaning process removes
the oxidized copper layer prior treatment (FIGURE 4, left). Nanoscale nodules are formed on the copper surface
by chemical reaction using a proprietary treatment solution (Figure 4,
right). Then the surface of copper
foil is covered with a uniform and
dense layer. The nanoscale nodules
have a large contact area that offers
secure bonding to prepreg by means of
the anchoring effect. Scanning probe
microscope (SPM) images are shown
in FIGURE 5. For the conventional
very-low profile copper foil, the SPM
images are similar to SEM images.
However, SPM shows a quite different
image of nanoscale profile copper foil.
It seems probes have difficulty tracing
the sharp nano surface.
Fine line capability. The nodule of
copper foil is embedded in the prepreg
as it is subjected to hot press lamination. In the case of a subtractive process using conventional copper foil, it
has to be etched completely because
the large-size nodules get stuck in the
prepreg. This may cause over-etching
of the wiring pattern. FIGURE 6 shows
3D images from a confocal microscope
of 9m thick copper foil and nanoscale
foil. The nanoscale profile copper has
twice the etch factor (TABLE 1). The
surfaces of prepreg and the anchored
part of copper are completely different
in appearance. SEM images comparing
etching characteristics of a copper foil
profile are shown in FIGURE 7.
Adhesion behavior. Peel strength is
performed with 30m thick specimens
by performing additional copper plating. The prepreg of FR-4 was laminated with copper foil. Results are shown
in FIGURE 8. There is no significant
difference between the 9m and 18m
thick copper foil with nanoscale profile copper. The adhesion strength is
acceptable on both copper foils. The
nanoscale profile copper foil demonstrated 20 to 30% lower peel strength
than the conventional copper foil.
The samples showed different fracture
26
FIGURE 8. Result of peel strength.
FIGURE 9. Fracture location after peel test.
FIGURE 10. Fracture surface after peel test of nanoscale

profile copper foil.
NOVEMBER 2016
PCB MATERIALS
behavior, even though they shared the same adhesion failure.
The fracture location of nanoscale profile copper is close to
the copper surface (FIGURE 9). The surface of nanoscale copper foil is covered with resin of prepreg (FIGURE 10).
Finite element simulations. To address this behavior of
nanoscale copper foil, FEM (finite element modeling) was
used for stress analysis. The maximum principal stress was
conducted. Typically copper foil is laminated with prepreg or
buildup material at high temperature. The maximum principal stress is conducted by calculation of the accumulated
principal stress at -55C using Ansys 16.1 software. Prepreg
and copper foil are contained in the model. The material supplier describes typical properties of the prepreg. It is
FIGURE 11. The image-processing algorithm.
overall property of prepreg, but it is not
localized property. Segmented, accurate
parameters are required for prepreg. Prepreg material is a mixture of glass fabric,
resin and filler. The glass fabric layer and
resin/filler layer are separated. Filler is
distributed in the resin.
Filler volume information was
extracted from a cross-sectioned SEM
image. The image-processing algorithm is outlined in FIGURE 11. The
SEM image was split into 500nm thick
images for resin filler layer of prepreg.
Binary images were generated, which
highlighted the filler parts (in green)
within the selected region. The filler
defines the shape of the target. FIGURE
12 shows the binary image obtained
from the contrast-enhanced image. The
volume of filler is calculated on each
tomographic image. CTE (coefficient
of thermal expansion) and modulus are
conducted by a curve-fitting technique
based on filler volume information.
Then, segmented model parameters for
prepreg are conducted. The parameters
of FR-4 type prepreg are shown in FIG- FIGURE 12. Binary image processing for filler distribution in prepreg.
URE 13. A localized realistic model of
copper foil is implemented in this study
for FEM, which can recognize the nanostructure with representative prepreg.
Localized realistic model for
nanoscale profile copper. The simulation model used a 1 to 4m size
nodule with a simplified conventional
profile (FIGURE 14). Given the adhesion
results, higher maximum principal stress
is expected on nanoscale copper foil.
Simulation results are shown in FIGURE
15. Simplified nanoscale profile is flat
model, resulting in low stress distribution, as indicated. The maximum principal stress of conventional foil is greater
than that of the nanoscale profile copper.
These results contradict the adhesion test
NOVEMBER 2016
FIGURE 13. Segmentalized property of prepreg for FR-4 type prepreg.

27
PCB MATERIALS
FIGURE 14. Simplified model.
results. Macro size simulation model

does not match nanoscale profile.
The localized realistic model is proposed in FIGURE 16. The result of the
maximum principal stress on FR-4 is
shown in FIGURE 17. Higher stress level
is conducted on nanoscale profile copper. This seems reasonable for adhesion
test. The result on BT and buildup
film is shown in FIGURE 18. Almost
the same level of maximum principal
stress is achieved on BT on both foils,
which is quite low, because BT has
unique characteristics such as low CTE
and high Tg. FIGURE 19 shows the
results of the comparison of segmentalized parameter and typical parameter.
Results were different based on the
prepreg. In the case of buildup film, no
glass fabric was incorporated, resulting in similar parameters used. The
segmentalized parameter is closer to
the real situation. As such, the results
should be more accurate.
Conclusion
FIGURE 15. Maximum principal stress of simplified model.
A newly developed nanoscale profile

copper foil is introduced as ultra-low
profile copper foil for PCBs fabricated using subtractive processes. Fineline capability is demonstrated, and
it seems 20-25m traces are possible
using a subtractive process. This would
contribute to a reduction in cost. Good
adhesion is confirmed even though
the surface is flat. Adhesion behavior
was investigated through simulation.
A localized realistic model and segmentalized parameter of prepreg are
important to calculate the accumulated
principal stress at the nanoscale level.
The use of nanoscale profile copper
foil is highly recommended for fine-line
PCBs using a subtractive process. PCD&F
Acknowledgments
The authors would like to thank
KTT Inc. for kind advice and further
evaluation.
REFERENCES
FIGURE 16. Localized realistic model.

28
1. JEITA, Japan Jisso Technology Roadmap,

2015 Edition.
2. J.U. Knickerbocker, et al, 2.5D and 3D
Technology Challenges and Test Vehicle
Demonstrations, Proceedings of the 62nd
Electronic Components and Technology
Conference (ECTC), May 2012.
3. J.H. Lau, TSV Manufacturing Yield and Hidden Costs for 3D IC Integration, Proceedings of the 60th Electronic Components and
NOVEMBER 2016
PCB MATERIALS
FIGURE 17. Maximum principal stress (FR-4) of localized realistic model.
Technology Conference (ECTC), May 2010.

4. K.W. Lee, et al, A Resilient 3-D Stacked Multicore Processor Fabricated Using Die-Level
3-D Integration and Backside TSV Technologies, Proceedings of the 64th Electronic
Components and Technology Conference
(ECTC), May 2014.
5. Y.H. Hu, et al, Process Development to
Enable 3D IC Multi-Tier Die Bond for 20m
Pitch and Beyond, Proceedings of the 64th
Electronic Components and Technology
Conference (ECTC), May 2014.
6. T. Kanki, et al, Development of highly reliable Cu wiring of L/S=1/1m for chip to chip
interconnection, Proceedings of the 2012
IEEE International Interconnect Technology
Conference (IITC), 2012.
7. K. Oi, et al, Development of New 2.5D Package with Novel Integrated Organic Interposer Substrate with Ultra-fine Wiring and
High Density Bumps, Proceedings of the
64th Electronic Components and Technology Conference (ECTC), May 2014.
8. H. Noma, et al, HAST failure investigation
on ultra-high density lines for 2.1D packages, Proceedings of the International Conference on Electronics Packaging and IMAPS
All Asia Conference (ICEP-IAAC), 2015.
Ed.: This article was first published at the
SMTA Pan Pacific Microelectronics Symposium (Pan Pacific), January 2016, and is
republished with permission of the authors.
FIGURE 18. Comparison of maximum principal stress.
OSAMU SUZUKI, AKITO YOSHII,

HIRONOBU TSUBURA, MAKIKO SATO,
NAOKI OBATA and YOSHINOBU KOKAJI
are with Namics Corp. (namics.co.jp);
os@namics.co.jp.
FIGURE 19. Comparison of parameter of prepreg.

NOVEMBER 2016
29
EMS
JABIL Steps Up
A small New England city is now home to a new ODM plant,
but its not the typical electronics kind. by MIKE BUETOW
Move over Nike: Jabil is jumping into shoe manufacturing,

In a phone interview, Loparco told Circuits Assembly the
and in a big way.
reality around 3D printing has at long last caught up to the
The EMS/ODM, which has been expanding its focus in
hype. 3D printing is now about 1/50th of the cost of conventional methods, he said. It improves cycle time; speeds; tolerrecent years to include everything from plastics to supply-chain
ances become more achievable. Its a very real and viable tool.
software, is now leveraging that additional expertise to join
3D printing, Jabil says, has reached the point where costs
one of the most consumer-oriented industries imaginable.
have declined sufficiently to drive adoption, and Jabil plans
Jabil sees the $55 billion sensory footwear market as ripe
to become an absolute leader in the market, noted Sherri
for transformation. The emergence of 3D printing, coupled
Scribner, an analyst at Deutsche Bank. Indeed, the company
with significant investments in supply-chain tools, is enabling
expects its revenue from 3D printing to grow 45% comthe contract manufacturer to compete in areas many steps
pounded annually through 2019.
ahead of traditional SMT assembly.
New investments and capabilities are enhancing supplyTheres little doubt that for upper-tier EMS compachain management so critical to ensuring the fast time-tonies, the markets they serve have transformed significantly
market demanded in the consumer world. Jabils proprietary
of late. But for Jabil to compete in footwear turned on a
suite of software called InControl looks at a supply chain
strategy put in place more than a decade ago. Engineers
from end-to-end, evaluates risks and manages them in a realneeded to gain expertise in materials science. Cutting-edge
time manner.
manufacturing methods and supply-chain tools had to
Loparco says sophisticated tools like InControl are necbe readied for prime time. And automation had to reach
essary to match up with the sophistication of science that
the point where it could displace low-cost, high-volume
makes up todays footwear. Its really transformational, he
manufacturing regions.
says. Moreover, Jabil has honed its capabilities in robotics
The maturity of additive manufacturing is one enabler.
and automation for the volumes necessary to contend with
Jabil has been investing in 3D printing for more than 10
high-volume, low-cost geographies.
years. It has emerged as a core manufacturing process for
fixtures and jigs. In May, Jabil was selected
by HP to bring its Jet Fusion 3D printer to
market. The tool will accelerate the move
to mass customization while also supporting lower-volume production.
Those are critical components of the
footwear business, explains Mike Loparco,
CEO of Jabils Engineered Solutions Group.
Jabil would like to introduce new forms of
manufacturing, new forms of optimizing the
supply chain, and new forms of getting products in the hands of consumers.
Millennials want everything customized, with the features they want, when they
want. Automation enables otherwise costprohibitive geographies and brings [manufacturing] close to the point of consumption.
RUNNING GEAR. Are shoes like these in ODMs future? (Source: Virgin America)
30
NOVEMBER 2016
The development is the culmination of a strategy put in

motion years ago, as Jabil began acquiring companies in a
variety of industries far afield from electronics. The deals for
GreenPoint (acquired in 2006), Nypro (2013) and Clothing+
(2015) now make clear sense.
GreenPoint knows mechanical design and plastic injectionmolding. Nypromanufactures precision plastics. Clothing+ is a world leader in smart textiles, incorporating
sensor technology, molding and product design.
Theres no question we cross-pollinate investment and
technologies, notes Loparco. Take a step back and look
not just at the automotive markets we serve, but the emerging ones. Weve developed a level of expertise to make these
businesses weve honed and get into a new one.
The Blue Sky innovation center (profiled by Circuits
Assembly in December 2015) is also paying dividends. Jabil
is leveraging the San Jose-based center to demonstrate the
breadth and depth of its expertise to potential customers,
while also using the site to educate its workers.
The convergence has led Jabil to open a manufacturing
plant in Dover, NH, a small city (population 30,000) on the
Piscataqua River, about 65 miles north of Boston and just west
of the Atlantic Ocean. Why Dover? Is Jabil simply seeking to
capitalize on Made in America trends? Theres no question
its exciting for political reasons. Loparco says, but if you
look at some of the tariffs and protected industries, there are
very real economic reasons for making footwear in America.
If you look at the manufacturing regions around the

US, footwear has grown up in two locations: Greater Boston
[home to Converse and New Balance] and Oregon [Nike].
Its where the talent is; its where the marketing expertise is.
The company declined to disclose the customers
lined up for the new site, other than to say it already has
incredible traction.
It doesnt appear Jabil will stop at shoes.
Theres added potential in the high-performance fitness
equipment market, which forecasts say will reach $12 billion
by 2020. Jabils acquisition of Clothing+ gave it a foothold in
that space, which is attractive not just because the products
align with Jabils core capabilities, but the prices customers
are willing to pay.
Jabil wont stop there either, Loparco suggests. Many
other industries are ripe for transformation. InControl
embodies a suite of different platforms that enable procurement as a service. And Jabil can leverage it for customers for
which it doesnt even manufacture a product.
Youd be fighting gravity to ignore it. We have the ability to rapidly do prototypes and ramp them to scale. Think
of how sophisticated electronics is, the complex global supply
chain, and apply that on top of other box-build processes; the
innovation is there. And they are asking. CA
MIKE BUETOW is editor in chief of PCD&F/Circuits Assembly;
mbuetow@upmediagroup.com.
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4/19/16 3:14 PM
31
PROCESS CONTROL
How Stencil Design and Reflow Profiles

Affect Variation in QFN VOIDING DATA:
A CASE STUDY
Is a new standard test needed? by BROOK SANDY-SMITH
Forward. I would like to note as an addition to the original

text a few topics from frequently asked questions. Originally
I had approached this paper as an investigation into several
data sets that showed interesting results. It seems to have
evolved into an analysis of how a variety of factors will
impact voiding results. I see many of these factors echoed in
further industry papers, as QFN packages grow in popularity
and more projects are published. The common key to success is considering all the potential contributing factors, then
controlling most, and optimizing the ones that are mutable.
Often it comes down to solder paste material choice and
limited process parameters as the main optimizing factors.
Reflow profiling: Some of the investigated cases include a
comparison between typical reflow profiles and longer, hotter
profiles. It is important to always consider the full assembly
when profiling. The cases here are idealized because a test
board with only QFN components was used. In the real
world, the process window is limited by several factors: component maximum temperatures, oxidation resistance on large
components, avoiding graping on small components, etc.
When creating an optimal profile for voiding on a real assembly, profiling to minimize voiding must be tempered with
attention for the other challenging parts on the assembly.
Stencil design: The stencil designs presented in this paper
were chosen to illustrate whether increasing solder volume
will decrease voiding. Sometimes, depending on factors like
component size, having one large aperture is not favorable.
When solder becomes molten, the surface tension of the
solder forms a meniscus. When the aperture design is not
separated, this meniscus may be tall enough to permit the
component to tip or float, challenging the integrity of perimeter solder joints. The component used here was relatively
small, so this effect was not seen.
Component cleanliness: A possible explanation was proposed
for the incidence of intermittent high voiding values: Were the
components clean? Through further investigation, there was
certainly variation in the surface finish of the components.
32
The data sets in this paper were collected over a considerable

period of time, so variations in component cleanliness may
have contributed to higher incidence of intermittent high
voiding values in some data sets. Nonetheless, the trends seen
with reflow profile and stencil design stay true.
Standoff height: For geometric calculations, the minimum
recommended standoff height was chosen. This is not the
default, however. Ample standoff height will improve the
ability of volatiles to escape from the solder paste during preheat. Furthermore, decreased standoff height will
degrade solder joint reliability because there will not be
enough solder material to bridge the gap when CTE mismatches and stresses occur. It is critical to maintain the
minimum standoff recommended by the component manufacturer. This can become more challenging when vias are
included in the thermal pad design.
Vias: Vias were not included in this test design. This is a critical difference between these material comparisons and most
real-life assemblies. If a design has vias in the thermal pad,
this drastically changes the approach to stencil design. In the
case of designs with open vias, it is preferred to avoid printing solder paste close enough to permit solder to wick into
the vias. Depending on the number and size of vias, when
solder wicks down them, it can have a significant impact in
the solder volume remaining in the solder joint.1 There are
also cases where the solder interaction with the vias can contribute to voiding, or result in the component being skewed
or tilted, thus affecting perimeter solder joint integrity as
well. The industry has pursued several different approaches
to this design challenge2, and this is an interesting area for
further study.
Introduction
Void reduction in large, confined solder joints has been a
hot topic for more than a decade. The affected component
may be evolving, but the same challenge exists. Many
papers have reviewed process recommendations to lower
voiding,3 looked at material modifications to mitigate the
NOVEMBER 2016
PROCESS CONTROL
studies several cases in which voiding
data were collected using a standardized method. The trends in these
data sets led to further test method
development.
Cases and Procedures
FIGURE 1. Component and pads on

standardized test board.
issue, and even suggested material

additions such as preforms to increase
solder volume without adding volatiles.4 These studies agree on a few
things: If there is poor wetting (no
matter what the cause), there will be
an increase in voiding, and if there is
insufficient solder volume, there will
be an increase in voiding. The second
mechanism contributing to voiding is
entrapment of volatiles.
Instead of discussing different
ways to mitigate voiding, this article
The new product introduction cycle

requires plenty of data collection using
standardized test methods. Many
experimental formulas and benchmarks are tested. Over the course of
many studies, it was evident there were
opportunities to improve the standard
test for QFN voiding.
The standard test uses a commercially available test vehicle, with
12 QFN components on the reflowfocused side. These components are
Amkor MLF68s, 10mm in size, with
0.5mm pitch, and matte tin finish.
The test boards were copper with
OSP finish.
The data presented in this paper
were compiled from several different studies conducted in Indiums
Advanced Materials and Process Development Lab. These studies were not
necessarily focused on QFN voiding,
but the resulting voiding data showed
interesting patterns that led to further

investigation. To make sense of these
sets, a brief background of each of the
studies is referenced here:
Case 1: Material comparison of SAC
305 materials, processed at two different reflow profiles. This testing was
conducted with the original stencil
designed for the test board.
Case 2: Screening test for several
developmental high-reliability alloys
with different fluxes. This testing was
conducted with the original stencil
designed for the board. Data will be
shown with two different profiles.
Case 3: Material comparison with
low-Ag alloy fine powder. Several
combinations were tested using modified stencil designs.
Case 4: Two standard materials, chosen to represent best- and worst-case,
with all three stencil designs.
In all cases, paste was stencil-printed onto the test boards at 100mm/s
with minimal pressure. Components
were automatically placed using placement equipment. The boards were then
reflowed in air in a 10-zone reflow
oven. The profile was a standard ramp
to peak unless otherwise noted.
Stencil Designs
In the component application notes,5
a few stencil designs are suggested, as
shown in FIGURE 2, all with varying
levels of solder coverage on the thermal
pad. The suggested designs break up
the solder deposit on the center pad
into several deposits. The coverage by
area ranges from 37 to 81%.
These recommendations take into
account considerations for thermal
vias in the pad. The test board design
has no vias. This removes a large
FIGURE 2. Suggested aperture designs.1
FIGURE 3. Original stencil design.

NOVEMBER 2016
FIGURE 4. Modified stencil designs.

33
PROCESS CONTROL
complicating factor from this applesto-apples comparison test method.
For designs using vias, some of this
discussion of solder volume will
nonetheless apply.
The original stencil design (FIGURE
3) split the thermal pad area into nine
square deposits with a wide windowpane pattern. The panes between
deposits measured 20 mils thick. Basic
area calculations show the coverage
by area is 75.1%. This is within the
suggested range.
When a geometric calculation is
made for the 5 mil stencil, assuming
solder is approximately 50% solid by
volume, the deposit will be 13.5%
less than the ideal volume. The ideal
volume is based on the pad size and
the component application note, which
recommends a minimum of 50 microns
of standoff for reliability.
A new stencil was designed to
increase the coverage of the solder
paste and vary the volume of solder to
see the impact on voiding results. As
shown in FIGURE 4, the four designs
chosen were a full pad print, nine windowpanes with finer spacing (10 mils),
quadrants with the same finer spacing,
and quadrants with 20 mil panes.
These designs have a range from
0.0 to 12.9% reduction in solder paste
coverage by area. By obtaining both 4
mil- and 5 mil-thick stencils, volumes
will range from insufficient to excessive, as tabulated in TABLE 1.
TABLE 1. Geometric Calculated Values for Coverage by Area and Volume

PATTERN
AREA REDUCTION
ALLOY VOLUME % DIFFERENCE
9 Thin pane 5 mil
12.9%
-19.7%
Quadrants wide pane 4 mil
12.9%
-19.7%
Quadrants fine pane 4 mil
6.6%
-13.9%
Original design
24.9%
-13.5%
Full pad 4 mil
0.0%
-7.8%
9 Thin pane 4 mil
12.9%
0.4%
Quadrants wide pane 5 mil
12.9%
0.4%
Quadrants fine pane 5 mil
6.6%
7.6%
No window pane
0.0%
15.2%
FIGURE 5. Voiding for Case 1 with the original 5 mil stencil design, showing results
at two profiles.
Results
Case 1 demonstrates a typical data set
that was collected using the original 5
mil stencil design. Two profiles were
used to demonstrate the low and high
side of the reflow profile window.
Figure 3 shows voiding results for
four different commercially available
solder pastes. Each condition had three
associated boards. The voiding results
are plotted by component to determine
whether any location had an effect on
the results. Generally, the higher reflow
profile seems to yield lower voiding
percentages and lower variation for
all four pastes. This result is easily
assessed visually; however, it is also
clear there seem to be intermittent high
voiding results.
Viewing all the results by profile as
distributions (FIGURE 6), there is one
group of voiding results that is distinctly
34
FIGURE 6. Distributions with Benchmark paste A highlighted.

NOVEMBER 2016
PROCESS CONTROL
higher than the general distribution.
Highlighting only benchmark paste A in
darker green, the distribution and averages are low, but a couple outliers have
voiding >35%. Case 2 is a comparison
of several different solder pastes with
different flux and alloy combinations.
The results in FIGURE 7 are presented by
alloy and flux, plotted by component.
In this case, two boards were reflowed
per paste with a typical ramp to peak
profile. Benchmark paste E with alloy 1
shows acceptable results as far as voiding percent, as well as low variation.
The experimental formulations do not
approach this result. Some pastes show
intermittent low voiding components,
which led to investigation of the individual x-ray images.
FIGURE 8 shows a selection of comFIGURE 7. Voiding for case 2 using typical reflow profile and original 5 mil
stencil design.
ponent images. The minimum voided
component shows different characteristic voiding, depending on the solder paste. The maximum
voided component has drastically larger voids. Benchmark
paste Bs largest voids do not seem to follow any pattern.
FIGURE 8. X-ray voiding images from case 2.

NOVEMBER 2016
FIGURE 9. Case 3 summarized voiding results by stencil only.

35
PROCESS CONTROL
Many images of experimental pastes
were shown to have a similar frowny
face pattern. This resembles voids congregating along the pathways created by
the nine windowpane pattern. Benchmark C shows large voids, which almost
seem to correspond to the deposits created by the nine windowpane pattern.
Looking back at the maximum voided components in many data sets, the
same pattern emerged.
There may be many sources for this
variation. Was this trend in the pattern
of voiding with this design real? One
possible source of this inconsistency was
variation in placement height. The placement machine used in this test places
components at some height above an
ideal zero. Since the board thickness and
flatness varies, the amount the component is pressed into the paste could also
be a variable. Could the variation be
another characteristic of the solder paste
formulation? Experimental solder pastes
typically showed many small voids and
the frowny face pattern. These considerations always return to the question
of how the solder paste outgassing is FIGURE 10. Case 3 voiding results plotted by aperture design.
affected by the choice of stencil aperture
design. This led to development of stencils with new designs, as discussed in the previous section.
With an increase in the solder volume, could these intermittent high voiding levels be mitigated? Would a different
pattern with the same amount of coverage yield different
results? Overall, the goal was to reduce voiding percentages,
mitigate largest voids, and reduce variation in the voiding
test results.
Case 3 was conducted on several different fluxes tested
with a low-silver alloy. All boards were reflowed using the
standard ramp to peak profile. FIGURE 9 shows the variabilFIGURE 11. X-ray images of maximum voided components in
ity of the voiding results with the new stencil designs at both
case 3.
thicknesses. Overall, the standard deviation has fallen below
10% for all of the results. There are still a few intermittent
high voiding results. When the data are plotted, separating
boards was analyzed, but the number of components was not
the results by design (FIGURE 10), the intermittent high voiding results do not correlate with a particular stencil or design.
normalized. It may be possible to yield more definitive results
The associated x-ray images (FIGURE 11) do not seem to have
with more replicates.
a common pattern.
Conclusion
Case 4 simply compares the stencil designs, all other facThe first case studied was one directed to show the impact
tors being equal. This trial was carried out with two SAC 305
of reflow profiling on voiding results. The data presented
commercially available pastes: one with typically low voiding
strongly support lower voiding with a longer, hotter profile.
and low variation, and one with typically higher voiding. The
One additional set of results from Case 2, found in FIGURE
results that were plotted based on stencil and aperture design
13, shows where the profile is varied, but there is little cor(FIGURE 12) show relatively consistent results for benchmark
paste A. For the other paste, the new 5 mil stencil showed
relation between profile and voiding results. The main difhigher variation than either the original stencil or the new
ference is Case 2 shows pastes with different alloys, as well
4 mil stencil. The average voiding with new stencil designs
as different profiles. Each paste combination may have a
was marginally lower. The comparison of variation is slightly
different trend.
skewed because there are more components with the same
Generally, the profile influence will have a few general
pattern for the original stencil because the same number of
trends resulting in higher voiding:
36
NOVEMBER 2016
PROCESS CONTROL
Low peak temperature tends to require more time for complete solder wetting.
Excessive peak temperature or profile length results in
oxidation on surfaces, increasing the potential for voiding.
To reduce the sources of variation in voiding comparison
data, two new stencils with four different aperture designs
were tested. Generally, these stencils yielded results with less
variation than was experienced with the original stencil. The
intermittent high voiding results were also less frequent with
the new designs; however, some pastes still showed more
variation than others.
Designs with higher volumes did not show signs of
defects from the excess. (Solder balling or poor fillet formation were the downsides stated in the component application note.5) Designs with less volume (4 mil stencil) did not
intrinsically show more voiding or variation. This implies
there is not a direct correlation to voiding percent and solder volume. This is especially evident looking at the results
for Benchmark paste A in Figure 10, where all stencils and
designs show very similar results. This seems to indicate that
for some pastes that have a chemistry designed to reduce
QFN voiding, the results will also be good for a wide range
of designs and conditions. CA
Acknowledgments
FIGURE 12. Results from case 4, comparing stencils and
aperture designs.
Thanks to Mark Reece and Sarah Bjornland for their assistance collecting much of these data. Thanks to Dr. Arnab
Dasgupta for providing many of the experimental formulas.
Ed.: This article was first published at the SMTA International Conference on Soldering and Reliability in June 2016, and is republished
with permission of the author.
REFERENCES
1. Brook Sandy-Smith, Reliability Challenges for Bottom Termination
Components, SMTA International Conference on Soldering and Reliability, May 2013.
2. Matthew Kelly, et al, Via-in-pad Plated Over (VIPPO) Design Considerations for Enterprise Server and Storage Hardware, SMTAI
Proceedings, October 2015.
3. Brook Sandy-Smith and Seth Homer, Optimizing Assembly of QFNs,
SMTAI Proceedings, October 2013.
4. BrandonJuddand MariaDurham, The Benefits of Flux-Coated
Solder Preforms in a QFN Assembly Process, IMAPS, October 2015.
5. Application Notes for Surface Mount Assembly of Amkors MicroLeadFrame Packages, Rev G, September 2008.
BROOK SANDY-SMITH is PCB assembly materials specialist at

Indium (indium.com); bsandy@indium.com.
FIGURE 13. Results from case 2, comparing different profiles.
If the preheat is too quick, there is not enough time for

volatiles to evolve and escape before the solder is molten.
If the preheat is too quick, the paste can slump, reducing
the standoff and preventing the escape of volatiles.
If the profile is generally too short, volatiles will be more
easily entrapped.
NOVEMBER 2016
37
TECH TIPS
Void Reduction on QFNs

Sometimes the answers to the most tenacious questions are right under your nose.
AS I SIT in Chicagos OHare Airport having just left
TIM ONEILLis
technical marketing
manager at AIM
Solder (aimsolder.
com);toneill@aimsolder.com.
38
another productive and exciting SMTA International

trade show, I reflect on what an excellent opportunity
this event presents to network and stay current in the
world of electronics assembly. If you dont attend
these events regularly, you should. I was fortunate
to have the opportunity to attend a number of the
technical conference sessions and not only learn what
is emerging, but also speak with customers and colleagues on what they see as the most pressing needs
of the market.
To sum it up BTC void reduction. The technical sessions on void reduction I attended were all
standing room only, and the topic was the subject of
many hallway conversations among technologists.
The presentations offered supplier and user perspectives on materials and techniques that have been
tested both in the lab and the field with varying
degrees of success in reducing voids. A few themes
were repeated: Solder paste formulation is the biggest
single variable that aided in void reduction; profiling techniques can definitely help mitigate voids,
and pad/via/stencil design is extremely important.
The bottom line remains the same, however: It will
always be difficult to evacuate 50% of the volume of
the printed deposit in the form of gaseous flux during
a typical reflow cycle with limited outgassing paths.
Those who have been following our recent series
of articles know that we have been actively performing
print studies to ensure we have the processes and materials to meet the requirements of the ever-shrinking
solder features on PCB assemblies. During these tests,
my esteemed colleagues in our Juarez, Mexico, applications lab noticed something unusual while studying
the I/O pads on QFN. If they didnt print the I/O pads,
they saw a dramatic reduction in voids on the ground
pads. And by dramatic, we mean dramatic. There were
no measurable voids on a component that otherwise
exhibited voids in the 10 to 15% range. This piqued
their interest, as all the ground pads on the test board
were printed with the typical window pane pattern
at about 70% coverage.
Following their instincts, the engineers decided
to pursue manipulating the print volume on the I/O
pads to determine whether there was a design that
would promote void reduction. Up until now, much
of the industry testing has focused on manipulating
the ground pad paste deposit, not the I/O deposit.
Window panes, star bursts, hourglass, diamonds, herringbones, and every other aperture shape imaginable
have been tried on ground pads, all with the same
objectives of providing outgassing pathways for flux
volatiles and manipulating the volume of solder. Our
experience has been that these ground pad aperture
FIGURE 1. Void reduction on BTC ground pads as a

result of changing I/O aperture design while maintaining the same ground pad aperture design on the
original experiment.
FIGURE 2. Repeated results in reduced voiding resulting from I/O aperture design in larger DoE with more
input variables.
designs have some impact on void mitigation, but

not the ultimate answer. These preliminary results,
however, were the first time we have seen the volume
of solder paste on the I/O pads impact void formation on the ground pad. FIGURE 1 shows the degree
of impact the I/O aperture design had on ground pad
voiding in the initial tests.
These results were unexpected and profoundly
positive. However, the sample size was small and was
only on one package size. The skeptics in AIMs technical department needed more data to be convinced
there was something to it. What ensued was a fullfledged design of experiments (DoE) that employed a
variety of QFN sizes and I/O pad designs to attempt
to repeat the outcomes.
FIGURE 2 shows the results of I/O aperture manipulation on QFN grounding for a variety of process
conditions. These results clearly indicated a correlation
between I/O pad design and a significant reduction
in ground pad voids. We are currently engaged in an
even deeper study by manipulating more variables and
introducing the I/O design to a production environment to determine how repeatable and robust this
technique can be. Every strategy that can be deployed
to reduce voiding especially those that do not require
significant capital investment represents an important opportunity to improve product quality.
continued on pg. 41
NOVEMBER 2016
CELEBRATING 60 YEARS
OF BEING THE TURNING POINT
FOR THE ELECTRONICS INDUSTRY
GETTING LEAN
LED Assembly and Lean Manufacturing

The sensitive nature of LEDs underscores the need for minimizing waste.
MANUFACTURERS OF PRINTED circuit board assem-
YOUSEF
HEIDARI is
vice president of
engineering, West
Coast operations
at SigmaTron;
yousef.heidari@
sigmatronintl.com.
DENNIS
MCNAMARA
is vice president
of engineering,
Mexico operations
at SigmaTron
International
(sigmatronintl.com);
dennis.mcnamara@
sigmatronintl.com.
40
blies, in general, have been experiencing relatively

high first-pass yield infant mortality rates due to the
nature of smaller LED component design and manufacturing itself. These are very delicate, wire-bonded
parts. Common component failures include silver-filled
epoxy die attach de-bonding issues, wire-bond lifting
due to encapsulation around the LED die or the wire
bonding process itself, and broken wires due to PCB
flexing or solder wicking stress on the wire bonds.
Not surprisingly, addressing challenges represented by smaller LED components aligns closely with
the focus on eliminating several of the seven wastes
identified by Taiichi Ohno, the key founder of the
Toyota Production System (TPS). These inefficiencies
or wastes are:
Overproduction
Waiting
Transportation
Inappropriate processing
Excessive inventory
Unnecessary motion
Defects.
While focus on all seven of these wastes is a hallmark of a well-run production operation utilizing Lean
manufacturing principles, three wastes in particular
relate strongly to LED manufacturing: defects, inappropriate processing, and transportation. This column
looks at the steps being taken in each of these areas.
Eliminating the waste of defects. The challenge
in LED assembly is the sheer number of defect
opportunities that exists due to the delicacy of small
parts. The discipline of eliminating the potential for
defects to occur is critical and requires a combination of close collaboration with the LED component
supply chain; strong focus on design for manufacturability (DfM) and design for assembly (DfA);
and tight process controls and specialized handling
during manufacturing.
Selecting LED component suppliers capable of
providing consistent quality parts is a key first step.
Additionally, hue selection is very important. LEDs
are bought by the bin. While providers are good at
keeping hue consistency within a specific bin, the correct bin for the desired hue must be specified.
The delicacy and nature of LED manufacturing
drives more stringent process control in PCBA manufacturing. Adhering to each LED manufacturers
component data sheet guidelines is critical. As an
example, some 0603 LEDs start out as a thin specialized printed circuit board panel containing thousands
of LEDs.This large PCB panel is drilled at two
locations at each individual LED site.These holes
are plated through and will facilitate the electrical

connections between the bottom mounting side and
the topside, where the wire bonds or silver die attach
epoxy connections are placed. When the LED panel
fabrication is completed, the panel is sawed along the
hole axis. This leaves a portion of each hole present
at each end of each LED or a castellated connection.Soldering must be tightly controlled; otherwise
hot liquid solder will flow upward into the partial
hole or castellated termination and come in contact
with the LED lens and attempt to dislodge it.
From a DfM standpoint, stencil design is very
important for ensuring the correct amount of solder is
deposited. In SigmaTrons process, the apertures in the
solder stencil use a trapezoid shape because controlling
the amount of solder paste, aperture and shape of the
print is critical for keeping the solder from wicking up
and coming in contact with the clear lens. Otherwise,
the excess solder can peel off the lens, or put too much
strain on the wire bonds holding the lens.
This contractors Acuna, Mexico, facility still occasionally runs through-hole LEDs in low volume for
legacy products. DfM and adherence to IPC design
guidelines is important with these PCBAs, as the hole
sizes for leads and spacing between holes is critical. If
spacing between holes is too far or too close, it will
place stress on the leads and weaken the part. Throughhole LEDs should also be inserted with a standoff.
There are also DfA considerations in field failure
mitigation where 0603 LEDs are involved. If a plastic
light guide or light-focusing device is placed too near
the 0603 lens, shock and vibration in normal use can
cause the device to touch the lens and break.
ESD damage is also a concern, and defect mitigation requires a higher level of ESD protection.
Ultraviolet (UV) or blue LEDs are considered the
most ESD-sensitive, but in reality white LEDs are
also blue LEDs. A phosphor coating is used to color
the lens yellow so that human eyes interpret the
light as white. So basically, all LEDs are extremely
ESD-sensitive.
In this contractors process, ionizers are used in
all areas where LED PCBAs are handled, in addition
to the factorys standard ESD protective flooring and
employee protective clothing.
Eliminating the waste of inappropriate processing. The delicacy of wire-bonded 0603 LEDs also
creates challenges in reflow, particularly on Pb-free
products. The process window is very narrow. When
possible, SnPb solder is preferred because peak soldering temperatures run 217-220C. Conversely, the
peak soldering temperature is 242C with Pb-free
solder. The temperature profile needs to be as gentle as
NOVEMBER 2016
TECH TIPS
possible to minimize the impact of peak
temperatures on the wire-bonded die. If
the profile is not hot enough and long
enough in duration, the flux does not
properly activate and then deactivate.
If peak temperatures are held too long
and higher temperature profiles are used
for Pb-free solder, yields go down due to
silver die attach failures. The die attach
failure is normally caused by some type
of force acting on the lens or due to an
LED vendor wire bonding issue.
Mitigating the waste of inappropriate processing also plays a factor
in test strategy. In this case, the issue
is most related to cost of test. Simpler
equipment achieves the desired result
at lower cost.
LED PCBAs are typically tested
using in-circuit test (ICT). However,
standard ICT will not test for brightness. At this contractor, testing is done
using cameras and software that analyzes pixel values. The alternative test
option measures LED hue using a
spectrophotometer with an integrating
sphere, which requires precise distance
between the LED and test equipment.
From a cost and test time perspective,
the latter method was deemed too costly
when the two methods were analyzed in
terms of cost and accuracy. In the camera method for white LEDs, the ratio of
blue pixel intensity to red pixel intensity
is measured to verify the correct hue.
on this most recent SMTAI conference,

I realize much of the information that
both users and suppliers seek is right
under our noses. These industry events,
whether local, regional or international,
enable us to witness the latest advancements and see the opportunities to
improve quality, productivity and efficiency, all under one roof. I cant wait for
the next one. See you there! CA
Tech Tips, continued from pg. 38

This development not only has exciting potential, it also highlights the importance of attending industry events. We
are looking forward to providing Circuits
Assembly readers with the big-picture overview and sharing all the critical details
of this testing within our SMT community at upcoming events. Reflecting
Circuits Assembly 2016 (4.5x7.5).pdf
11/24/15
11:00 AM
Eliminating the waste of excess

transportation. Handling following
reflow is also critical. If the PCBAs are
moved when hot, the LED will separate from the substrate. This contractor addresses this with a chiller in the
reflow oven followed by a fan tray as
the PCBAs exit the oven so boards are
room temperature when handled. Even
at room temperature, handling can be
an issue. A shock or bump will break
the lens of a 0603 LED. Consequently,
the production process is designed to
minimize the need for production operators to handle PCBAs.
With careful planning LED manufacturing can generate high yields.
However, the margin for error in process or handling is much smaller for
packages such as the 0603 SMT device.
As noted, many of the foundation disciplines utilized in Lean manufacturing
can pay big dividends in improving
LED assembly production processes. CA
NOVEMBER 2016
41
TEST AND INSPECTION
New Girls Replace Old Guys

Next-gen test engineers are an investment for all of us.
TWO YEARS AGO I wondered in this space where we
would unearth the test engineers of the future (Who

Replaces the Old Guys, Circuits Assembly, September
2014). I promised to report back what we found,
once we found it. I was, I thought, realistic about our
prospects. We were competing, as humble manufacturers, for future engineering talent against the magnetic allure of app designing. We were shunned by the
prestigious universities. We contacted the commuter
schools, hoping for a warmer reception. Reception
was decidedly lukewarm. It is perhaps stating the
obvious to note our company is not for everyone. In
the Miss Universe of corporate beauty pageants, the
most we can hope for is to secure Miss Congeniality.
Nevertheless, and in spite of the process taking far
longer than we anticipated, we have seen the future, and
it comes for us, this year, in the form of several risktaking individuals at a boundary-breaking university
(The University of California, Davis), who offered us its
best: a 21-year-old, smart-as-a-whip, Hispanic female.
Who were you expecting?
Maybe shell join us.
If we dont scare her away first. Shed be partnered
with old guys, after all. Who just get older. And crankier. You see evidence of that in their magazine columns.
All the more reason to strike a firm blow on
behalf of diversity.
Basic qualifications:
ROBERT
BOGUSKI is
president of Datest
Corp., (datest.com);
rboguski@datest.
com. His column

runs bimonthly.
42
Bachelors of science (or equivalent work experience) in electrical engineering, computer engineering, computer science, mechanical engineering, or
materials science.
Attention to detail; daring; self-confident; selfmotivated. How self-confident? Willingness to
call the Boss out when he says something stupid.
Fearlessness a definite differentiator.
Exceptional written and verbal communication
skills. And when we say exceptional, we aint
blowin smoke!
Possessed of an innate aversion to Groupthink.
Intellectual curiosity and a willingness to learn,
especially concerning why systems work, and even
more especially, why they dont.
Not shy or afraid to ask questions, the most important being, why?
Not being afraid to fail and make mistakes,
learning from those mistakes, applying what was
learned, and (hopefully) not making the same
mistake twice.
Knows how, or at least is willing to learn how, to
read, interpret, and potentially create a test design
from a customers statement of work, while being
cognizant of the probability the customer has at best
a partial grasp of the cost and performance of what

they are specifying. All while smiling. Ability to turn
lab manuals into bodice-ripping fiction a definite plus.
Willingness to read (gasp!) and comprehend
(whaaaat!?!) complex technical specifications.
High skills in electrical schematic interpretation.
Ability to diagram, on a white board, in two languages, the Infield Fly Rule.
Basic programming skills in some of the more common languages used in our trade, such as LabView,
C, and C++.
Strong debugging and/or troubleshooting skills.
Digital and analog electrical design experience.
Exceptional nonsense (BS) recognition skills.
Just like every other red-blooded American boy
and girl.
Intimidating requirements, to be sure. Doubtful
we can find someone who meets all of them. About as
likely as Bob Dylan winning the Nobel Prize.
Oops.
But first comes the interview.
Questions to ask in an interview to a

potential engineering employee:
What motivates you?

Do you understand what a test engineer does?
What is it about your major that excites you the
most? Why study to be an EE, CE or CS?
How are you at explaining things in non-technical
terms to others who do not understand engineering-speak?
How are you at working on a team?
Are you comfortable delivering bad news?
Do you have good time-management and multitasking skills?
Do you believe the old line that the customer is
always right? Give an example where that might
not be true.
Do you have a commitment to product quality?
Are you more comfortable being bound by rules,
or would you rather make them up as you go;
in other words, are you at ease maneuvering in
uncharted waters?
Are you a good listener? If not, are you willing to
suspend your prejudices and preconceptions and
become one?
Do you understand the difference between quality
and reliability? Can you explain that difference,
using examples, in laymans terms? Can you do so
in another language other than the one you were
raised with?
Are you bilingual; i.e., can you switch with ease
between technical and non-technical terminology,
depending upon the listener?
NOVEMBER 2016
TEST AND INSPECTION
Describe a recent technical problem you were confronted

with and how you resolved it.
How do you handle jerks?
Do you think being clever and being smart are the same or
different things?
Do you have leadership skills? What are they? Give a
recent example of how you used them.
Why would you possibly want to work for our little company when you could design apps, ride big white doubledecker buses, make lots of money, and pay cash for your
first house?
Do you like meetings or hate them?
What is your understanding, at this time of your life, of the
concept of job satisfaction?
Do you think Silicon Valley looks past its high A-----e Quotient due to its high creativity quotient? Is that a fair tradeoff?
Do you think one needs to be an a-----e in order to succeed
leading a high-tech business? Is it a fair assessment to say most
prominent business leaders have at least one screw loose?
Do you understand that technical excellence has a budgetary component? In other words, at a certain point, revenue
must begin to be generated? We arent Bell Labs! Hell, Bell
Labs isnt Bell Labs anymore.
What makes you think youre so good?
What question have we not asked you that you think we
should have asked you, and how would you answer it?
Do you find the excessive use of penetrating questions
annoying?
The few. The proud.

This summer we hosted an internship for the first time.
Our Hispanic female was selected to endure 12 weeks with
our kind. She prepared questions for us. Very thorough. Her
rivals didnt. Guys. The kind who are good at math and science, but deficient in questions. She blew us away. We chose
her. She came armed from day one with those incessant questions. Intellectual curiosity. Made the old gray-haired guys
squirm to find answers and remember what their acronyms
stood for. Makes you remember why you do what you do
and what it all means. Re-questioning timeless assumptions
to make sure they withstood scrutiny from the next generation. Thats healthy. That old nagging why? again. She
brought more questions, an avalanche of them, when a friend
graciously and proudly toured us through her manufacturing
facility. At the conclusion of the tour, with the perfunctory
any questions? request, out came the list. Typewritten and
single-spaced. Its good to see clear evidence of considered
thought. She took nothing for granted.
Good. We want people like that.
Success = Preparation + Opportunity + Luck.
And positive cash flow.
But first you have to set one foot, metaphorically, on
the path.
Her move.
OK, so she ran the gauntlet. Now what?
Our move.
continued on pg. 46
THE DEFECTS DATABASE
THE DEFECTS DATABASE
Flux Spitting/Vapors and Condensation

Slow the soldering, control the problem.
FLUX SPITTING IS essentially the same problem as sol-
control the escape of flux volatiles from the wire and,

at the same time, spitting of solder balls.
FIGURE 1 shows the point that flux escapes from
the wire during heating. It also shows solder balls
formed on a white ceramic tile when the wire was
not prepared.
These are typical defects shown in the National
Physical Laboratorys interactive assembly and soldering defects database. The database (http://defectsdatabase.npl.co.uk), available to all this publications
readers, allows engineers to search and view countless
defects and solutions, or to submit defects online.
To complement the defect of the month, NPL features the Defect Video
of the Month, presented
online by Bob Willis.
This describes over 20
different failure modes,
many with video examples of the defect occurring in real time. CA
FIGURE 1. Arrows in the images on the left and center show the flux escapes from cored
der balling. It is caused by soldering at a speed too fast
for the material or process settings in use. If a company
were to develop new cored wire, engineers would still
try to push the process window. Hence, the best way is
to look at the materials and the process.
Testing and observing the soldering characteristics of the wire during heating and reflow is a very
useful means to compare products. Japan Unix has
used high-speed video to show the difference in wires
and the degree of solder balling. Video on the companys website shows the benefits of wire preparation
prior to reflow. In our tests, we have been able to
MARTIN WICKHAM is a consultant at the National

Physical Laboratory
(npl.co.uk); martin.
wickham@npl.co.uk.
His column
appears monthly.
wire during heating. The image on the right shows solder balling due to unprepared wire.
NOVEMBER 2016
43
MACHINES
MATERIALS
TOOLS
SYSTEMS
OMA CALIBRATION TOOL
CAD WITH PARTS SEARCH

PCB Artist v. 3.2 professional-grade
PCB CAD includes upgrades to the
softwares Library Manager, improving the way users search and identify components from a library of
over 500,000 parts. Fetch Component
option on the Schematics and PCB
Context menu allows quicker component placement to the users current
cursor position with just a few clicks.
Optical modulation analyzer software

can evaluate multi-channel coherent
modulation schemes using a single
measurement system. Can calibrate and
control multiple OMAs to acquire and
analyze simultaneous data from multiple channels such as different wavelengths or fiber cores. Includes visual
OMA setup tool that facilitates reconfiguration of oscilloscopes and coherent
receiver frontends, so the same hardware can be used for different applications, like PAM4 research or increased
channel count in DP-QPSK testing.
SOFTWARE
FREE PCB CAD

PCB123 v. 5.4 offers production-style
manufacturing capabilities, including
more board thickness options; slots
and cutouts; longer lead times; copper weight options; smaller holes; closer clearances; and tighter tolerances.
Upgraded polygon handler, for handling
complex operations of merging, clipping and optimizing complex designs
for export manufacture. Retooled graphics/rendering engine offers better, more
accurate handling of very geometrically
complex design features.
Advanced Circuits
Tektronix
Sunstone Circuits
pcbartist.com
tek.com
pcb123.com
OTHERS OF NOTE
44
PLM/MRP-CAD INTEGRATION
PCB, CHASSES PROTOTYPING
2-WAY EDA TRANSLATION
EMA Enterprise Integrate provides direct

integration between OrCAD data and
corporate PLM and ERP/MRP systems.
Enables OrCAD to automatically upload
information from corporate systems
seamlessly while working within the
OrCAD environment. Maintains data
integrity between engineering WIP data
and corporate product lifecycle data.
IsoPro CNC2PCB software provides ability

to output DXF, Gerber, or NC drill data to
computer numerical control programs.
Follows EIA RS-274 industry standard;
can fabricate PCB or chassis on milling
center. For rapid PCB prototypes and programs for the mechanical chassis that fits
the PCB. Edits and converts Gerber, Excellon drill, and DXF files for use by quick
prototyping systems to fabricate boards,
delrin parts, aluminum chasses and other
mechanical components.
ACE Translator 3000 v 7.0 offers twoway translation between most common EDA, CAD, and 3D formats, in a
single intuitive environment. Converts
DXF, GDSII, Gerber, Postscript, PDF,
ODB++, TIFF, BITMAP, STEP, STL, and
more. Built-in viewer verifies translation results. Includes rulers, measurement tools, query, cell browser, hierarchy browser, HighLite broken polygons,
plus new editing and repair features.
EMA Design Automation
T-Tech
Numerical Innovations
ema-eda.com/connect
t-tech.com
numericalinnovations.com/collections/ace-translator-3000
EM SIMULATION SOFTWARE
HIGH-FREQUENCY LAMINATE
SYMBOL DESIGN ON-DEMAND
CST Studio Suite v. 17 accurately simulates phenomena that appear when components are combined into systems. New features permit individual components to be combined and simulated
effectively. Filter Designer 3D, a design and synthesis tool for cross-coupled cavity filters, can design
for arbitrary filter response with easy placement of
transmission zeros and a wide range of coupling
resonator topologies available to realize the corresponding filter response. Also extracts coupling
matrix, which helps analyze and tune a device.
AeroWave woven glass-reinforced thermoset UL-94 V0 material reportedly

exhibits excellent electrical and mechanical properties with a consistent, stable
Dk and low Df over frequencies ranging 1GHz to 35GHz and temperatures
from -40 to +125C. Low loss (0.0028
@10GHz) controlled dielectric constant
material (+/-0.05) comes in a range of
nominal cores and prepreg. PIM performance values exceed -160dBc typical.
InstaPart is an on-demand service that

delivers symbols and footprints to
designers inboxes in fewer than 24
hr. Can search and download models
for free. Digital models are compatible
with popular design tools via translation technology that exports to Eagle,
Altium, KiCad, Cadence OrCad/Allegro
(Beta), Mentor Graphics PADS (Beta)
and Pulsonix.
CST - Computer Simulation Technology
Shengyi Technology
SnapEDA
cst.com
shengyi-usa.com
snapeda.com
NOVEMBER 2016
MACHINES
MATERIALS
TOOLS
SYSTEMS
SOFTWARE
DUAL-WORKPLACE FUME EXTRACTION
TABLETOP VPS
MASTER TENSIONING FRAME
tensoRED is designed to provide more
tension than Alpha Tetra frame. No
air pressure on the frame is needed.
Reportedly delivers less paste smearing, reduced variation in volume deposits, and improved positional alignment
compared to Tetra frames.
Redesigned tabletop SV260 vapor

phase soldering machine offers easy
front-loading, for small series and
prototyping. Solders BGAs and LGAs.
Handles boards up to 300 x 260 x
80mm. Low energy and fluid consumption with two-chamber design
and integrated heat exchanger. Live
temperature monitoring. Maintenance-free transport system.
Zero Smog EL provides fume extraction for up to two workplaces. Provides clean, reconditioned air with a
combination ultrafine H13 HEPA/10%
active carbon foam filter that captures
0.3m, plus low-volume gas. Includes
M5 dust pre-filter that captures 40 to
50% of particles up to 100m. Features maintenance-free, brushless turbine, energy-saving air recirculation, a
simple filter replacement process and
optional remote control. Has blower
capacity of 220m3/h and extraction
power of 2,500Pa.
Alpha Assembly Solutions
IBL Technologies
Weller
alphaassembly.com
ibl-tech.com
weller-toolsus.com
OTHERS OF NOTE
LED PANEL X-RAY
FLEXIBLE ASSEMBLY GASKET
NONFLAMMABLE FLUX CLEANER
Jewel Box Oversize x-ray system is for

inspecting backplane and LED panels.
Accommodates 24" x 24" panel and
positioner can fully scan 23" x 12". Compact footprint requires minimal floor
space and is on wheels for ease of
movement throughout the facility. Provides up to 500X geometric and 2,000X
electronic magnification, five-axis positioner with 360 and 45 and optional
GTI image processing software.
Dymax GA-201 is a UV/visible lightcurable

form-in-place/cure-in-place
(FIP/CIP) gasket formulated for sealing plastic enclosures, glass enclosures,
metal enclosures, and plated surfaces
for automotive door handle, appliance
housing, and critical electronic assembly and device applications that require
a soft, tack-free, flexible gasket. Acts as
a barrier to moisture to prevent absorption or penetration of air, dust, noise,
liquids, gaseous substances, or dirt.
Electro-Wash Tri-V precision cleaner is

nonflammable cleaner and removes flux,
grease, oils, dirt, dust and other contaminants from electronic components and
assemblies. Max-Kleen Tri-V removes
soils, including oxidized oil and grease
from motors and relays. Flux-Off Tri-V
flux remover is an extra-strength nonflammable solvent that removes heavy
encrusted flux deposits common after
circuit board assembly. Works on R, RA,
RMA and synthetic fluxes.
Glenbrook Technologies
Dymax
Chemtronics
glenbrooktech.com
dymax.com
chemtronics.com
HARSH ENVIRONMENT SEALANT
PASTE CLEANER
MULTI-FUNCTION JTAG TESTER
Bergquist TLB 400 SLT two-part silicone

adhesive sealant, for automotive module applications, has adaptable thermal
cure profile that enables full cure at
temperatures from 25 to 180C. Cures
in minutes at higher temperatures.
Adhesion strength aluminum, steel
and plasma-treated plastic. Compatible
with gap filler materials.
Nano Stencil Clean is for cleaning solder paste from nanocoated stencils and
misprinted boards. Is environmentally
safe with a low pH and nearly zero
VOC content. Contains no CFCs, HCFCs,
terpenes, alcohol or other hazardous
ingredients. Performs in ultrasonic,
spray or manual cleaning applications.
Safe on metals and plastics and is
REACH and RoHS compliant.
JT 5705/FXT compact, single-board,

multi-function JTAG tester supports
analog measurement and stimulus,
frequency measurements, digital I/O,
boundary scan testing and in-system
device programming. Tester cards can
be mounted on carriers featuring Pylon
connectors.
Henkel
Nano Stencil
JTAG Technologies
henkel-adhesives.com/electronics
NanoStencil.com
jtag.com
NOVEMBER 2016
45
MARKETPLACE
Vertrel
Miller-Stephenson offers a wide range of solvent blends!

nPB & HCFC-225 replacements available!
These cleaning solvents are excellent for removing particulates, flux, light and heavy
oil and grease. Other Vertrel solvents are effective rinsing and drying agents. High
purity, nonflammable, low toxicity.
Vertrel XF Vertrel MCA Vertrel X-T85
Vertrel XSi Vertrel MCA Plus Vertrel SMT
Vertrel XMS Plus Vertrel XMS Vertrel MCA
Vertrel SFR Vertrel SDG Vertrel X-P10
Connecticut Illinois California Canada

http://cav.mschem.com
For technical information call 800.464.1967
Vertrel is a trademark of The Chemours Company FC, LLC
The CIRCUITS ASSEMBLY

DIRECTORY OF EMS COMPANIES
Build your EMS database Unrestricted use

2,900+ facilities worldwide Includes contact info, no. of lines,
markets served and more!
Sortable in Excel
circuitsassembly.com/dems
AD INDEX
Visit pcdandf.com or circuitsassembly.com to access the digital edition for links to advertisers' websites.
Company
Page No.
AIM, aimsolder.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Beta Layout, pcb-pool.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Directory of EMS Companies, circuitsassembly.com/dems. . . 19, 46
DownStream Technologies, downstreamtech.com. . . . . . . . . . . . . . 4
EMA, go.ema-eda.com/172-3D-1. . . . . . . . . . . . . . . . . . . . . . . . . . C4
HKPCA, hkpca-ipc-show.org . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Imagineering, Inc., PCBnet.com . . . . . . . . . . . . . . . . . . . . . . . . . 1, 47
IPC Apex Expo, ipcapexexpo.org. . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Master Bond, masterbond.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Miller-Stephenson, cav.mschem.com. . . . . . . . . . . . . . . . . . . . . . . 46
Online Electronics, pcb4less.com. . . . . . . . . . . . . . . . . . . . . . . . . . 47
Overnite Protos, pcborder.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

PCB West 2017, pcbwest.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Prototron Circuits, prototron.com. . . . . . . . . . . . . . . . . . . . . . . . . . . C3
Rogers, rogerscorp.com/acs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Seika Machinery, seikausa.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Sierra Circuits, hdidesignguide.com. . . . . . . . . . . . . . . . . . . . . . . . C2
SigmaTron, sigmatronintl.com/ca. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SMTA Pan Pac, smta.org/panpac . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Topline, ccga.co . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Test and Inspection, continued from pg. 43

Now comes the test for us. How
can we, as a small engineering firm,
embrace test engineering and sell it in
a sufficiently compelling way to attract
new talent? Someone with the requisite
qualifications has many choices. We
compete at a disadvantage. We arent
sexy. We are, however, sincere. And
we offer the opportunity to learn how
stuff works, why it breaks, how to fix
it, and how to keep customers happy.
We also offer unique exposure to the
running of a small business.
Gotta start somewhere. So here is
where well start.
Deep breath, the kind one takes
before launching into the Unknown.
Casting out into the deep waters, as
it were.
Our politicians say America needs
much long-delayed investment in infrastructure. This is ours, and here is our
investment. Our pipeline construction
begins now.
Au.: The author is grateful for the
assistance of AnaIsabel Huezo-Fernandez in compiling the qualifications and interview questions listed
herein. CA
Uyemura, uyemura.com. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
The advertising index is published as an additional service. The publisher does not assume any liability for errors or omissions.
Advertising Sales
Frances Stewart, 678-817-1286, fstewart@upmediagroup.com
46
NOVEMBER 2016
MARKETPLACE
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NOVEMBER 2016
Get
your
dose
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Subscribe to PCB UPdate

www.pcbupdate.com
The e-mail newsletter filled with
news and resources for PCB design,
fab and assembly professionals
47
TECHNICAL ABSTRACTS
In Case You Missed It

Electronic Materials
Substrate-Induced Nanoscale Undulations of Borophene on Silver
Authors: Zhuhua Zhang, et al; biy@rice.edu.
Abstract: Two-dimensional materials tend to be
mechanically flexible, yet planar, especially when
adhered on metal substrates. Here, the authors show
by first-principle calculations that periodic nanoscale
one-dimensional undulations can be preferred in borophenes on concertedly reconstructed Ag(111). This
wavy configuration is more stable than its planar
form on flat Ag(111) due to anisotropic high bending
flexibility of borophene that is also well described by
a continuum model. Atomic-scale ultrahigh vacuum
scanning tunneling microscopy characterization of
borophene grown on Ag(111) reveals such undulations, which agree with theory in terms of topography,
wavelength, Moir pattern, and prevalence of vacancy
defects. Although the lattice is coherent within a borophene island, the undulations nucleated from different
sides of the island form a distinctive domain boundary
when they are laterally misaligned. This structural
model suggests the transfer of undulated borophene
onto an elastomeric substrate would allow for high
levels of stretchability and compressibility with potential applications to emerging stretchable and foldable
devices. (Nano Letters, Sept. 22, 2016)
Implantable Electronics
This column provides

abstracts from recent
industry conferences
and company white
papers. Our goal is
to provide an added
opportunity for readers to keep abreast of
technology and business trends.
48
Ultraflexible Organic Photonic Skin

Authors: Tomoyuki Yokota, et al; yokota@
ntech.t.u-tokyo.ac.jp.
Abstract: The authors demonstrate ultraflexible and conformable three-color, highly efficient
polymer light-emitting diodes (PLEDs) and organic
photodetectors (OPDs) to realize optoelectronic skins
(oe-skins) that introduce multiple electronic functionalities such as sensing and displays on the surface
of human skin. The total thickness of the devices,
including the substrate and encapsulation layer, is
only 3m, one order of magnitude thinner than the
epidermal layer of human skin. By integrating green
and red PLEDs with OPDs, the authors fabricated
an ultraflexible reflective pulse oximeter. The device
unobtrusively measures the oxygen concentration of
blood when laminated on a finger. On-skin seven-segment digital displays and color indicators can visualize data directly on the body. (Science Advances, Apr.
15, 2016, vol. 2, no. 4)
Materials Qualification
BTC/QFN Test Board Design Considerations and
Method for Qualifying Soldering Materials and
Cleaning Processes
Authors: Mike Bixenman, Mark McMeen and
Jason Tynes; mikeb@kyzen.com.
Abstract: It becomes necessary from time to time

to change materials of construction, manufacturing processes and process conditions. A soldering
material or cleaning agent may become unavailable
due to environmental regulation, market forces, or
reformulation. The following conditions necessitate
validation and verification: 1. New soldering and/or
cleaning material changes that may improve performance or be more cost-effective. 2. New soldering or
cleaning equipment. 3. Technology assembly advances using a wide range of components placed in highly
dense footprints. Each of these conditions requires
some form of verification and validation that the process meets the OEMs quality and reliability specifications. J-STD-001, Requirements for Soldered Electrical and Electronic Assemblies, states validation and
verification be confirmed with test vehicles that are
representative of the product being produced. Many
industry test vehicles are dated and not representative
of current electrical and electronic assemblies. The
purpose of this research is to use a nonstandard test
board with sensors placed at the bottom termination
to study cleanliness and contamination effects under
QFN components. The nonstandard test board has
features to also study thermal paddle design options
and to develop a risk profile. This research reports
surface insulation resistance effects at the source of
the residue. (SMTAI, September 2016)
Solder
Improving the PCB Assembly Manufacturing Process by Utilizing an Alternative Solder Paste: A Statistical Evaluation
Author: Denis Barbini, Ph.D.; barbini@uic.com.
Abstract: Results from an investigation that studied and characterized a novel lead-free solder paste
compared to traditional solder materials. As a basis
for the analysis, solder materials were exposed to
harsh environments to understand if the new solder
paste technology is capable of withstanding the realities of modern manufacturing processes for fine-pitch
components (0.3mm CSPs and 01005/0201 passives).
Evaluation of solder paste printing performance was
a primary focus of the investigation, taking into
consideration numerous common board finishes and
stencil aperture designs. Paste volume measurements
acquired by SPI were used to verify solder paste volume on pads to quantify performance. Challenging
manufacturing processes were simulated by aging the
pastes at room versus elevated temperatures and then
printing at defined time intervals. Simulated extended
continuous printing was also examined. A detailed
statistical analysis identifies the relationship between
the condition of the solder paste and the paste volume on the pad of a given component type. (SMTAI,
September 2016)
NOVEMBER 2016
Will it Fit?
Know Before You Build
Do you find yourself crossing your fingers the first
time your board is put in its enclosure? The new
collision detection and advanced 3D analysis
tools in OrCAD 17.2 allow you to find
potential ECAD/MCAD integration issues
well before your first physical prototype is
produced. Design with confidenceno
rabbits foot needed.
Learn More

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