SCL 180nm CMOS Foundry: High Reliability ASIC

design for Aerospace Applications

Shri H.S.Jatana & Team
Semi-Conductor Laboratory (SCL),
Chandigarh

Nilesh M. Desai & Team

MRSA, Space Applications Centre (ISRO),
Ahmedabad

ABSTRACT
Semi-Conductor Laboratory (SCL) Fab. has been upgraded to 8 wafer fab to
support 180 nm CMOS process made available by M/s. Tower
Semiconductor Ltd, Israel. This tutorial describes SCL foundry process
features and capabilities. The tutorial will cover SCL Fab base line
technology features, analog process modules, digital standard cell library for
core and I/Os and memory modules. End to end design flow of digital and
mixed signal ASICs with case-study of recently completed ASIC designs
along with EDA tools will be covered in this tutorial. SCL Packaging, testing
and qualification capabilities will also be addressed.
This tutorial will also cover the role of ASICs in various aerospace
applications like remote sensing (microwave and optical), communication,
navigation etc. Space radiation environment and its effect on electronics
devices will be discussed in tutorial. Methodologies for design of
Highreliability ASIC with various radiation mitigation techniques will be
covered in tutorial. Radiation hardening by design (RHBD) and its
implementation aspects will also be suitably addressed.
This tutorial will further cover case studies of On Board Controller (OBC1.1) Digital ASIC and Addressable Synchronous Differential Receiver (ASDR)
mixed signal ASIC. Both these ASICs have been fabricated on 180 nm CMOS
process with front-end design by SAC and back-end design by SCL.
Details of each session:
1. Introduction of Aerospace Applications: This session would cover
introduction of various aerospace applications and usage of ASIC in
various on board missions of ISRO.
2. Process Flow and Integration issues in 180/130nm CMOS process:
The session would include the flow of 180/130nm CMOS Process and
process integration issues involved, key modules, SCL process highlights
in terms of design capability, SCL foundry infrastructure
3. Digital ASIC design with case study:
This session would include
complete digital ASIC design flow from requirements capture to GDS-II
generation. On Board Controller (OBC-1.1) design flow would be taken
as case study.
4. Analog ASIC design with case study: This session would include complete
analog mixed signal ASIC design flow from requirements capture to
GDS-II generation. Issues involved in design of analog circuits,

availability of different types of passive & active components and choice,

analog layout, etc would covered in this seeion. Addressable
Synchronous Differential Receiver (ASDR) mixed signal ASIC would be
taken as case study.
5. Development of RadHard Product: The session would dwell on radiation
effect on ICs, ways of prevention ( Process, design) with focus on design
techniques for digital / memory / analog circuits, our experience of
using RBHD techniques in few devices and results at silicon level.
Tutorial goals:
Providing information of Indigenous SCL, foundry to VLSI students,
researchers and industry professionals
It is great opportunity for Industry professionals in field of Electronics
Product Development, ASIC design & verification as well as students
to explore capabilities of SCL, foundry and utilize it for silicon
implementation of their products or projects.
End to end design flow with case-study will be useful for students to
gain practical knowledge about VLSI subject.
Challenges and opportunities of research in Aerospace applications
will be useful for VLSI researches.