724 MULTIPLEXERS (DATA SELECTORS) Multiplexing means sharing, There are two types of andonly one device is using the line, This is an example of time: ° given specific time intervals to use the line. In frequency m common line by transmitting at different frequencies. In a te the computer simultaneously. ‘A multiplexer (MUX) or data selector is a logic: allows only one of them at a time to get through Figure 7, ger outputs are drawn as large arrows to indicate Normally there are 2" input lines and m select ir is selected. a‘The AND gates and inverters gecode the selection input lines, n-to-2" decoder by adding to it 2"j in the multiplexer: In general, a 2”. input Lin to are applied to a single OR gate, The size ota jines and the single output line. The n selection decoders multiplexers may have an enable input 0 oo enable input is in the inactive state, the outp circuit functions as a normal multiplexer 7.24.3. The 16-Input Multiplexer from Two 8-Input Mul oe Figure 7.78 shows an arrangement to use two 8+i multiplexer. One OR gate and one inverter: Sp will select one of the 16 inputs to pass 1 is enabled. When S, = 0, the left multiplexer is of its data inputs will appear at its output and j multiplexer is enabled and S,,S,, and S, This arrangement is also called multip 32 x | mux using two 16 x 1 muxesComeINA same ‘TIONAL LOGIC DESIGN 349 ‘The truth table for F and the logic di, are shown in Figures 7,80a and b res ra i Sram to implement the function F using an 8 : | MUX elect inputs S>, S, and Sox spectively.‘ a spectively Pride The inputs x, y and z are applied to the data Tis connected to data inputs D,-D,, Bn 000, 010,011. and 101, logic D,, Dg and D. nd D., Logic 0 is connected to other data inputs D,, sow] 8x1 MUX * oD | —» Output =F (@) Truth table (6) Logie diagram Figure 7.80 Example 7.12. general, a multiplexer with n-data select inputs can implement any function ofn+1 variables. The key to this design is to use the first n variables of the function as the select inputs and to use the least significant input variable and its complement to drive some of the data inputs. If the single variable is denoted by D, each data output of the multiplexer will be D, D, 1, or 0. Suppose, we wish to implement a 4-variable logic function using a multiplexer with three data select inputs. Let the input variables be A, B, C, and D; Dis the LSB. A truth table for the function F(A, B, C, D) is constructed. In the truth table, we note that ‘ABC has the same value twice once with D'= 0 and again with D = 1. The following mules are used to determine the connections that should be made to the data inputs of the multiplexer. 1. If F = 0 both times when the same combination of ABC occurs, connect logic 0 to the data input selected by that combination. : 21F= t both scnes when the same combination of ABC occurs, connect 1oBie 1 to the data input selected by that combination. ‘df ee 4, IPF is different for the two occurrences of 8 combination of ABC, and if F= Din each tase, connect D to the data input selected PY that combina FF js different for the two occurrences Seg ‘D to the data input selected by that combination. case, connect EXAMPLE 7.13 Use a multiplexer havi \ i for the function eee using a 16:1 MUX. Form, 1.2.3.4, 10, 11, 14, 15). Solution fanction is shown in Figure 7.812. Since the given function is of ‘The truth table for the given Funct i select inputs (i.e. 8:1 mux) as shown four variables, we can use a ouplenet with hee aia ee350 FUNDAMENTALS OF DIGITAL CIRCUITS i i “ach of the two ete ible, since F is same for eac! : occu; eee ee et and ABC = 111 and since F= 1 in both re Di, Dj, Since Fis the same for each of two occurrences of ABC =o ABC= 100 and ABC = 116 and since F =0 in both cases, 0 is connected to Ds-D, and, Since F is different for each of the two occurrences of ABC = 010 and since F Din both cases, D is connected to D,. ’ Realization of the same using a 16:1 MUX is shown in Figure 7.81c. es Cases, 1 ig ee Sass ABC blr aay ite oot ‘8x 1 MUX Hea te, awe sti| F= cs, RRS] als DEdbao /1)|\9 F= eae =e o 1 1 ofo pum Te lomb=O | 4. Ps Output Fo eae 10 0 ojo kt + 100 ifg Feo pf Seta ts D, deme ei |. 4 F=1 D, | Ababa) | So B | oa sas} Gece i—>|D, ito ist act +p, (b) Logic diagram, _— Flgure7.81 Example 7.13,COMBINATIONAL LOGIC DESIGN ~351 AB =00, the output F = C, because F= 0) whenC = variable C be applied to data line 0. The opertioy nes Ewen C 00, data input O has a path to the outpi determine the required inputte data lines 1, 2, and: from and 11 respectively, a a “4 ion with a MUX; bc) =Em(l, 3, 5, 6) aa EXAMPLE 7.15~ Implement the following functi Fa, Choose a and b as select inputs. a m t Solution The truth table for F and the implementation of F(a, b, c)=E m(1, 3, 5,6) using a4: 1 MUX with select inputs a and b are shown in Figures 7.83a and b respectively. The inputs a and b are connected to the data select lines §, and S,, From the truth table we observe that BA 4 ta ss UG = 1. For both values of ab = 00, 2. For both values of ab = 11, F= 6. SoD, is FU TA, bam O11 3138 : iconsUNDAMENTALS OF DIGITAL CIROUITS “observe : are connected to the data select lines §, and Sp, From the truth tal puts a and b nk Sy Fi a pb=J0, "= and D, are com jected toc, lues of ab = 00, and ab Fac. SoD ind D, je ‘ Fi = 01, F=0. So D, is com 2. For both values of ab pe fies D, is connected to li 3. For both values of ab = 11, F cs : bf EXAMPLE 217“Amplement the following lose function using an 8 x 1 MU%: Pr eeicpies mise 1213 14,15) Solution ‘The truth table for the given fo MUX with three select inputs A, B, and ‘The inputs A, B, and C are connected table we observe that 1. For both values of ABC = 000, ABC = 001 connected to D. i “¢ 2. Foy both values of ABC = 010, F= D. So D, is connected to D. Bie isl valoes ceREGIEOiMsandAEC= 100, F = 0-SoD, andiD, are-connected #00 = 110, and AB "So D,and D, are connected to 1. nd its implementation using an 8:1 Figures 7.85a and b respectively. Tines S,y $,» and Sq. From the truth ur variable function F al Care shown in to the data select and ABC = 101, F=D. So Do, Dy, and DareCOMBINATIONAL LOGIC DESIGN 353 S._Si_ Sp e ‘ i ea ie 0 0 0 Tie oo 7 0 k 0115 g 1 j 0 te 1 10 Ose ii & 1 Log 1 1 1 oR ie 1 1000 sUMSg~ 85.5 (@) Truth table (b) Logic diagram 4a Sonclglatawas A Figure 7.86 Example 7.18. * ‘The inputs x,y and z are connected to the data select lines S$, and S,, From the truth able we observe that 1. F= 1 forxyz= 2, F=0 for xyz EXAMPLE Implement the following Boolean function using an. considering D as the input and A, B, C as the selection lines: ee F(A, B,C, D)=AB+BD + BCD Solution F(A, B, C, D) =AB + BD + BCD = 10XX + X1X1 + X010 000 + 1001 + 1010+ LmiB, 9, 10, 11, ae354 FUNDAMENTALS OF DIGITAL CIRCUTTS sea and Care connected t0 the data select lines So» S,, and So From the truth The inputs A, B, and C are c table we observe that is connected to 0. 1. For both values of ABC = 000. Fc = 101, F= 1. So Dg and Ds are connected toy iC = 100, ane nt =111,F=D. t e Nica Bae PABGMUIO/ABC =011, ABC=110, nd ABC oe D, and D, are connected to D. Bre BD. ec thouiraliel 6fAsc-=(001, F= D,SoD, is connected 10 7.26 DEMULTIPLEXERS (DATA DISTRIBUTORS) Amuttiplexer! i transmits one of them to the output, A demultiplexer performs Haat takes inate inputand dsebutes it over several outputs. So ademultipleer can be thought of as a ‘distributor’, since it transmits the same data to different destinations. ‘Thus, ‘whereas a multiplexer is an N-to-1 device, a demultiplexer is a 1-to-N (or 2") device. Figure 7.88 shows the functional diagram for a demultiplexer (DEMUX). The large arrows for inputs and ‘outputs can represent one or more lines. The ‘select’ input code determines the output line to which the input data will be transmitted. In other words, the demultiplexer takes one input data source and selectively distributes it to 1-of-N output channels just like a multi-position switch, or OO fad et UNT Li &.c 20rr COMBINATIONAL LOGIC DESIGN 355 0, will be enabled, and the data inputD will Pooch te other Outputs. The truth able HAE ee eee Figure 7.90b summarizes the operation. D Data ‘bout [1 )}—o,=088, {2 )—0, =08, | 3 }-— 02 = DS,8) ‘ S; So Os OQ, 0; O% rs 0 80, o 0 0 D }— %=08,8, ogg 0 Be " 1 oO 0 Do 0 Select inputs S, Sp ce bo Ovi (a) Logic diagram (o) Truthtable, Figure 7.89. 1-line to 4-line demultiplexer. 20 ni owes Data input 2 S, : s, S—+ 1 ;356 FUNDAMENTALS OF DIGITAL CIRCUITS select inputs. Depending on the select inputs, the data input will be routed to a particular output, For G6 landed anartectnrers oftew call this type of device a decoder/demultiplexer, ‘The 74LS138 decoder can be used as a demultiplexer by using B, as the data input D, holding the other two enable inputs in their active states and using the A,A,Ay inputs as the select code, 1" | fMableterp Eas’ used ap the data input, land the binary code inputs are used the | | | | EXAMPLE7.20 Implement the following multiple output combinational logic circuit using a4-line to 16-line decoder. F,=Em(1, 24,7, 8, 11, 12, 13) F,=2m(2, 3,9, 11) } F, == m(10, 12, 13, 14) F,=2m(2, 4,8) Solution | The realization of the given multiple output logic circuit using a 4-line to 16-line decoder is | shown in Figure 7.91. The decoder’s outputs are active LOW; therefore, a NAND gate is i required for every output of the combinational circuit. In combinational logic design using a multiplexer, additional gates are not required, whereas the design using a demultiplexer Tequires additional gates. However, even with this disadvantage, the decoder is more €conomical in cases where non-trivial, multiple-output expressions of the same input variables are required. In such cases, one multiplexer is required for each output, whereas it is likel that only one decoder supported with a few gates would be required. Th ning decoder could have advantages over using a multiplexer. TeCOMBINATIONAL LOGIC DESIGN 357° decoders. In a similar manner 6-line to general m-line to n-line decoders ean ‘ Gens T-line to 128-line and 8-line to 256-line and in implemented, or EN Ay etl A, —- ta 4x16 . A, decoder . iS a Ay Ee Ay 15) ¥ EN 76 17) 4x16 a e x 2 decoder . ea . Ao at Earlier, the design of digital resistors and so on, Now the logic circuit des integrated circuits which are fabricated in soli design using ICs is called modular design. There are many le number of transistors and other components, on th Medium scale integration (MSD), large sca are all in use for various appli ran digital systems like computers. category. The designer will have tl illustrated by the following examP™ ‘ s.x8,0 oft wt Hew ant nts 420 A vec ly 240 tp. brains iaqaeed of. = AA—————— EE ” CIRCUITS 358 FUNDAMENTALS OF DIGITAI g 4:1 muxs: Figure 7.93 16:1 mux usin Two 16:1 Muxs and One 2: 6:1 muxes and one 2:1 mux is shown in 1 Mux Modules 7.27.2 Design of a 32:1 Mux Using ‘The arrangement to obtain a 32:1 mux using two | ne 2:1 Figure 7. Ma gost mux had 32 data inputs. So it requires five data select lines. Since a 16:1 may has only four data select lines, the inputs B.C,D,E are connected 10 the data select lines of both the 16:1 muxes and the most significant input A is connected to the single data select line of the 2 5 will appear at the input terminal 0 of mux. For the values of BCDE = 0000 to 1111, inputs 0 to L 3 inputs 16 to 31 will appear atthe input the 2:1 mux through the output F, of the first 16:1 mux and terminal 1 of the 2:1 mux through the output F, of the second 16:1 mux. For A= 0, output F=F, For A = 1, output F=F,. F, ue FABOOE