Reg. No. : Name Second Semester M.Tech. Degree (2013 Sch Branch : Electroni TAD 2001 : DESIGN OF VLSI SYS’ 3 Hours ; ; Instruction : Answer any two questians from eacModule. x yw ay De > 2 MODULI Implement the equation X = ((A’ + B’) +D' pi ie O°, E', F and G' represent the com nt of A, B, G, D, &| and, respectivelyyusing complementary 2, Consider CMOS inverter circuit with the following parameters. channel transistors and no velocity saturation > a bi 0 i «6 a * . a Draw the block diagram of a carry select adder and carry skip adder. Explain “ their operation with an example. 4 MODULE ~ II 7. Draw the circuit diagrams of row decoder and the column decoders fora memory with 4 rows and 8 columns. 8. Describe the circuit and operation of any one type of sense amplifier. 9. A 1-T DRAM cell consists of a single transistor connected in series with a capacitor. For a read, the bit line is precharged to Vpp/2 by a clocked precharge circuit. Then, the transistor is tuned on by applying a) Find the maximum voltage across the storage capacitor C, after a writing a 1 into the memory cell (i.e., bit line is driven to Vp = 2.5 V). b) Ignoring leakage currents, find the voltage on the bit line when this from the memory cell.SR Examination, September-2015 RCH METHODOLOGY P Questions from each Module) loduie — | lefining and formulating a Research problem in and Analytical Research eh and Applied Research and Quantitative Research Literature Survey in detail Module — II | of Hypothesis and testing of Hypothesis in detail se design involved in the Research process. on-probabilistic Sampling in the Module — il steps in the Preparation, Layout, Structure and Language of typical the preparations for making entation effective using audio- visual ghisandFeten aw [ae owing - + _ Intellectual Property ni i! copy right