VHDL CODE FOR HALF ADDER :

Object 1

ENTITY half_adder IS
--- Half Adder
PORT(a,b:IN BIT; s,c :OUT BIT);
END half_adder;
ARCHITECTURE half_adder_beh OF half_adder IS
BEGIN
s <= a XOR b;
-- Implements Sum for Half Adder
c <= a AND b;
-- Implements Carry for Half Adder
END half_adder_beh;

VHDL CODE FOR FULL ADDER :

ENTITY full_adder IS
PORT(a,b,c: IN BIT ;
sum, carry : OUT BIT);
END full_adder;

--- Full Adder

ARCHITECTURE full_adder_beh OF full_adder IS

BEGIN
PROCESS(a,b,c)
-- Sensitive on all the three bits
VARIABLE temp :BIT;
BEGIN
--- DOES the addition in one DELTA time
temp := a XOR b;
sum <= temp XOR c;
carry <= (a AND b) OR (temp AND c);
END PROCESS ;
END full_adder_beh;

Half Adder - Structural Verilog Design

module ADD_HALF (s,c,x,y);

output s,c;
input x,y;
wire s,c,x,y;
// this line is optional since nodes default to wires
xor G1 (s,x,y); // instantiation of XOR gate
and G2 (c,x,y); // instantiation of AND gate
endmodule Half Adder - Structural Verilog Design
module ADD_HALF (s,c,x,y);
output s,c;
input x,y;
wire s,c,x,y;
// this line is optional since nodes default to wires
xor G1 (s,x,y); // instantiation of XOR gate
and G2 (c,x,y); // instantiation of AND gate
endmodule

Full Adder Structural Verilog Design

module ADD_FULL (s,cout,x,y,cin);

output s,cout;
input x,y,cin;
//internal nodes also declared as wires
wire cin,x,y,s,cout,s1,c1,c2;
ADD_HALF HA1(s1,c1,x,y);
ADD_HALF HA2(s,c2,cin,s1);
or (cout,c1,c2);
endmodule

module ha(s,co,a,b);
output s,co;
input a,b;
xor1 u1(s,a,b);
and1 u2 (co,a,b);
endmodule

module fa(s,co,a,b,ci);
output s,co;
input a,b,ci;
xor1 u1(s,a,b,ci);
and1 u2(n1,a,b);
and1 u3(n2,b,ci);
and1 u4(n3,a,ci);
or1 u5(co,n1,n2,n3);

endmodule

Half Adder HDL Verilog Code

This page of verilog sourcecode covers HDL code for half adder, half substractor, full substractor
using verilog.
The half adder truth table and schematic (fig-1) is mentioned below. The boolean expressions are:
S= A (EXOR) B
C=A.B
Input-A
0
0
1
1

Input-B
0
1
0
1

Output-S
0
1
1
0

Output-C
0
0
0
1

Half Adder Schematic

Half Adder Verilog code

module ha ( a, b, s, c)
input a, b;
output s, c;
assign s= a ^ b;
assign c= a & b;
end module

Half Substractor
The half substractor truth table and schematic (fig-2) is mentioned below. The boolean expressions
are:
D= A (EXOR) B
Br=A'.B

Input-A
0
0
1
1

Input-B
0
1
0
1

Output-D
0
1
1
0

Output-Br
0
1
0
0

Half substractor Schematic

Half Substractor Verilog code

module hs ( a, b, d, br)
input a, b;
output d, br;
assign d= a ^ b;
assign br= ~a & b;
end module

Full Substractor
The full substractor truth table and schematic (fig-3) is mentioned below. The boolean expressions
are:
D= A (EXOR) B (EXOR) C
Br=A'.B + B.Cin + A'.Cin
Input-A
0
0
0
0
1
1
1
1

Input-B
0
0
1
1
0
0
1
1

Input-Cin
0
1
0
1
0
1
0
1

Output-D
0
1
1
0
1
0
0
1

Output-Br
0
1
1
1
0
0
0
1

Full substractor Schematic

Full Substractor Verilog code

module fs ( a, b, c, d, br)
input a, b, c;
output d, br;
assign d= a ^ b ^ c;
assign br=(( ~a)& (b ^ c)) | (b & c);
end module