ASSIGNMENT-1

Name: G.Karthikeyan
Username: 1417121
Mail id:karthikeyanvis1996 @gmail.com
1. How is 8255 (Programmable Peripheral Interface) configured
if its control register contains 9B h.

9BH => 1001 1011 =>

b6b5=00-> Mode0
b4=0-> Port A as input.
b3=1-> Port C as input (PC7-PC4)
b2=0-> Mode 0
b1=1-> Port B as input
b0=1-> Port C as input (PC3-PC0).

2. Interface 2k X 8 (i.e. 2716) EPROM with 8086 using multiple

input NAND gate decoder for memory locations FF800HFFFFFH.

When the 2k x 8 EPROM is used, address connection A10 A0 of the 8086

are connected to address inputs A10-A0 of the EPROM. The remaining nine
address pins (A19-A11) are connected to the inputs of a NAND gate decoder.
The decoder selects the EPROM from one of the many 2Kbyte sections of
the entire 1Mbyte address range of the 8086 microprocessor. In this circuit,
a single NAND gate decodes the memory address. The output of the NAND
gate is logic 0 whenever the 8086 address pins attached to its inputs (A19-

A11) are all logic 1s. The active low, logic 0 output of the NAND gate
decoder is connected to the CE input pin that selects (enables) the EPROM.

3. Find the total delay introduced by the instructions in the

following program. Take count as 8C H, Clock frequency as 2
MHz
Label

NEXT

DELAY

Mnemonics

No. of
T-state

No. of execution
times for each
instruction

Total T-state for

each instruction

MVI B, 00

DCR B

255

1020

MVI C, 8C

255

1785

DCR C

255x140=35700

142800

JNZ DELAY

10

254x140=35690
(T)
1x140=140(F)

357880

MOV A, B

255

1020

OUT PORT

10

255

2550

JMP NEXT

10

255

2550

Total no. of T-state 509612

Total execution time

execution time

= Total no. of T-state x one T-state

=509612x 0.5 micro sec

=254.806 milli sec

4. Draw the timing diagram for the instruction

5. Assume that the times required for the five functional units,
which operate in each of the five cycles are: 10 ns, 8 ns, 10
ns, 10 ns and 7 ns. Assume that pipelining add 1 ns of
overhead find the speed up versus single cycle data path.
Solution:
Since the unpipelined machine executes all instructions in a single clock
cycle, its average time per instruction is simply the clock cycle time. The
clock cycle time is equal to the sum of the times for each step in the
execution:
Average instruction execution time =10n+ 8n+ 10n+10n+ 7n
=45ns
The clock cycle time on the pipelined machine must be the largest time
for any stage in the pipeline (10 ns) plus the overhead of 1 ns, for a total
of 11 ns. Since the CPI is 1, this yields an average instruction execution
time of 11 ns. Thus,
Speedup from pipelining= Average instruction time unpipelined
-------------------------------------------------------------Average instruction time pipelined
45 ns /11 ns = 4.1 times