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Chap1 Lect02 Registers PDF
Chap1 Lect02 Registers PDF
CMPE 310
Basic Architecture
Outline
Q Internal programmer visible architecture, e.g. registers
Q Real Mode Addressing:
Real Mode Memory: 00000H-FFFFFH (the first 1MB of main memory).
Q Protected Mode Addressing: (covered later in the semester)
All of memory (applicable to 80286 and later processors).
Programmer invisible registers to control and operate the protected memory system.
Q 80x86 Memory Paging. (covered later in the semester)
CMPE 310
16-bit
registers
EAX
AH AX AL
EBX
AH AX AL
ECX
BH BX BL Base Index
CH CX CL Count
DH DX DL Data
Stack Pointer
SP
8-bit 16-bit
names
EDX
ESP
EBP
32-bit
extensions
BP
DI
SI
EDI
ESI
IP
FLAGS
EIP
EFLAGS
FS
GS
80386-Pentium III only
Base Pointer
Destination Index
Source Index
Instruction Pointer
Flags
CS
Code
DS
ES
SS
Data
Extra
Stack
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21 20 19 18 17 16
14 13 12 11 10 9
NT
IOP
IOP
31
ID
VIP
VIF
AC
VM
RF
O D I
1 0
The rightmost 5 flag bits and overflow change after many of the arithmetic and logic
instructions execute. Data transfer and control instructions never change the flags.
Q C (Carry):
Holds the carry out after addition or the borrow after subtraction.
Also indicates error conditions.
Q P (Parity):
0 for odd number of bits and 1 for even.
Obsolete feature of the 80x86.
Q A (Auxiliary Carry):
Highly specialized flag used by DAA and DAS instructions after BCD addition or
subtraction.
5
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1 MB
1F000
10000
00000
1000
Segment register
Shift
<< 4
+
F000
Offset
10
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1 MB
49000
4900
ES
34000
3400
SS
10F00
10F0
CS
10000
1000
DS
00000
Segmented addressing allows relocation of data and code.
OS can assign the segment addresses at run time.
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