UNIT-I

Design with HDL

By Prof. Shahzad Mobeen
Department of E&TC Engineering
Maulana Mukhtar Ahmad Nadvi Technical Campus
1
 TOPICS
Design flow
Language Constructs, Modeling styles
Data objects, Data types, Operators
Sequential statements
Concurrent statements
Packages and Libraries
Attributes
Operator overloading, Resolution functions ( Notes )
Mealy and Moore machine sequence detector and other state
machine examples
Compilation, Simulation, and Synthesis
Hierarchical and flat designs
Partitioning for synthesis
Resource sharing
Pipelining
Efficient coding styles 2
 Book Sources

T1: Charles Roth, and Lizy John “Digital System Design

using VHDL,” 2nd Ed., Cengage Learning.

T3: Steve Kilts “Advanced FPGA Design Architecture,

Implementation and Optimization,” Wiley.

R3: John F. Wakerly, “Digital Design Principles and

Practices,” 4th Ed., Prentice Hall

R6: Jayaram Bhasker, “A VHDL Primer,” 3rd Ed., PHI. 3

DESIGN FLOW

4
 Basic Design Methodology
Requirements

RTL Model Simulate

Synthesize

Gate-level
Model Simulate Test Bench

ASIC or FPGA Place & Route

Timing
Model Simulate 5
6
7
 HDL
( Hardware Description Language )

8
 Need of HDLs
Arguments :
 Why ONE More language ?
 Can’t our CHAMPs do everything ?
 FORTRAN , PASCAL , COBOL
 C , C++ , VB , JAVA

9
 Strengths & Limitations of C
Strengths…
• C is an extremely powerful Language.
• In fact even JAVA Compiler has been written Using C Language.
Limitations…
• C is a sequential language & the statements are executed in the order
in which they are written.
• But Electronic Hardware is CONCURRENT in Nature, which means
it functions on the occurrence of EVENTS.
• eg. In Asynchronous Counter when LSB F/F outputs a 1  0 then
middle F/F changes state and so on…till MSB F/F.
• C LANGUAGE cannot represent the CONCURRENT Nature of
Electronic Hardware EFFICIENTLY.
• Thus there is a need of a Special language which can efficiently
represent the behavior of Electronics Hardware.
 VHDL
VHDL = V + H.D.L.

V.H.S.I.C. means
Very High Speed Integrated Circuit

Hardware Description Language

Thus…..
V.H.D.L. = Very High Speed Integrated Circuit Hardware Description Language
 History of V.H.D.L.
• DOD-USA needed Very High SPEED ICs ( VHSICs )
• Contract Given to different vendors
• Incompatibility Issues while Integrating Designs
• Need of common standard to describe Digital Designs
• IBM , Texas Instruments , Intermetrics collaborate
• Standardized in 1987 as IEEE STD 1076 / VHDL-87
• Standardized in 1993 as IEEE STD 1164 / VHDL-93
• So , we will be studying VHDL-93 & Not VHDL-87
• VHDL : VERBOSE , Strongly Typed , Form-Free , Case-Insensitive
• VHDL is a combination of ….
Sequential Language , Concurrent Language , Net-List Language ,
Waveform Generation Language & Timing Specifications
 VHDL…
• Is used to “ MODEL the PDS ( Proposed Digital System )“
• Modeling means 2 Things :
a) To define signals through which PDS interacts with Real World
b) To define the Logical relationship between I/P & O/P Signals
• Primary usage is to describe DIGITAL HARDWARE.
• Digital Circuits are ultimately made up of LOGIC GATES.
• Keywords : AND,OR,NOT,XOR,XNOR ,describe LOGIC GATES.
• Hence VHDL can efficiently represent a DIGITAL SYSTEM.

• Cannot Model Digital System if expressed on TRANSISTOR Level

 DA Q DB QB
A
D Flip-Flop D Flip-Flop
 Things common to all Languages…

• Basic Program Constructs.

• Grammar ( called as SYNTAX ).
• Variables & ways of declaring them.
• Data Types ( What values the variables can hold )
• Language Compiler ( Converts English-Like Program into Machine-Language )

Thus Learning VHDL is nothing but learning NEWer ways of doing

the above things.
 Need of a Compiler…
Oh ! That’s
ENGLISH-LIKE !!

main( )
{
int x=10,y=20,z;
z=x+y;
What’s That ?
printf ( “ %d “, z ); Give me only
1010001111
getch( ) ;
}

..
1.

Th
11

at
00

’s
d
10

el
10

ic
iou
s!
Turbo C- Compiler

!
C - Program C-Compiler
main( )
( Software )
{
Processor
int x=10,y=20,z;  Syntax Check ( Hardware )
z=x+y;  Generates .obj File The ALU Then
printf ( “ %d “, z ); ie. Program into
machine language Adds the 2 nos. 10 & 20 and
getch( ) ;
Generates the result 30.
} (11000011….)

On your PC
HARDWARE
SYNTHESIS
TOOL
VHDL Program
( XILINX Software ) CPLD / FPGA
Syntax Check ( Programmable H/W )
For  Converts VHDL Programming The above device then operates
Half-Adder , MUX , Code Program Instructions as the desired Digital Circuit
Counter , into a GATE-
LEVEL NETLIST ( Half-Adder , MUX , Counter ,
µController
(11000011….) Or even a MicroController )
 A VHDL Program may consist of….
• LIBRARY STATEMENTS (LS)
COMPULSORY
• ENTITY Declaration (ED)
• ARCHITECTURE Body (AB)
• Configuration Declaration (CD)
• Package OPTIONAL

* Package Body (PB)

* Package Declaration (PD)

All Declarations are called P.D.U’s ( Primary Design Units )

All Body’s are called S.D.U’s ( Secondary Design Units )
Syntax For LIBRARY STATEMENTS (LS)
--SYNTAX
LIBRARY library_name;
USE library_name.package_name.function_name;

--ACTUAL Library Statements in a VHDL Model

LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL ;
 Syntax For Entity Declaration
ENTITY entity_name IS

PORT

(
signalname_1 : [ MODE ] [ DATATYPE ] ;
signalname_2 : [ MODE ] [ DATATYPE ] ; NO Semi-colon
signalname_3 : [ MODE ] [ DATATYPE ] ; after Last Signal
.
.
signalname_n : [ MODE ] [ DATATYPE ]
);

END entity_name ;

IN / OUT / INOUT
1) BIT ( 2-Valued Logic )
2) STD_LOGIC ( 9-Valued LOGIC ) --Preferred
Example of ED For an AND Gate
A
Y
and_gate
B

ENTITY and_gate IS

PORT

(
A : IN STD_LOGIC ;
B : IN STD_LOGIC ;
Y : OUT STD_LOGIC
);

END and_gate ;
 Syntax For ARCHITECTURE BODY

ARCHITECTURE arch_name OF entity_name IS

Declaratio
n Section
Local variables / Global Variables / Constants / …..
Don’t write anything if not needed

BEGIN

Here you ….

Express “ The Logical Relationship between your I/Ps & O/Ps as

a) Boolean Equation(s)

LOGIC
Section
b) Various Modeling Styles
c) Various Constructs

END arch_name ;
 Example of AB For AND Gate
ARCHITECTURE andgate_arch OF and_gate IS

BEGIN

Y < = A and B ; -- VHDL equivalent of Y = A.B

END arch_name ;
The Complete VHDL Program For AND Gate
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL ;

ENTITY and_gate IS
PORT

(
A : IN STD_LOGIC ;
B : IN STD_LOGIC ;
Y : OUT STD_LOGIC
);
END and_gate ;

ARCHITECTURE andgate_arch OF and_gate IS

BEGIN
Y < = A and B ;
END arch_name ;
 DATA TYPES
DATA OBJECTS
26
 Data Types
• All declarations of VHDL ports, signals, and
variables must specify their corresponding type
or subtype Types

Access Composite

Array Record

Scalar

Integer Physical
Real Enumerated
27
 VHDL Data Types
Scalar Types
• Integer
• Minimum range for any implementation as defined by standard: -
2,147,483,647 to 2,147,483,647
• Example assignments to a variable of type integer :

ARCHITECTURE
ARCHITECTURE test_int
test_int OFOF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: INTEGER;
INTEGER;
BEGIN
BEGIN
aa :=
:= 1;
1; --
-- OK
OK
aa :=
:= -1;
-1; --
-- OK
OK
aa :=
:= 1.0;
1.0; --
-- illegal
illegal
END
END PROCESS;
PROCESS;
END
END test_int;
test_int;
28
 VHDL Data Types
Scalar Types (Cont.)

• Real
• Minimum range for any implementation as defined by
standard: -1.0E38 to 1.0E38
• Example assignments to a variable of type real :

ARCHITECTURE
ARCHITECTURE test_real
test_real OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: REAL;
REAL;
BEGIN
BEGIN
aa :=
:= 1.3;
1.3; --
-- OK
OK
aa :=
:= -7.5;
-7.5; ---- OK
OK
aa :=
:= 1;
1; --
-- illegal
illegal
aa :=
:= 1.7E13;
1.7E13; ---- OKOK 29
a := 5.3 ns; -- illegal
 VHDL Data Types
Scalar Types (Cont.)
• Enumerated
• User specifies list of possible values
• Example declaration and usage of enumerated data type :

TYPE
TYPE binary
binary ISIS (( ON,
ON, OFF
OFF );
);
...
... some
some statements
statements ... ...
ARCHITECTURE
ARCHITECTURE test_enum
test_enum OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (X)
(X)
VARIABLE
VARIABLE a:a: binary;
binary;
BEGIN
BEGIN
aa :=
:= ON;
ON; ---- OK
OK
...
... more
more statements
statements ... ...
aa :=
:= OFF;
OFF; ---- OK
OK
...
... more
more statements
statements ... ...
END
END PROCESS;
PROCESS;
END
END test_enum;
test_enum;
30
 VHDL Data Types
Scalar Types (Cont.)

• Physical
• Require associated units
• Range must be specified
• Example of physical type declaration :

TYPE
TYPE resistance
resistance IS
IS RANGE
RANGE 00 TO
TO 10000000
10000000

UNITS
UNITS
ohm;
ohm; ---- ohm
ohm
Kohm
Kohm == 1000
1000 ohm;
ohm; --
-- i.e.
i.e. 11 KW
KW
Mohm
Mohm == 1000
1000 kohm;
kohm; --
-- i.e.
i.e. 11 MW
MW
END
END UNITS;
UNITS;

Time is the only physical type predefined in

VHDL standard 31
 VHDL Data Types
Composite Types
• Array
• Used to group elements of the same type into a single VHDL object
• Range may be unconstrained in declaration
• Range would then be constrained when array is used
• Example declaration for one-dimensional array

TYPE
TYPE data_bus
data_bus IS
IS ARRAY(0
ARRAY(0 TO
TO 31)
31) OF
OF BIT;
BIT;
• (vector) : 0 ...element indices... 31

0 ...array values... 1

VARIABLE
VARIABLE XX :: data_bus;
data_bus;
VARIABLE
VARIABLE YY :: BIT;
BIT;

YY :=
:= X(12);
X(12); --
-- YY gets
gets value
value of
of element
element at
at index
index 12
1232
 VHDL Data Types
Composite Types (Cont.)
• Example one-dimensional array using
DOWNTO :
TYPE
TYPE reg_type
reg_type IS
IS ARRAY(15
ARRAY(15 DOWNTO
DOWNTO 0)
0) OF
OF BIT;
BIT;

15 ...element indices... 0
0 ...array values... 1

VARIABLE
VARIABLE XX :: reg_type;
reg_type;
VARIABLE
VARIABLE YY :: BIT;
BIT;

YY :=
:= X(4);
X(4); --
-- YY gets
gets value
value of
of element
element at
at index
index 44

• DOWNTO keyword must be used if leftmost index is

greater than rightmost index
• e.g. ‘Big-Endian’ bit ordering 33
 VHDL Data Types
Composite Types (Cont.)

• Records
• Used to group elements of possibly different types into a single
VHDL object
• Elements are indexed via field names
• Examples of record declaration and usage :
TYPE
TYPE binary
binary IS
IS (( ON,
ON, OFF
OFF );
);
TYPE
TYPE switch_info
switch_info IS IS
RECORD
RECORD
status
status :: BINARY;
BINARY;
IDnumber
IDnumber :: INTEGER;
INTEGER;
END
END RECORD;
RECORD;

VARIABLE
VARIABLE switch
switch :: switch_info;
switch_info;
switch.status
switch.status :=
:= ON;
ON; ---- status
status of
of the
the switch
switch
switch.IDnumber
switch.IDnumber :=:= 30;
30; --
-- e.g.
e.g. number
number ofof the
the switch
switch 34
 VHDL Data Types
Access Type

• Access
• Analogous to pointers in other languages
• Allows for dynamic allocation of storage
• Useful for implementing queues, fifos, etc.

35
 VHDL Data Types
Subtypes
• Subtype
• Allows for user defined constraints on a data type
• e.g. a subtype based on an unconstrained VHDL type
• May include entire range of base type
• Assignments that are out of the subtype range are illegal
• Range violation detected at run time rather than compile time
because only base type is checked at compile time
• Subtype declaration syntax :
SUBTYPE
SUBTYPE name
name IS
IS base_type
base_type RANGE
RANGE <user
<user range>;
range>;

• Subtype
SUBTYPE example : IS INTEGER
SUBTYPE first_ten
first_ten IS INTEGER RANGE
RANGE 00 TO
TO 9;
9;
36
 VHDL Data Types
Summary
• All declarations of VHDL ports, signals, and
variables must include their associated type
or subtype
• Three forms of VHDL data types are :
• Access -- pointers for dynamic storage allocation
• Scalar -- includes Integer, Real, Enumerated, and
Physical
• Composite -- includes Array, and Record
• A set of built-in data types are defined in
VHDL standard
• User can also define own data types and subtypes
37
 VHDL Objects
• There are four types of objects in VHDL
• Constants
• Variables
• Signals
• Files
• The scope of an object is as follows :
• Objects declared in a package are available to all
VHDL descriptions that use that package
• Objects declared in an entity are available to all
architectures associated with that entity
• Objects declared in an architecture are available to all
statements in that architecture
• Objects declared in a process are available only within
that process 38
 VHDL Objects
Constants
• Name assigned to a specific value of a type
• Allow for easy update and readability
• Declaration of constant may omit value so
that the value assignment may be deferred
• Facilitates reconfiguration
• Declaration
CONSTANT syntax : :: type_name
CONSTANT constant_name
constant_name type_name [:=
[:= value];
value];

CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT SPEED : INTEGER;
CONSTANT SPEED : INTEGER;
39
 VHDL Objects
Variables
• Provide convenient mechanism for local
storage
• E.g. loop counters, intermediate values
• Scope is process in which they are declared
• VHDL ‘93 provides for global variables, to be
discussed in the Advanced Concepts in VHDL
module
• VARIABLE
All variable
VARIABLE assignments
variable_name
variable_name take[:=
:: type_name
type_name place
[:= value];
value];

immediately
• No delta
VARIABLE
VARIABLE or user
opcode
opcode specified delay
:: BIT_VECTOR(3
BIT_VECTOR(3 DOWNTOis0)
DOWNTO incurred
0) :=
:= "0000";
"0000";
• Declaration syntax:
VARIABLE
VARIABLE freq
freq :: INTEGER;
INTEGER; 40
 VHDL Objects
Signals
• Used for communication between VHDL
components
• Real, physical signals in system often mapped
to VHDL signals
• ALL VHDL signal assignments require either
delta cycle or user-specified delay before new
value is assumed
SIGNAL
SIGNAL signal_name
signal_name :: type_name
type_name [:=
[:= value];
value];

• Declaration syntax :
SIGNAL
SIGNAL brdy
brdy :: BIT;
BIT;
brdy
brdy <=
<= '0'
'0' AFTER
AFTER 5ns,
5ns, '1'
'1' AFTER
AFTER 10ns;
10ns;
• Declaration and assignment examples : 41
 Signals and Variables
• This example highlights the difference
between signals and variables
ARCHITECTURE
ARCHITECTURE test1
test1 OFOF mux
mux IS
IS ARCHITECTURE
ARCHITECTURE test2
test2 OFOF mux
mux IS
IS
SIGNAL
SIGNAL xx :: BIT
BIT :=
:= '1';
'1'; SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0';
SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0'; BEGIN
BEGIN
BEGIN
BEGIN PROCESS
PROCESS (in_sig,
(in_sig, y)y)
PROCESS
PROCESS (in_sig,
(in_sig, x,x, y)y) VARIABLE
VARIABLE xx :: BIT
BIT :=:= '1';
'1';
BEGIN
BEGIN BEGIN
BEGIN
xx <=
<= in_sig
in_sig XOR
XOR y;y; xx :=
:= in_sig
in_sig XOR
XOR y;
y;
yy <=
<= in_sig
in_sig XOR
XOR x;x; yy <=
<= in_sig
in_sig XOR
XOR x;
x;
END
END PROCESS;
PROCESS; END PROCESS;
END PROCESS;
END
END test1;
test1; END
END test2;
test2;

 Assuming a 1 to 0 transition on in_sig, what are

the resulting values for y in the both cases?
42
 VHDL Objects
Signals vs Variables
• A key difference between variables and
signals is the assignment delay
ARCHITECTURE
ARCHITECTURE sig_ex
sig_ex OF OF test
test IS
IS
PROCESS (a, b, c, out_1)
PROCESS (a, b, c, out_1)
BEGIN
BEGIN
out_1
out_1 <=
<= aa NAND
NAND b;
b;
out_2
out_2 <= out_1 XOR c;
<= out_1 XOR c;
END
END PROCESS;
PROCESS;
END sig_ex;
END sig_ex;

Time a b c out_1 out_2

0 0 1 1 1 0
1 1 1 1 1 0
1+d 1 1 1 0 0
1+2d 1 1 1 0 1 43
 VHDL Objects
Signals vs Variables (Cont.)
ARCHITECTURE
ARCHITECTURE var_ex
var_ex OF OF test
test IS
IS
BEGIN
BEGIN
PROCESS
PROCESS (a,
(a, b,b, c)
c)
VARIABLE
VARIABLE out_3
out_3 :: BIT;
BIT;
BEGIN
BEGIN
out_3
out_3 :=
:= aa NAND
NAND b;b;
out_4
out_4 <=
<= out_3
out_3 XOR
XOR c;c;
END
END PROCESS;
PROCESS;
END
END var_ex;
var_ex;

Time a b c out_3 out_4

0 0 1 1 1 0
1 1 1 1 0 0
1+d 1 1 1 0 1
44
 Types of Statements
 Concurrent Statements
PROCESS Clause ( Most Frequently used )
WHEN-ELSE Construct ( Frequently used )
WITH-SELECT Construct ( Sparingly used )
 Sequential Statements
IF-THEN-ELSE-END IF Construct ( 2 conditions )
IF-THEN-ELSIF-END IF Construct ( > 2 conditions)
( Most Frequently used )
CASE Construct ( Frequently used )
 Sequential Statements are always embedded
within Concurrent statements
 Concurrent Statements are Stand-Alone 45
VHDL Constructs

46
PROCESS Clause
&
CASE Construct
47
 Syntax For PROCESS Clause
ARCHITECTURE arch_name OF entity_name IS

BEGIN
PROCESS ( Sensitivity List )
BEGIN

-- LOGIC expressed using Sequential Statements

-- IF – THEN – ELSE - END IF
-- IF – THEN –ELSIF - END IF
-- CASE – END CASE Construct

END PROCESS ;

END arch_name ;

SENSITIVITY List ( SL ) :

It is a list of all those Signals on which the O/P is dependent ( Sensitive )

Naturally , this List will contain “ ALL I/P Signals “
Eg. SL for 2:1 MUX will contain all I/P Signals : I0 , I1 ,I2 , I3 , S1 , S0
4:1 MUX ( Using PROCESS Clause)
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL ;

entity mux41_bms_CASE is
Port
(
I : in STD_LOGIC_VECTOR (0 to 3);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC
);
end mux41_bms_CASE;

architecture mux41_bms_CASE_arch of mux41_bms_CASE is

begin
PROCESS ( I , S )
BEGIN
CASE S IS
WHEN "00" => Y <= I(0);
WHEN "01" => Y <= I(1);
WHEN "10" => Y <= I(2);
WHEN OTHERS => Y <= I(3);
END CASE;
END PROCESS;
end mux41_bms_CASE_arch;
WHEN-ELSE
Construct
50
4:1 MUX ( Using WHEN-ELSE Construct )
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41_dms is
Port
(
I : in STD_LOGIC_VECTOR (0 to 3);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC
);
end mux41_dms;

architecture mux41_dms _arch of mux41_dms is

begin
Y <= I(0) WHEN S=“000” ELSE
I(1) WHEN S=“001” ELSE
I(2) WHEN S=“010” ELSE
I(3) ;

end mux41_dms _arch;

 IF-THEN-ELSE-END IF
IF-THEN-ELSIF-END IF
Constructs
52
2:1 MUX ( Using IF-THEN-ELSE-END IF)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux21 is
Port
(
I0 , I1 : in STD_LOGIC ;
S : in STD_LOGIC ;
Y : out STD_LOGIC
);
end mux21;
architecture mux21 _arch of mux21 is
begin
PROCESS ( I0 , I1 , S )
BEGIN
IF S=‘0’ THEN ----- Do not FORGET to write “ THEN “
Y <= I0 ;
ELSE
Y <= I1 ;
END IF ; ----- ENDIF is not allowed
END PROCESS;

end mux21 _arch;

4:1 MUX ( Using IF-THEN-ELSIF-END IF)
--LS
entity mux41 is
Port
(
I : in STD_LOGIC_VECTOR ( 0 TO 3) ;
S : in STD_LOGIC_VECTOR ( 1 DOWNTO 0 ) ;
Y : out STD_LOGIC
);
end mux41;
architecture mux41 _arch of mux41 is
begin
PROCESS ( I , S )
BEGIN
IF S= “00” THEN
Y <= I(0) ; -- (0) accesses 1st bit of the 4-bit Sugnal “I” & 1st I/P of MUX
ELSIF S= “01” THEN -- ELSE IF is not allowed
Y <= I(1) ;
ELSIF S= “10” THEN
Y <= I(2) ;
ELSE
Y <= I(3) ;
END IF ;
END PROCESS;
end mux41 _arch;
 Modeling Styles (MS) in VHDL
 What is a MS ?
 It is a way of expressing functionality of PDS
 We can write Multiple Programs to model same PDS
 Functionality remains same , H/W inferred may change
 4 Styles ( B , D , S , M )
 B : Behavioral ( BMS )
 D : Dataflow ( DMS )
 S : Structural ( SMS )
 M : Mixed ( MMS )
 How to identify which MS has been used ?
 By looking for specific KEYWORDS / Constructs in
the VHDL Program 55
How to Identify the Modeling Style
 If you find “PROCESS” clause
Its Behavioral MS
 If you find following Constructs :
With Select
When-Else
Its Dataflow MS
 If you find following Constructs :
COMPONENT – END COMPONENT
PORT MAP ( )
Its Structural MS
 If you find Two / More of above in Same Program
Its Mixed MS 56
BEHAVIORAL
MODELING
STYLE
57
 VHDL Program For 4:1 MUX

I0

I1
mux41_bms_CASE Y
I2

I3

s1 s0
4:1 MUX ( Behavioral Modeling Style )
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL ;

entity mux41_bms_CASE is
Port
(
I : in STD_LOGIC_VECTOR (0 to 3);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC
);
end mux41_bms_CASE;

architecture mux41_bms_CASE_arch of mux41_bms_CASE is

begin
PROCESS ( I , S )
BEGIN
CASE S IS
WHEN "00" => Y <= I(0);
WHEN "01" => Y <= I(1);
WHEN "10" => Y <= I(2);
WHEN OTHERS => Y <= I(3);
END CASE;
END PROCESS;
end mux41_bms_CASE_arch;
DATAFLOW
MODELING
STYLE
60
 VHDL Program For 4:1 MUX

I0

I1
mux41_bms_CASE Y
I2

I3

s1 s0
 4:1 MUX ( DMS ) : WHEN-ELSE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux41_dms is
Port
(
I : in STD_LOGIC_VECTOR (0 to 3);
S : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC
);
end mux41_dms;

architecture mux41_dms _arch of mux41_dms is

begin
Y <= I(0) WHEN S=“000” ELSE
I(1) WHEN S=“001” ELSE
I(2) WHEN S=“010” ELSE
I(3) ;

end mux41_dms _arch;

STRUCTURAL
MODELING
STYLE
63
Structural Modeling Style (SMS)
 VHDL Program using SMS has 4 Parts :

SR.NO. Part Name Location

1) COMPONENT Creation Declaration Section of AB
2) Declaration of Connecting Signals Declaration Section of AB

3) COMPONENT Instantiation Logic Section of AB

4) Port Mapping Logic Section of AB

64
 STRUCTURAL Modeling Style

cout
b
FULL ADDER
sum
cin
 STRUCTURAL Modeling Style…

carry1
a x1 c1
add1
x2 s1
b cout
sum1

carry2
x1 c1
add2
cin x2 s1 sum
 VHDL Program For FULL-ADDER
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_UNSIGNED.ALL ;
USE IEEE.NUMERIC_STD.ALL ;
ENTITY FA IS
Port
(
a : in std_logic;
b : in std_logic; ED for Main Entity
c : in std_logic;
“ THE FULL-ADDER “
sum : out std_logic;
cout : out std_logic
);
END FA ;

ARCHITECTURE FA_arch IS

COMPONENT add IS
PORT Creating COMPONENT
( “add” ( Half-Adder )
x1,x2 : in std_logic;
s1,c1 : out std_logic
);
END COMPONENT;

SIGNAL sum1,carry1,carry2 : std_logic ;

Intermediate Signals
BEGIN
Connecting the 2 Half-Adders
add1 & add2
add1 : add PORT MAP (x1=>a,x2=>b,c1=>carry1,s1=>sum1);
add2 : add PORT MAP (x1=>sum1,x2=>c,c1=>carry2,s1=>sum);
The Carry output of FA
cout<=carry1 OR carry2;

END FA_arch ;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY add IS
PORT ED for the COMPONENT
( “add” ( Half-Adder )
x1,x2 : in std_logic;
s1,c1 : out std_logic
);
END add;

ARCHITECTURE add_struct OF add IS

begin
AB for the COMPONENT
s1 <= x1 XOR x2;
c1 <= x1 AND x2;
“add” ( Half-Adder )

END add_struct;
PACKAGES
LIBRARIES
70
 Packages and Libraries
• User defined constructs declared inside
architectures and entities are not visible to
other VHDL components
• Scope of subprograms, user defined data types,
constants, and signals is limited to the VHDL
components in which they are declared

• Packages and libraries provide the ability to

reuse constructs in multiple entities and
architectures 71
 Packages
• Packages consist of two parts
• Package declaration -- contains declarations of
objects defined in the package
• Package body -- contains necessary definitions
for certain objects in package declaration
• e.g. subprogram descriptions
Signal declarations

• Examples of VHDL items included
 Attribute in
declarations
packages :  Component declarations

• Basic declarations
• Types, subtypes
• Constants
72
• Subprograms
 Packages
Declaration
• An example of a package declaration :
PACKAGE
PACKAGE my_stuff
my_stuff ISIS
TYPE
TYPE binary
binary IS
IS (( ON,
ON, OFF
OFF );
);
CONSTANT
CONSTANT PI
PI :: REAL
REAL :=
:= 3.14;
3.14;
CONSTANT
CONSTANT My_ID
My_ID :: INTEGER;
INTEGER;
PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,
b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result,
temp_result, temp_carry
temp_carry :: OUTOUT BIT);
BIT);
END
END my_stuff;
my_stuff;

• Note some items only require declaration

while others need further detail provided in
subsequent package body 73
 Packages
Package Body
• The package body includes the necessary
functional descriptions needed for objects
declared in the package declaration
• e.g. subprogram descriptions, assignments to
PACKAGEconstants
PACKAGE BODY
BODY my_stuff
my_stuff IS
IS
CONSTANT
CONSTANT My_ID
My_ID :: INTEGER
INTEGER :=
:= 2;
2;

PROCEDURE
PROCEDURE add_bits3(SIGNAL
add_bits3(SIGNAL a, a, b,
b, en
en :: IN
IN BIT;
BIT;
SIGNAL
SIGNAL temp_result,
temp_result, temp_carry
temp_carry :: OUT OUT BIT)
BIT) IS
IS
BEGIN
BEGIN --
-- this
this function
function cancan return
return aa carry
carry
temp_result
temp_result <=
<= (a
(a XOR
XOR b)b) AND
AND en;
en;
temp_carry
temp_carry <=
<= aa AND
AND bb AND
AND en;
en;
END
END add_bits3;
add_bits3;
END
END my_stuff;
my_stuff;

74
 Packages
Use Clause
• Packages must be made visible before their
contents can be used
• The USE clause makes packages visible to
entities, architectures, and other packages
-- use only the binary and add_bits3 declarations
USE my_stuff.binary, my_stuff.add_bits3;

... ENTITY declaration...

... ARCHITECTURE declaration ...

-- use all of the declarations in package my_stuff

USE my_stuff.ALL;

... ENTITY declaration...

... ARCHITECTURE declaration ...
75
 Libraries
• Analogous to directories of files
• VHDL libraries contain analyzed (i.e.
compiled) VHDL entities, architectures, and
packages
• Facilitate administration of configuration
and revision control
• E.g. libraries of previous designs
• Libraries accessed via an assigned logical
name
• Current design unit is compiled into the Work 76
library
 Signals and Variables
• This example highlights the difference
between signals and variables
ARCHITECTURE
ARCHITECTURE test1
test1 OFOF mux
mux IS
IS ARCHITECTURE
ARCHITECTURE test2
test2 OFOF mux
mux IS
IS
SIGNAL
SIGNAL xx :: BIT
BIT :=
:= '1';
'1'; SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0';
SIGNAL
SIGNAL yy :: BIT
BIT :=
:= '0';
'0'; BEGIN
BEGIN
BEGIN
BEGIN PROCESS
PROCESS (in_sig,
(in_sig, y)y)
PROCESS
PROCESS (in_sig,
(in_sig, x,x, y)y) VARIABLE
VARIABLE xx :: BIT
BIT :=:= '1';
'1';
BEGIN
BEGIN BEGIN
BEGIN
xx <=
<= in_sig
in_sig XOR
XOR y;y; xx :=
:= in_sig
in_sig XOR
XOR y;
y;
yy <=
<= in_sig
in_sig XOR
XOR x;x; yy <=
<= in_sig
in_sig XOR
XOR x;
x;
END
END PROCESS;
PROCESS; END PROCESS;
END PROCESS;
END
END test1;
test1; END
END test2;
test2;

 Assuming a 1 to 0 transition on in_sig, what are

the resulting values for y in the both cases?
77
 FUNCTIONS
PROCEDURES
78
ATTRIBUTES
OPERATORS
79
 Attributes
• Attributes provide information about certain
items in VHDL
• E.g. types, subtypes, procedures, functions,
signals, variables, constants, entities,
architectures, configurations,
name'attribute_identifier
packages,
name'attribute_identifier -- read as
-- read as "tick"
"tick"
components
• General form of attribute use :

• VHDL has several predefined, e.g :

• X'EVENT -- TRUE when there is an event on 80
 Attributes
Register Example
• The following example shows how
attributes can be used to make an 8-bit
register
• Specifications :
• Triggers on rising clock edge
• Latches only on enable high
ENTITY 8_bit_reg IS
•GENERIC
Has a (x_setup,
data setupprop_delay
time of x_setup
: TIME);
•PORT(enable, clk : IN qsim_state;
Hasa propagation delay of prop_delay
: IN qsim_state_vector(7 DOWNTO 0);
b : OUT qsim_state_vector(7 DOWNTO 0));
END 8_bit_reg;
 qsim_state type is being used - includes logic
values 0, 1, X, and Z 81
 Attributes
Register Example (Cont.)
 The following architecture is a first attempt at the
register
 The use of 'STABLE is to used to detect setup
violations in the data input
ARCHITECTURE first_attempt OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable = '1') AND a'STABLE(x_setup)
AND
(clk = '1') THEN
b <= a AFTER prop_delay;
END IF;
END PROCESS;
END first_attempt;
 What happens if a does not satisfy its setup time
requirement of x_setup? 82
 Attributes
 The followingRegister Example
architecture is a (Cont.)
second and more
robust attempt
 The use of 'LAST_VALUE ensures the clock is
rising from a value of ‘0’
ARCHITECTURE behavior OF 8_bit_reg IS
BEGIN
PROCESS (clk)
BEGIN
IF (enable = '1') AND a'STABLE(x_setup) AND
(clk = '1') AND (clk'LAST_VALUE = '0') THEN
b <= a AFTER prop_delay;
END IF;
END PROCESS;
END behavior;

 An ELSE clause could be added to define the

behavior when the requirements are not satisfied 83
 Operators
• Operators can be chained to form complex
expressions, e.g. :
res
res <=
<= aa AND
AND NOT(B)
NOT(B) OR
OR NOT(a)
NOT(a) AND
AND b;
b;

• Can use parentheses for readability and to

control the association of operators and
operands
• Defined precedence levels in decreasing
order :
• Miscellaneous operators -- **, abs, not
• Multiplication operators -- *, /, mod, rem
• Sign operator -- +, - 84
 Operators
Examples
• The concatenation operator &
VARIABLE
VARIABLE shifted,
shifted, shiftin
shiftin :: BIT_VECTOR(0
BIT_VECTOR(0 TO
TO 3);
3);
...
...
shifted
shifted :=
:= shiftin(1
shiftin(1 TO
TO 3)
3) && '0';
'0';
0 1 2 3
SHIFTIN 1 0 0 1

SHIFTED 0 0 1 0

 The exponentiation operator **

xx :=
:= 5**5
5**5 --
-- 5^5,
5^5, OKOK
yy :=
:= 0.5**3
0.5**3 --
-- 0.5^3,
0.5^3, OK
OK
xx :=
:= 4**0.5
4**0.5 --
-- 4^0.5,
4^0.5, Illegal
Illegal
yy :=
:= 0.5**(-2)
0.5**(-2) ---- 0.5^(-2),
0.5^(-2), OK
OK
85
VHDL Modeling
Of
STATE Machines
86
 Generic Steps
1) Create a Block Diagram Out of State Diagram
2) Create New Datatype in DS of AB
3) Define Signal belonging to Datatype
4) Use PROCESS Clause ( LS of AB )
5) Use CASE Construct within
6) IF-THEN-ELSIF-END IF within

87
 rst

w MOORE_MC z
clk

statemc Name of our State Machine

88
 VHDL Model of State m/c
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MOORE_MC is
Port ( rst : in std_logic;
clk : in std_logic;
W : in std_logic;
Z : out std_logic);
end MOORE_MC;

architecture MOORE_MC_arch of MOORE_MC is

TYPE state_name IS ( A , B , C );
SIGNAL statemc : state_name;

begin
 VHDL Model of State m/c…..
PROCESS( rst , clk , W )
BEGIN

IF rst='1' THEN

statemc<=A ;

ELSIF ( clk'EVENT AND clk='0' ) THEN

CASE statemc IS

WHEN A =>

IF W='1' THEN

statemc<= B;

ELSE

statemc<= A;

END IF;
 WHEN B =>

IF W='1' THEN

statemc<= C;

ELSE

statemc<= A;

END IF;

WHEN C =>

IF W='1' THEN

statemc<= C;

ELSE

statemc<= A;

END IF;

END CASE;
 VHDL Model of State m/c…..
END IF;

END PROCESS;

Z <= '1' WHEN statemc=C

ELSE '0';

end MOORE_MC_arch;
SIMULATION

93
 Testing the functionality of PDS
If I write in AND Gate Model : Y <= A OR B ;
Will it generate a SYNTHESIS Error ? NO
Download this Model into FPGA , you get OR Gate
If I would have Simulated my MODEL …
I would have caught LOGIC Error in my Design
 Done by writing a TestBench (TB) for PDS
 TB is 2nd VHDL MODEL in FPGA Design Flow
 TB uses a Blank Entity & Structural MS
 TB uses Multiple PROCESS’es w/o SL
 As many I/Ps , those many PROCESS’es
 Simulator ( ISim in XILINX ISE ) runs TB
 W/Fs show the Functional Correctness of MODEL
You will Appreciate it better , during Practical Session
94
 KNOWN
CORRECT
PDS RESULTS
TB Program ( Main Program )

STIMULUS DUT
DRIVER ( Device Under Test ) O/P Comparison
Test O/P
Vectors W/Fs
Modify
NO Real World I/Ps Model
Hence BLANK ED
YES
ERROR

We will Re-Visit the Above Flow-Model NO

During LAB Assignments
FPGA
Prototyping
 LIVE Tool Demo
 Simulation of AND Gate
 Simulation of XOR Gate
 Simulation of 2:1 MUX
 Simulation of 3-Bit Up Counter

96
SYNTHESIS

97
 PLD
AREA ( Area )
Technology -Family
User TIMING ( Speed ) --Member
Library
Constraints POWER ( Power ) ---Capacity
Balanced ---No. of Pins

Design SYNTHESIS TOOL Gate Level

Entry ( XILINX ISE ) Netlist

HDL ( VHDL / VeriLog ) Basic Gates

( AND , OR ,NOT )
Schematic
Multiplexer
EDIF
Latch ( Not Preferred )
NGC / NGO Flip-Flop

It is an Automated process of converting a High Level Of Abstraction

Into a Gate-Level Netlist ( Interconnection between BASIC Gates /
D F/F / Multiplexers )
 LIVE Tool Demo
 Synthesis of AND Gate
 Synthesis of NAND Gate
 Synthesis of XOR Gate
 Synthesis of 2:1 MUX
 Synthesis of D F/F

99
Hierarchical
&
Flat Designs
100
Hierarchy in Design is achieved by :  Structural MS
a) Component Creation  Top-Down Design Approach
b) Component Instantiation

G
C E
A
F
D
B
E
 XOR GATE

4-Bit
FULL-
Binary ADDER
AND GATE
Adder

OR GATE
BCD ADDER NOT GATE

XOR GATE
Partitioning
for Synthesis
( PFS )
103
METHOD -1 : Partitioning between Datapath and Control
 METHOD -2 : Clock and Reset Structures

With One type of Clock and One type of Reset.

 Problem of Hazards ( Static / Dynamic ) is rare

With Multiple clock domains and / or Reset structures

 partition the hierarchy to separate them by different modules.

Problem of Hazards appears by mixing Clock and Reset

types in procedural descriptions.
 METHOD -3 : Multiple Instantiations

Instance-1 Instance-2 Instance-3

VeriLog Model Multiple Instantiations

RESOURCE
SHARING
107
 Consider the following Code Section…
process (SEL, A, B, C, D)
begin
if (SEL = ‘1’) then

Y <= A + B; ADDER -1
else MUX
Y <= C + D; ADDER -2
end if ;
end process;

A , B are n-bit signals

Let us compute the MOSFET

Count if CMOS Logic is used
 If A , B are 4-bit signals
We need :
1) Two BINARY ADDERS
2) Single 2:1 MUX

3) Single BINARY ADDER = 4 Full-Adders

4) 1-bit Full-Adder = 2 XOR , 3 AND , 2 OR Gates
5) 1 XOR = 22 MOSFETs , 1 AND = 6 MOSFETs , 1 OR = 6 MOSFETs
6) 1-bit Full-Adder = 44 + 18 + 12 = 74 MOSFETs
7) Single BINARY ADDER = 74*4 = 296 MOSFETs
8) TWO BINARY ADDERS = 296*2 = 592 MOSFETs

9) Single MUX = 1 NOT , 2 AND , 1 OR Gate

10) Hence Single MUX = 2 + (2*6) + 6 = 20 MOSFETs
11) The Above H/W will need = 592 + 20 = 612 MOSFETs
 Revised Code with same functionality
Y1 <= A when SEL = ‘1’ else C; MUX -1

Y2 <= B when SEL = ‘1’ else D; MUX-2

Y <= Y1 + Y2; ADDER

WHEN-ELSE & IF-THEN-ELSE
infer MUX in H/W
Y1
We need :
**Single BINARY ADDER=296 C
TWO 2:1 MUX = 20*2 =40
** H/W will need = 336 MOSFETs
B Y
% Saving = 45 %
Y2
Advice : Write VHDL Models for
Both versions of Code
PIPELINING
111
Pipelining….

Speed Optimisation of Design done by Pipelining

 F/F to F/F throughput increased by adding Register stages
 Total latency with a small in AREA ( Trade-Off )
 F/Fs are moved @ logic to balance delay bet’n Register stages
 Also known as ReTiming , Register balancing

Regular structures like pipelined memories / Multipliers

are identified by Synthesis Tool
Structures are Re-Architected with redistributed logic to
achieve Load Balancing
Pipelining….
EFFICIENT
CODING
STYLES
114
EFFICIENT CODING STYLES….

 Removal of FALSE Paths

a) Control over Critical path Synthesis
b) Checking of Redundant conditions in IF
if (A) then
if (C) then
if (A) then -- avoid
 Unnecessary Calculations in “for” Loops
a) Placing unchanging expressions in “for” loops
b) Optimisation of Redundant Logic
 Avoid using Complex operators
a) Relational operators ( > , < )
 Arranging Expression Trees for Minimum delay
115
EFFICIENT CODING STYLES….
 CODING
EXAMPLES
117
 Coding on XILINX Tool
 4:1 MUX
 4:1 MUX with Enable
 3:8 Decoder
 74LS138
 ALU
 D Latch ( Incomplete IF Statement )
 D F/F
 D F/F with Reset
 D F/F with Reset & Preset
 3-Bit UP Counter , 3-bit DOWN Counter
 3-Bit UP Counter , 3-bit DOWN Counter with Reset , Preset
 4-Bit UP Down Counter with Asynchronous Reset Preset
118
 Coding on XILINX Tool
 Full-Adder Using Half-Adder as Component ( SMS )
 4:1 MUX Using 2:1 MUX as Component ( SMS )
 16:1 MUX Using 4:1 MUX as Component ( SMS )
 7483 ( 4-Bit Binary Adder ) using SMS
 3-Bit Asynchronous Counter using SMS
 2:1 MUX Using SMS
 Logic Gates Using MUX ( AND , OR ,……XNOR )
 Logic Gates Using MUX ( SMS )
 NOT Gate using NAND / NOR as Component
 4-Bit PRBS using SMS

119