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CMOS VLSI
Design
Slides adapted from:
N. Weste, D. Harris, CMOS VLSI Design,
Addison-Wesley, 3/e, 2004
Introduction
Integrated Circuits:
many transistors on one chip
Very Large Scale Integration (VLSI):
very many transistors on one chip
Complementary Metal Oxide Semiconductor (CMOS):
fast, cheap, low power
Outline
A Brief History
MOS transistors
CMOS Logic
CMOS Fabrication and Layout
Chip Design Challenges
System Design
Logic Design
Physical Design
Design Verification
Fabrication, Packaging and Testing
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A Brief History
T-R-A-N-S-I-S-T-O-R = TRANsfer resiSTOR
1947: John Bardeen, Walter Brattain and William Schokley at Bell
laboratories built the first working point contact transistor (Nobel
Prize in Physics in 1956)
1958: Jack Kylby built the first integrated circuit flip flop at Texas
Instruments (Nobel Prize in Physics in 2000)
1925: Julius Lilienfield patents the original idea of field effect
transistors
1935: Oskar Heil patents the first MOSFET
1963: Frank Wanlass at Fairchild describes the first CMOS logic
gate (nMOS and pMOS)
1970: Processes using nMOS became dominant
1980: Power consumption become a major issue. CMOS process
are widely adopted.
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A Brief History
Integrated Circuits enabled todays way of life
1018 transistors manufactured in 2003
100 million for every human on the planet
Moores Law
In 1963 Gordon Moore predicted that as a result of continuous miniaturization
transistor count would double every 18 months
53% compound annual growth rate over 45 years
No other technology has grown so fast so long
Transistors become smaller, faster, consume less power, and are
cheaper to manufacture
Technology Scaling
1971: Intel 4004
transistors with minimum dimension of 10um
2003: Pentium 4
transistors with minimum dimension of 130 nm
Scaling cannot go on forever because
transistors cannot be smaller than atoms
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Source: SEMATECH
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Silicon Lattice
Silicon is a semiconductor
Transistors are built on a silicon substrate
Silicon is a Group IV material
Forms crystal lattice with bonds to four neighbors
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Dopants
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
Si
Si
Si
Si
Si
Si
As
Si
Si
Si
Si
Si
Si
Si
+
-
Si
Si
Si
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Transistor Types
Bipolar transistors
npn or pnp silicon structure
Small current into very thin base layer controls large
currents between emitter and collector
Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors
nMOS and pMOS MOSFETS
Voltage applied to insulated gate controls current
between source and drain
Low power allows very high integration
13
MOS Transistors
Four terminals: gate, source, drain, body (= bulk = substrate)
14
nMOS Operation
Body is commonly tied to ground (0 V)
When the gate is at a low voltage:
P-type body is at low voltage
Source-body and drain-body diodes are OFF
No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
n+
n+
p
bulk Si
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Gate
Drain
Polysilicon
SiO2
n+
n+
p
bulk Si
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pMOS Transistor
Similar, but doping and voltages reversed
Body tied to high voltage (VDD)
Gate low: transistor ON
Gate high: transistor OFF
Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
bulk Si
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CMOS Technology
CMOS technology uses both nMOS and
pMOS transistors. The transistors are
arranged in a structure formed by two
complementary networks
Pull-up network is complement of pull-down
Parallel -> series, series -> parallel
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10
1= 0=
1
ON OFF
=1 =0
OFF ON
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22
11
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Compound Gates
Example: Y = (A+B+C) D
ABCD
---0
0001
1--1
-1-1
--11
1
1
0
0
0
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Compound Gates
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13
Pass Transistors
Transistors can be used as switches
28
14
Transmission Gates
Pass transistors produce degraded outputs
Transmission gates pass both 0 and 1 well
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30
15
31
Tristates
Tristate buffer produces Z when not enabled
EN
0
0
1
1
A
0
1
0
1
Y
Z
Z
0
1
32
16
Nonrestoring Tristates
Tristate Inverter
Tristate inverter produces restored output
For a non inverting tristate add an inverter in front
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17
Multiplexers
2:1 multiplexer chooses between two inputs
S
0
0
1
1
D1
X
X
0
1
D0
0
1
X
X
Y
0
1
0
1
S
D0
D1
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D1
S
D0
D1
S
D0
4
2
Y
36
18
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Inverting Mux
Inverting multiplexer
Use compound gate or pair of tristate inverters
Essentially the same thing
For noninverting multiplexer add an inverter
38
19
D Latch
When CLK = 1, latch is transparent
D flows through to Q like a buffer
When CLK = 0, the latch is opaque
Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
Latch
CLK
D
CLK
D
Q
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D Latch Design
Multiplexer chooses D or hold Q
CLK
D
CLK
Q
Q
0
CLK
CLK
CLK
40
20
D Latch Operation
Q
D
CLK = 1
Q
D
CLK = 0
CLK
D
Q
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D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, masterslave flip-flop
CLK
CLK
D
Flop
Q
Q
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21
D Flip-flop Design
Built from master and slave D latches
CLK
CLK
CLK
D
CLK
QM
Latch
Latch
CLK
D
QM
CLK
Q
CLK
CLK
Q
CLK
CLK
43
D Flip-flop Operation
D
QM
CLK = 0
QM
CLK = 1
CLK
D
Q
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22
Summary
If the automobile had followed the same
development cycle as the computer, a Rolls
Royce would today cost $100, get one million
miles per gallon, and explode once a year
Robert X. Cringely,
InfoWorld Magazine
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