Project - MOSFET (Electronics) PDF

Chapter1
Introduction
1.1History
MetalOxideSemiconductorFieldEffectTransistor(MOSFET)isusedinavastmanner
inVLSIdesignforhighspeedperformance,safeoperatingarea,unipolarityandeasiness
to be used inparallel. For the study of MOSFET characteristics and operations various
models have been proposed. All these models have their own assumptions and
predictions.DuetoscalingofMOSFETs,ithasbecomeverysignificanttoconsiderthe
effect of generated traps in SiSiO2 junction. The interface states although are not of
significance in case of thicker gate oxides but study of devices with tunneling oxide
thickness(~2nm)showsthatthesealmostnegligiblestateshaveremarkableimpacton
the drive current. As the oxide thickness is reduced these interfacetrapped charges
becomesignificantgradually.Inearliertimes,gateoxidethicknesswassolargethatthis
phenomenon was not noticeable, but introduction of nanotechnology puts a barrier in
determiningthenatureoftheMOSFETswithultrathinoxides.Asaresult,nowadayit
isamatterofimportancetoconsidertheinterfacestatesduringMOSoperation.
1.2Aglimpseofpreviousworksoninterfacetrappedcharges
A theoretical treatment on the process of hotelectron emission from silicon into SiO2
was carried out by Ning [1]. He considered avalanche and nonavalanche injection
mechanismtocalculateemissionprobabilityofthecarriersatSiSiO2 interface.Yambae
andMiura[2]observedexperimentallytheflatbandvoltageshiftduetothegenerationof
interface states because of electron trapping in the SiO2 film. They suggested that the
interface states, where electrons can be trapped, are generated due to the collisions of
electronsattheSiSiO2 interface.
Khosruandothers[3]observedthatholesarecreatedbyionizingradiationthatproduces
newelectronicstatesattheSiSiO2 interfaceresultingintheformationofinterfacetraps.
They alsofound a thresholdvoltage shiftdue tothetrappingof carriersinside the SiO2
layer.
Inarecentapproach,KueiShanWenandothers[4]showedthatthegeneratedelectron
traps at the SiSiO2 interface enhance the degradation of MOSFET characteristics. To
determine the interface trapped charges in a SiSiO2 interface Guido Goreseneken and
others [5] used the charge pumping method introduced by Brugler and Jespers [6] and
representedaverykeenanalysisofenergydistributionofinterfacetrappedcharges.
1.3Outlineofthereport
Inthisreport,werepresentedourworkinafewchapters.Thesechaptersareasfollows:
Chapter 2: In this chapter, the physics and operation of MOS devices

are studied in detail. Especially, the theory of MOS capacitor is
presented. The dependency of MOS capacitance on frequency and
applied voltage is also showed. A brief description on the MOSFET
operationisdiscussedintheend.
Chapter3:ThephysicalalphapowerlawMOSFETmodelisexplained
in detail in this chapter. The expressions of the model along with
compact mathematical analyses and plotsof IDS vs. VGS curves and IDS
vs.VDS curvesfortwodifferentdevices(3.5nmoxideand2.2nmoxide)
are presented. Discussing briefly about the plots, an outline of the
operationoftheultrathinoxideMOSFETsareunderstandable.Intheend
2
portion of this chapter an analysis of the subthreshold slope of the

devicesispresented.
Chapter 4: This chapter deals with the development of the physical

alphapower law MOSFET model. The incorporation of depletion
capacitance(Cd)andinterfacetrappedchargecapacitance(Cit)showsan
amount of difference in the IDS vs. VGS and IDS vs. VDS curves for both
thedevices.Respectiveplotsinthispurposeareincluded.
Chapter5: Adetaileddescriptiononthelocationandpropertiesof the

interface states in a MOS device is discussed here. Also, it includes a
glimpseintheSiSiO2 interface.
Chapter 6: This chapter deals with two types of determination process

of interface trapped charges: 1) The Charge Pumping Method or CP
Method, 2) The Capacitance Voltage Method or CV Method. Later in
this chapter an analytical study and comparison between this two
methodsispresented.
Chapter2
MOSDevicePhysicsandOperations
2.1Introduction
Afieldeffecttransistor(FET)operatesasaconductingsemiconductorchannelwithtwo
ohmiccontacts the source and the drain where thenumberof chargecarriersin the
channel is controlled by a third contact the gate. In the vertical direction, the gate
channelsubstratestructure(gatejunction)canberegardedasanorthogonaltwoterminal
device,whichiseitheraMOSstructureorareversebiasedrectifyingdevicethatcontrols
themobilechargeinthechannelbycapacitivecoupling(fieldeffect).ExamplesofFETs
basedontheseprinciplesareMetalOxideSemiconductorFET(MOSFET),junctionFET
(JFET),metalsemiconductor FET (MESFET),andheterostructureFET(HFETs). Inall
cases,thestationarygatechannelimpedanceisverylargeatnormaloperatingconditions.
ThebasicFETstructureisshownschematicallyinfigure2.1.
Figure2.1:Schematicillustrationofagenericfieldeffecttransistor
The most important FET is the MOSFET. In a silicon MOSFET, the gate contact is
separated from the channel by an insulating silicon dioxide (SiO2) layer. The charge
carriersoftheconductingchannelconstituteaninversioncharge,thatis,electronsinthe
caseof a ptypesubstrate (nchanneldevice) orholesin thecaseofan ntypesubstrate
(pchanneldevice),inducedinthesemiconductoratthesiliconinsulatorinterfacebythe
voltageappliedtothegateelectrode.Theelectronsenterandexitthechannelatn+ source
anddraincontactsinthecaseofannchannelMOSFET,andatp+contactsinthecaseof
apchannelMOSFET.
MOSFETsareusedbothasdiscretedevicesandasactiveelementsindigitalandanalog
monolithic integrated circuits (ICs). In past decade, the device feature size of such
circuitshasbeenscaleddownintothedeepsubmicrometerrange.Presently,the0.13mm
technology node for complementary MOSFET (CMOS) is used very large scale Ics.
(VLSIs) and, within a few years, sub0.1mm technology will be available, with a
commensurate increase in speed and in integration scale. Hundreds of millions of
transistorsonasinglechipareusedinmicroprocessorsandinmemoryICstoday.
CMOS technology combines both nchannel and pchannel MOSFETs to provide very
low power consumption along with high speed. New silicononinsulator (SOI)
technology may help achieve threedimensional integration, that is, packing of devices
intomany layers with adramatic increase in integration density. New improveddevice
structures and the combination of bipolar and fieldeffect technologies (BiCMOS) may
leadtofurtheradvances,yetunforeseen.OneoftherapidlygrowingareasofCMOSisin
analog circuits, spanning a variety of applications from audio circuits operating at the
kilohertz (kHz) range to modern wireless applications operating at gigahertz (GHz)
frequencies.
2.2TheMOSCapacitor
TounderstandtheMOSFET,itisconvenienttoanalyzetheMOScapacitorfirst,which
constitutes the important gatechannelsubstrate structure of the MOSFET. The MOS
capacitorisatwoterminalsemiconductordeviceofpracticalinterestinitsownright.As
indicated in figure 2.2, it consists of a metal contact separated from the semiconductor
substrate. Almostuniversally, the MOS structure utilizesdoped silicon as the substrate
and its native oxide, SiO2, as the insulator. In the siliconsilicon dioxide system, the
densityofsurfacestatesattheoxidesemiconductorinterfaceisverylowcomparedtothe
typicalchannelcarrierdensityinaMOSFET.Also,theinsulatingqualityoftheoxideis
quitegood.
Figure2.2:SchematicviewofaMOScapacitor
We assumethat the insulator layer hasinfiniteresistance, preventing any chargecarrier

transportacrossthedielectriclayerwhenabiasvoltageisappliedbetweenthemetaland
semiconductor. Instead, the applied voltage will induce charges and counter charges in
themetalandintheinterfacelayerofthesemiconductor,similartowhatisexpectedin
the metal plates of a conventional parallel plate capacitor. However, in the MOS
capacitor we may use the applied voltage to control the type of interface charge we
induceinthesemiconductormajoritycarriers,minoritycarriersanddepletionregion.
Indeed, the ability toinduceand modulateaconductingsheetofminoritycareers at the

semiconductor oxideinterfaceisthebasisoftheoperationoftheMOSFET.
2.2.1InterfaceCharge
Theinduced interface charge intheMOScapacitor isclosely linkedto theshapeof the
electronenergy bands of the semiconductor near the interface. At zero applied voltage,
the bending of the energy bands are ideally determined by the difference in the work
functions of the metal and the semiconductor. This band bending changes with the
applied bias and the bands become flat when we apply the socalled flatband voltage
givenby
VFB =(F m - F s ) / q = (F m - Xs - EC + EF )/q
(2.1)
where F m and FS are the work functions of the metal and the semiconductor,
respectively, XS is the electron affinity for the semiconductor, Ec is the energy of the
conduction band edge and EF is the Fermi level at zero applied voltage. The various
energies involved are indicated in figure 2.3, where we show typical band diagrams of
MOS capacitor at zero bias and with the voltage V=VFB applied to the metal contact
relativetothesemiconductoroxideinterface.
At stationary conditions, no net current flows in the direction perpendicular to the

interfaceowingtotheveryhighresistanceoftheinsulatorlayer.Hence,theFermilevel
will remain constant inside the semiconductor, independent of the biasing conditions.
However,betweenthesemiconductorandthemetalcontact,theFermilevelisshiftedby
EFM EFS = qV (see Figure 2.3(b)). Hence, we have a quasiequilibrium situation in
whichthesemiconductorcanbetreatedasifinthermalequilibrium.
A MOS structure with a ptype semiconductor will enter the accumulation regime of
operation when the voltage applied between the metal and the semiconductor is more
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negative than the flatband voltage (VFB < 0 in Figure 2.3). In theopposite case, when
V>VFB,thesemiconductoroxideinterfacefirstbecomesdepletedofholesandweenter
thesocalleddepletionregime.
Figure2.3:BanddiagramofMOScapacitor(a)atzerobiasand(b)withanapplied
voltageequaltotheflatbandvoltage.Theflatbandvoltageisnegativeinthis
example.
By increasing the applied voltage, the band bending becomes so large that the energy
difference between the Fermi level and the bottom of the conduction band at the
insulatorsemiconductorinterfacebecomessmallerthanthatbetweentheFermileveland
the top of the valance band. This is the case indicated for V = 0V in Figure 2.3 (a).
Carrier statistics tells us that the electron concentration then will exceed the hole
concentrationneartheinterfaceandweentertheinversionregime.Atstilllargerapplied
voltage, we finally arrive at a significant conducting sheet of inversion charge at the
interface.
Thesymbol y isusedtosignifythepotentialinthesemiconductormeasuredrelativeto
the potential at a position x deep inside the semiconductor. To note that y becomes
positivewhenthebandsbenddown,asintheexampleofaptypesemiconductorshown
inFigure2.4.
Figure2.4:BanddiagramforMOScapacitorinweakinversion(j b <y s <2j b)
from equilibrium statistics, we find that the intrinsic Fermi level Ei in the bulk
corresponds to an energy separation qjb from the actual Fermi level EF of the doped
semiconductor,
Na
n
i
jb =Vth ln
(2.2)
where Vth is the thermal voltage, Na is the shallow acceptor density in the ptype
semiconductor and ni is the intrinsic carrier density of silicon. According to the usual
definition, strong inversion is reached when the total band bending equals 2qjb,
correspondingtothesurfacepotential y s =2jb.Valuesofthesurfacepotentialsuchthat
0< y s <2jb correspondto thedepletionand the weakinversion regimes, y s =0 is the
flatbandcondition,and y s <0correspondstotheaccumulationmode.
Thesurface concentrations of holes and electrons are expressed in terms of the surface
potentialsasfollowsusingequilibriumstatistics,
p s = Na exp(- y s Vth )
(2.3)
n s=ni2 ps = np0 exp(ys Vth )
(2.4)
where np0 =ni2 Na istheequilibriumconcentrationoftheminoritycarriers(electrons)in

thebulk.
Thepotentialdistribution y (x)inthesemiconductorcanbedeterminedfromasolutionof
theonedimensionalPoissonsequation:
d 2y (x)
r ( x)
= 2
e s
dx
(2.5)
where es isthesemiconductorpermittivityandthespacechargedensity r(x)isgivenby
r(x ) = q(q- n- Na )
(2.6)
Thepositiondependentholeandelectronconcentrationsmaybeexpressedas
p = Na exp(- y Vth )
(2.7)
n =np0 exp(y Vth )
(2.8)
Itistobenotedthat,deepinsidethesemiconductor,wehave y(a) =0.
Ingeneral,theaboveequationsdonothaveananalyticalsolutionfor y(x). However,the

following expression can be derived for the electric field Fs at the insulator
semiconductorinterface,intermsofthesurfacepotential,
10
Fs = 2
Vth
LDp
y
f s
Vth
(2.9)
wherethefunction f isdefinedby
f(u) = [exp(- u) + u- 1] +
np0
Na
[exp(u) - u- 1]
(2.10)
and
LDp =
e sVth
(2.11)
qNa
is called the Debyelength. In(2.10),apositivesign shouldbechosenfora positive y s

andanegativesigncorrespondstoanegative y s.
Using Gauss law, we can relate the total charge Qs per unit area (carrier charge and
depletioncharge)inthesemiconductortothesurfaceelectricfieldby
Qs = -e sFs
(2.12)
Attheflatbandcondition(V=VFB),thesurfacechargeisequaltozero.Inaccumulation
(V < VFB ), the surface charge is positive, and in depletion and inversion (V>VFB), the
surface charge isnegative. In accumulation (when ys exceeds a few times Vth) and in
strong inversion, the mobile sheet charge density is proportional to exp[ys (2Vth )]. In
depletion and weak inversion, the depletion charge is dominant and its sheet density
variesasys .Figure1.5shows Qs versusy s forptypesiliconwithadopingdensityof
1016 cm3 .
InordertorelatethesemiconductorsurfacepotentialtotheappliedvoltageV,wehaveto
investigate how this voltage is divided between the insulator and the semiconductor.
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Using the condition of continuity of the electric flux density at the semiconductor
insulatorinterface,wefind
e sFs =e iFi
(2.13)
where ei isthepermittivityoftheoxidelayerand Fs istheconstantelectricfieldinthe

insulator(assumingnospacecharge).Hencewithaninsulatorthickness di ,thevoltage
dropacrosstheinsulatorbecomes Fidi.Accordingfortheflatbandvoltage,theapplied
voltagecanbewrittenas
V =VFB + y s + e sFs ci
(2.14)
where ci =e i di istheinsulatorcapacitanceperunitarea.
Figure2.5:Normalizedtotalsemiconductorchargeperunitareavs.normalized
surfacepotentialforptypeSiwithNa=1016/cm3
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2.2.2ThresholdVoltage
ThethresholdvoltageV=VT,correspondingtotheonsetofthestronginversion,isoneof
themostimportantparameterscharacterizingmetalinsulatorsemiconductordevices.As
discussedabove,stronginversionoccurswhenthesurfacepotential ys becomesequalto
2jb .Forthissurfacepotential,thechargeofthefreecarriersinducedattheinsulator
semiconductorinterfaceisstillsmallcomparedtothechargeinthedepletionlayer,which
isgivenby
QdT =-qNaddT = - 4esqNaj b
where
(4esj b
(2.15)
qN a ) isthewidthofthedepletionlayeratthreshold.Accordingly,the
1 2
electricfieldatthesemiconductorinsulatorinterfacebecomes
FsT =- QdT es = 4qNaj b /e s
(2.16)
Hence, substitutingthethreshold valuesof y s andFs in(2.14),weobtainthefollowing

expressionforthethresholdvoltage:
VT =VFB + 2jb + 4e sqNaj b ci
(2.17)
Figure 2.6 shows typical calculated dependencies of VT on doping level and dielectric
thickness.
For the MOS structure shownin figure 2.2, the application of a bulkbias VB is simply
equivalenttochangingtheappliedvoltagefromVtoVVB .Hence,thethresholdreferred
tothegroundpotentialissimplyshiftedbyVB.However,thesituationwillbedifferentin
aMOSFETwheretheconductinglayerofmobileelectronsmaybemaintainedatsome
13
Figure2.6:DependenceofMOSthresholdvoltageonthesubstratedopinglevelfor
differentthicknessofthedielectriclayer.
constantpotential.Assumingthattheinversionlayerisgrounded,VB biasestheeffective
junctionbetweentheinversionlayerandthesubstrate,changingtheamountofchargein
thedepletionlayer.Inthiscase,thethresholdvoltagebecomes
VT = VFB + 2jb + 2e sqNa(2j b - VB ) ci
(2.18)
Notethatthethresholdvoltagemayalsobeaffectedbysocalledfastsurfacestatesatthe
semiconductoroxideinterfaceandbyfixedchargesintheinsulatorlayer.However,this
isnotasignificantconcernwithmoderndayfabricationtechnology.
Asdiscussedabove, thethreshold voltage separatesthesubthreshold regime,where the

mobile carrier charge increases exponentially with increasing applied voltage, from the
abovethreshold regime, where the mobile carrier charge is linearly dependent on the
appliedvoltage.
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2.2.3MOSCapacitance
InaMOScapacitor,themetalcontactandtheneutralregioninthedopedsemiconductor
substrate are separated by the insulator layer, the channel, and the depletion region.
Hence, the capacitance Cmos of the MOS structure can be represented as a series
connection of the insulator capacitance C i = Se i di , where S is the area of the MOS
capacitor,andthecapacitanceoftheactivesemiconductorlayerC s,
CiCs
Ci + Cs
C mos =
(2.19)
Thesemiconductorcapacitancecanbecalculatedas
dQs
dy s
C s = S
(2.20)
where Qs is the total charge per unit area in the semiconductor and y s is the surface
potential.Using(2.9)to(2.12)forQ s andperformingthedifferentiation,weobtain
C s =
y s np0 y s
+
- 1
1- exp exp
V
N
V
2f(ys Vth )
th
a
th

Cs0
(2.21)
here, C s0 = Se s LDp isthesemiconductorcapacitanceattheflatbandcondition(i.e.,for
y s=0) and LDp is the Debye length given by (2.11), equation (2.14) describes the
relationshipbetweenthesurfaceandtheappliedbias.
The semiconductor capacitance can formally be represented as the sum of two

capacitances a depletion layer capacitance, Cd and a free carrier capacitance Cfc. Cfc
together with a series resistance RGR describes the delay caused by the
15
generation/recombinationmechanismsinthebuildupandremovalofinversionchargein
responsetochangesinthebiasvoltage.Thedepletionlayercapacitanceisgivenby
Cd = Se s / dd
(2.22)
2esy s
qNa
(2.23)
where
d d =
is the depletion layer width. In strong inversion, a change in the applied voltage will
primarily affect the minority carrier charge at the interface, owing to the strong
dependenceof thischargeon thesurfacepotential. This means that thedepletion width
reaches a maximum value with no significant further increase in the depletion charge.
This maximum depletion width ddT can be determined from (2.23) by applying the
threshold condition, y s= 2jb. the corresponding minimum value of the depletion
capacitanceisCdT =Ses/d dT.
Thefreecarriercontributiontothesemiconductorcapacitancecanbeformallyexpressed
as
Cfc =C s Cd
(2.24)
Asindicated,thevariationintheminoritycarrierchargeattheinterfacecomesfromthe
processesofgenerationandrecombinationmechanisms,withthecreationandremovalof
electronholepairs.Onceanelectronholepairisgenerated,themajoritycarrier(aholein
ptypematerialandanelectroninntypematerial)issweptfromthespacechargeregion
intothesubstratebytheelectricfieldofthisregion.Theminoritycarrierissweptinthe
oppositedirectiontowardsemiconductorinsulatorinterface.Thevariationintheminority
carrierchargeinthesemiconductorinsulatorinterfacethereforeproceedsataratelimited
bythetimeconstantsassociatedwiththegeneration/recombinationprocesses.Thisfinite
16
raterepresentsadelay,whichmayberepresentedelectricallyintermsofanRCproduct
consisting of the capacitance Cfc and the resistance RGR, as reflected in the equivalent
circuitoftheMOSstructureshowninfigure2.7.ThecapacitanceCfc becomesimportant
in the inversion regime, especially in strong inversion where the mobile charge is
important.TheresistanceRs intheequivalentcircuitistheseriesresistanceoftheneutral
semiconductorlayerandthecontacts.
Figure2.7:EquivalentcircuitoftheMOScapacitor
Thisequivalentcircuitisclearlyfrequencydependent.Inthelowfrequencylimit,wecan
neglecttheeffectsofRGR andRs toobtain(usingCs =Cd+Cfc)
o
C mos
=
CsCi
Cs + Ci
(2.25)
Instronginversion,wehaveCs >>Ci,whichgives
o
C mos
=Ci
(2.26)
atlowfrequencies.
In the highfrequency limit, the time constant of the generation/recombination

mechanismswillbemuchlongerthanthesignalperiod(RGRCfc >>1/f)andCdeffectively
17
shuntsthelowerbranchoftheparallelsectionoftheequivalentinfigure2.7.Hence,the
highfrequency,stronginversioncapacitanceoftheequivalentcircuitbecomes
C mos
=
CdTCi
CdT + Ci
(2.27)
The calculated dependence of C mos on the applied voltage for different frequencies is
shown in figure 2.8. For applied voltages well below threshold, the device is in
accumulationandCmos equalsCi.Asthevoltageapproachesthreshold,thesemiconductor
passestheflatbandconditionwhereCmos hasthevalueCFB,andthenentersthedepletion
and weak inversion regimes where the depletion width increases and the capacitance
valuedropssteadilyuntilitreachestheminimumvalueatthresholdgivenby(2.27).The
calculatedcurvesclearlydemonstratehowtheMOS capacitancein thestrong inversion
regime depends onthe frequency, with a value of Cmos

at high frequencies toCi at low
frequencies.
Figure2.8:CalculateddependenceofCmos ontheappliedvoltagefordifferent
frequencies.
We note that in a MOSFET, where the highly doped source and drain regions act as
reservoirsof minority carriers fortheinversion layer,thetimeconstantRGRCfc mustbe
18
substituted by a much smaller time constant corresponding to the time needed for
transporting carriers from these reservoirs in and out of the MOSFET gate area.
Consequently, highfrequency strong inversion MOSFET gatechannel CV
characteristicswillresemblethezerofrequencyMOScharacteristics.
Since the lowfrequency MOS capacitance in the strong inversion is close to Ci, the
inducedinversionchargeperunitareacanbeapproximatedby
qn s ci(V - VT )
(2.28)
Thisequationservesasthebasisofasimplechargecontrolmodel(SCCM)allowingus
tocalculateMOSFETcurrentvoltagecharacteristicsinstronginversion.
FrommeasuredMOSCVcharacteristics,wecaneasilydetermineimportantparameters
oftheMOSstructure,includingthegateinsulatorthickness,thesemiconductorsubstrate
doping density, and the flatband voltage. The maximum measured capacitance C max
(capacitanceCi infigure2.7)yieldstheinsulatorthickness
di Se i Cmax
(2.29)
TheminimummeasuredcapacitanceCmin (athighfrequency)allowsustofindthedoping
concentration in the semiconductor substrate. First, we determine the depletion
capacitanceinthestronginversionregimeusing(2.27),
1 Cmin =1CdT + 1Ci
(2.30)
FromCdT weobtainthethicknessofthedepletionregionatthresholdas
d dT = Se s CdT
(2.31)
19
ThenwecalculatethedopingdensityNa using(2.23)with y s=2jb and(2.2)for jb.this

resultsinthefollowingtranscendentalequationforNa:
Na =
4esVth Na
ln
2
qddT
ni
(2.32)
Thisequationcaneasilybesolvedbyiterationorbyapproximateanalyticaltechniques.
Once d i and Na have been obtained, the device capacitance CFB under flatband
conditions can be determined using Cs = C s0 ((2.21) at flatband condition) in
combinationwith(2.19):
C FB =
Cs0Ci
Se se i
=
Cs0 + Ci e sdi + e iLDp
(2.33)
The flatband voltage VFB is simply equal to the applied voltage corresponding to this
valueofthedevicecapacitance.
We note that the above characterization technique applies to ideal MOS structures.
Different nonideal effects, such as geometrical effects, nonuniform doping in the
substrate, interface states, and mobile charges in the oxide may influence the CV
characteristicsoftheMOScapacitor.
2.2.4MOSChargeControlModel
Wellabovethreshold,thechargedensityofthemobilecarriersintheinversionlayercan
becalculatedusingtheparallelplatechargecontrolmodelof(2.28).Thismodelgivesan
adequatedescriptionforthestrong inversionregimeof theMOScapacitor,butfails for
applied voltages near and below threshold (i.e. in the weak inversion and depletion
regimes). Several expressions have been proposed for a unified charge control model
(UCCM)thatcoversalltheregimesofoperation,includingthefollowing:
20
n
V -VT = q(ns - n0) ca + hVth ln s
n0
(2.34)
where, c a ci is approximately the insulator capacitance per unit area (with a small
correctionforthefinite verticalextent ofthe inversion channel),n0 =ns(V =VT)is the
densityofminoritycarriersperunitareaatthreshold,and histhesocalledsubthreshold
ideality factor, also known as the subthreshold swing parameter. The ideality factor
accounts for thesubthresholddivisionoftheapplied voltagebetweenthegate insulator
andthedepletionlayer,andthe1/hrepresentsthefractionofthisvoltagethatcontributes
totheinterfacepotential.Asimplifiedanalysisgives
h = 1 + C d Ci
(2.35)
n0 =hVthca 2q
(2.36)
Inthesubthresholdregime,(2.34)approachesthelimit
V - VT
n s =n0 exp
h
V
th
(2.37)
Wenotethat(2.34)doesnothaveanexactanalyticalsolutionfortheinversionchargein
terms of the applied voltage. However, for many purposes, the following approximate
solutionmaybesuitable:
1 V - VT
n s =2n0 ln1+ exp

2 hVth
(2.38)
21
Figure2.9:ComparisonofvariouschargecontrolexpressionfortheMOS
capacitor.
This expression reproduces the correct limiting behaviour both in strong inversion and
the subthreshold regime, although it deviates slightly from (2.34) near threshold. The
various charge control expressions of the MOS capacitor are compared in the above
figure.
2.3BasicMOSFETOperation
In the MOSFET, an inversion layer at the semiconductoroxide interface acts as a

conducting channel. For example, in an nchannel MOSFET, the substrate is ptype
silicon and the inversion charge consists of electrons that form a conducting channel
between the n+ ohmic source and the drain contacts. At DC conditions, the depletion
regions and the neutral substrate provide isolation between devices fabricated on the
samesubstrate.AschematicviewofthenchannelMOSFETisshowninFigure2.10.
22
As described above for the MOS capacitor, inversion charge can be induced in the
channel by applying a suitable gate voltage relative to other terminals. The onset of
stronginversion isdefined intermsof athreshold voltage VT beingapplied tothegate
electrode relative to the other terminals. In order to assure that the induced inversion
channelextends all the way from source to drain, it is essential that the MOSFET gate
structure eitheroverlapsslightly oraligns with the edgesof thesecontacts (thelatter is
achieved by a selfalignedprocess). Selfalignment ispreferablesince it minimizes the
parasiticgatesourceandgatedraincapacitance.
Figure2.10:Schematicviewofan nchannelMOSFETwithconductingchanneland
depletionregion
WhenadrainsourcebiasVDS isappliedtoannchannelMOSFETintheabovethreshold
conducting state,electronsmove inthechannel inversionlayer from source todrain. A
change in the gatesource voltage VGS alters the electron sheet density in the channel,
modulating the channel conductance and the device current. For VGS > VT in an n
channel device, an application of a positive VDS gives a steady voltage increase from
sourcetodrainalongthechannelthatcausesacorrespondingreductioninthelocalgate
channel bias VGX (here X signifies a position x within the channel). This reduction is
greatestneardrainwhereVGX equalsthegatedrainbiasVGD.
23
Somewhatsimplistically,wemaysaythatwhenVGD =VT,thechannelreachesthreshold
atthedrainandthedensityofinversionchargevanishesatthispoint.Thisisthesocalled
pinchoff condition, which leads to a saturation of the drain current Ids. The
corresponding drainsource voltage, VDS = VSAT , iscalled the saturation voltage. Since
VGD =VGS VDS,wefindthatVSAT =VGSVT .
When VDS > VSAT, the pinchedoff region near drain expands only slightly in the
direction of the source, leaving the remaining inversion channel intact. The point of
transition between the two regions, x = x p, is characterized by V XS (xp )VSAT , where
VXS (xp ) isthechannelvoltagerelativetosourceatthetransitionpoint.Hence,thedrain
current in saturation remains approximately constant, given by the voltage drop VSAT
acrossthepart ofthe channelthat remainsin inversion.ThevoltageVDS VSAT across
the pinchedoff region creates a strong electric field, which efficiently transports the
electronsfromthestronglyinvertedregiontothedrain.
Typical currentvoltage characteristics of a longchannel MOSFET, where pinchoff is

thepredominantsaturationmechanism,areshowninthefollowingfigure.
Figure2.11:Currentvoltagecharacteristicsofan nchannelMOSFETwithcurrent
saturationcausedbypinchoff(longchannelcase)
24
However, with shorter MOSFET gate lengths, typically n the submicrometer range,
velocity saturation will occur in the channel near drain at lower VDS than that causing
pinchoff.Thisleadstomoreevenlyspacedsaturationcharacteristicsthanthoseshownin
thisfigure,moreinagreementwiththoseobservedformoderndevices.Also,phenomena
such as a finite channel conductance in saturation, a drain biasinduced shift in the
threshold voltage, and an increased subthreshold current are important consequencesof
shortergatelengths.
25
Chapter3
ThePhysicalAlphaPowerLawMOSFETModel
3.1Introduction
In1999,theproposalofthephysicalalphapowerlawMOSFETmodel[8]eliminatedthe
drawbacksofthepreviouslywidelyutilizedalphapowerlawMOSFETmodel[9].Inthis
regard, it included thehelpful features of the low power transregional MOSFET model
[10].Theadditionofthelowpowertransregionalmodelbringsinthesalientfeaturesof
operationinalltheregions(subthreshold,triodeandsaturation).Tomentionthatthelow
powertransregionalmodel[10]wasanadvantageouschoiceforpredictingperformance
of future technology generations and in particular for analyzing on/off drain current
tradeoffs. Due to the complex drain current equations the involvement with the alpha
powerlawMOSFETmodelbroughtthephysicalalphapowerlawMOSFETmodel.This
model included these salient features: 1) extension into the subthreshold region of
operation, 2) the effects of vertical and lateral high field mobility degradation and
velocitysaturationand3)thresholdrolloff.
3.2ModelDerivation
The physical alphapower law MOSFET model was derived by coupling the simple
empiricalalphapowerlawMOSFETmodel[9]andthemorecomplexphysicsbasedlow
power transregional MOSFET model [10]. The derivation of the model started by
equating the saturation drain current of the alphapower law MOSFET model [9],
equation(3.1)andthelowpowertransregionalmodel[10],equation(3.2)
26
V - VT
= IDSAT
I D0 GS
VDD - VT
(3.1)
WhereID0 (3.5)isamodifieddrivecurrentthatincludesaneffectivemobilitydependence
on VGS. Neglecting the small weak inversion contribution and performing a three term
binomial expansion of the bulk charge terms inIDSAT , the low power transregional
modelssaturationdraincurrent[10]wassimplifiedas
( )
I DSAT W COX m effVDSSAT VGS -VT - (h /2)VDSSAT

L
(3.2)
Where, (W/L) is thechannel widthtolengthratio, Cox istheoxidecapacitanceperunit

area, meff is the effective mobility. meff depends on the gate bias voltage (VGS) as the
influenceofgatebiasisdominantintheexpressionof meff.Ratherwecansayforamore
accurateexpression that meff dependson thetransverse field, which, inturn,dependson
allterminalvoltages[11].Ageneralexpressionof meff isgivenasfollows:
m eff =
m 0
(3.3)
1+ q (VGS - VT )+ q BVSB
Includingthevertical[12]andlateral[13]highfielddegradationeffects,theexpression
of meff provedtobe:
meff =
m0
[1+ q (VGS - VT )][1+ VDS /(ECL)]
(3.4)
SAT
Andthesaturationvoltageisgivenbythefollowingequation:
2 VGS - VT
VDSSAT = ECL 1 +
- 1
ECL
h
27
(3.5)
Thecombinationofequation(3.1)and(3.2),forVGS=VDD,obtains,
I D0 =(W L)COX m effVD0[VDD - VT - (h 2)VD0]
Where, V D0 =VDSSAT
(3.6)
(3.7)
VGS =VDD
From(3.1),
a
VGS - VT
I
= DSAT
ID0
VDD - VT
(3.8)
Fromtheaboveequationthevalueof a atVGS isobtained.Theexpressioncomesoutto

be,
a V
GS
VDSSAT VGS - VT - (h 2)VDSSAT

ln
VD0 [VDD - VT - (h 2)VD0]
=
V - VT
ln GS
V
V
DD T
(3.9)
The above equation expresses theparameter, a, as a function of VGS. A simplified and

accurate expression of a is determined by selecting VGS equal to the middle value
between the end points (VDD,VT ) such that VGS=(VDD+VT)/2. Substituting
VGS=(VDD+VT)/2intoequation(3.9),
a =
2V [V - V - (h 2)VD0]
1
ln D0 DD T
ln(2) VDa[VDD - VT - hVDa ]
Where, V Da =VDSSAT
(3.10)
(3.11)
VGS = (VDD +VT )/2
28
AfeatureofthephysicalalphapowerlawMOSFETmodeldescribesthatdependenceof
carrier velocity on VGS is jointly described by ID0, (3.3)(3.6), as well as a (3.10).This
yieldsimprovedaccuracyofthemodelforVGS nearVT comparedtotheoriginalalpha
powerlawmodel[8]thatdescribescarriervelocityasafunctionofVGS solelythrough a.
Therefore, the valuesof a calculatedby thephysical alphapowerlawmodelreslightly
larger than the measured a values of the original alphapower law model [8] for short
channelMOSFETs.
For further insight into the a parameter, analyses of the long channel MOSFET with
negligiblecarriervelocitysaturation(ECL>>VDD VT)andtheshortchannelMOSFET
withseverecarriervelocitysaturation(ECL<<VDD VT)areperformedinthemodel.In
thelongchannelcase,thesaturationvoltage(3.4)maybesimplifiedbyperformingatwo
termbinomialexpansionsuchthat
VDSSAT
ECL>>VGS -VT
(1h)(VGS - VT )
(3.12)
Substituting(3.12)into(3.10)gives
a E
CL>>VDD -VT
ln(4)
= 2
ln(2)
(3.13)
Thus,forlongchannelMOSFETswithnegligiblecarriervelocitysaturationtheexponent
aconvergestothevaluefortheclassicalShockleysquarelawMOSFETmodel[12].For
the short channelMOSFET with VGS sufficiently larger than VT, the saturation voltage
(3.4)maybesimplifiedas
VDSSAT
ECL<<VGS -VT
(2ECL/h)(VGS - VT )
29
(3.14)
Substituting(3.14)into(3.10)gives
a E
CL<<VDD -VT
1
3 2
ln(2) = 3 2
ln(2)
(3.15)
Substituting (3.14) and (3.15) as well as (3.3)(3.6) into the expression for saturation
draincurrent(3.1)gives
IDSAT
ECL<<VDD -VT
WCOX (VGS - VT )u sat
(3.16)
where usat is thesaturation velocity. Thus, for the short channel MOSFET withsevere
carrier velocity saturation thedraincurrent in the saturation region approaches a linear
dependenceofVGS VT [8].
30
3.3Representationofthemodel
3.4Simulations
WehavechosentwoMOSdevicesofultrathinoxides:1)a3.5nmdeviceand2)a2.2nm
device. For both the devices we simulated the IV characteristics plots in all the three
operating regions. We consideredthe3.5 nm device as the first sample and the 2.2 nm
deviceasthesecondsample.Weranthesimulationsonboththedevicesunderacommon
ambienttemperaturewhichisofthevalueT=20oC(293K).
31
3.4.1IDS vs. VGS curve:

While determining the IDS VGS curves we considered the constant drain to source
DrainCurrent,IDS (A)
voltage,VDS =50mV.
0.1
0.01
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1E10
1E11
1E12
1E13
1E14
1E15
1E16
1E17
3.5nm
2.2nm
o
T=20C
VDS =0.05Volt
0.0
0.5
1.0
1.5
2.0
GatetoSourceVoltage,VGS (Volt)
Figure3.1:IDS vs. VGS curvefor3.5nmdevice(hollowcircle)and2.2nmdevice
(hollowuptriangle)
32
3.4.2IDS vs. VDS curve:

IncaseofdeterminingthenatureoftheIDS VDS curvesthegatetosourcevoltage,VGS
was kept constant for a full operating rangeof drain to source voltage. We have taken
four distinct values of gate to source voltage for the determination of IDS VDS curve.
Theseare:0.8volt,1volt,1.5volt&2volt.
3.4.2.1IDS vs. VDS curve(VGS =0.8volt):
1E3
3.5nm
2.2nm
o
T=20C
VGS =0.8Volt
1E4
0.0
0.5
1.0
1.5
2.0
DraintoSourceVoltage,VDS (Volt)
Figure3.2:IDS vs. VDS curvefor3.5nmdevice(hollowcircle)and2.2nmdevice
(hollowuptriangle)with0.8voltgatebias
33
3.4.2.2IDS vs. VDS curve(VGS =1volt):
0.01
3.5nm
2.2nm
o
T=20C
VGS =1Volt
1E3
0.0
0.5
1.0
1.5
2.0
(hollowuptriangle)with1voltgatebias
34
0.1
0.01
3.5nm
2.2nm
o
T=20C
VGS =1.5Volt
1E3
0.0
0.5
1.0
1.5
2.0
(hollowuptriangle)with1.5voltgatebias
35
0.1
3.5nm
2.2nm
o
T=20C
VGS =2Volt
0.01
0.0
0.5
1.0
1.5
2.0
(hollowuptriangle)with2voltgatebias
As we see, from the mathematical representation of the alpha powerlaw MOSFET

model, the active region current and the saturation region current in IDS vs. VDS curves
andthesubthresholdregioncurrentandtheactiveregioncurrentintheIDS vs.VGS curve
are linearly proportional to the determinedoxide capacitance of the respectivedevices.
So, the amount of current decreases with the increase of oxide thickness as oxide
capacitanceisinverselyproportionaltotheoxidethickness.
Also,theamountofaccessofboththedevicesintheactiveregionincaseofIDS vs.VDS
curvesincreasewiththeincrementofappliedgatebiasvoltages.Similarly,theincrement
36
ofthegatevoltageincreasesalsoincreasesthevalueoftheoutputcurrentIDS (Seefigure
3.2,3.3,3.4&3.5).
3.4.3Subthresholdslope
From the representation of the model, we find that, subthreshold current IDSSUB depends
exponentially on gate bias voltage VGS. However, VDS has little influence once VDS
exceedsafew b =
kT
.Obviously,wefindalinearbehaviourinthesubthresholdregime
q
from figure 3.1 when we plot IDS VGS. The slope of this line (or more precisely the
reciprocaloftheslope)isknownasthesubthresholdslope,S,whichhastypicalvalueof
~70 mV/decade at room temperature for stateoftheart MOSFETs. This means that a
changeintheinputVGS of70mVwillchangetheoutputIDS byanorderofmagnitude.
Clearly,thesmallerthevalueofS,thebetterthetransistorisasaswitch.Asmallvalue
ofSmeansasmallchangeintheinputbiascanmodulatetheoutputcurrentconsiderably.
ItcanbeshownthatSisexpressedby
S =
dVGS
dVGS
kT C + Cit
= ln10
= 2.3 1+ d
d(logIDS )
d(logIDS )
q
Cox
(3.17)
Theelaboratedexpressiongivesusanideaofrepresentingtheelectricalequivalentcircuit
oftheMOSFETintermsofcapacitors.Theexpressioninbracketsintheaboveequation
is simply thecapacitor divider ratio thattells what the fraction of the applied gatebias
appears at the Si SiO2 interface as the surface potential. Ultimately it is the surface
potentialthatisresponsibleformodulatingthebarrierbetweenthesourceanddrain,and
thereforethedraincurrent,IDS.Hence,Sisameasureoftheefficacyofthegatepotential
inmodulatingIDS.Fromequation(3.17)wefindthatSisimprovedbyreducingthegate
oxidethickness,whichisreasonablebecauseifthegateelectrodeisclosertothechannel,
the gatecontrol is obviously better. The valueof S is higher for heavy channel doping
(which increases thedepletion capacitance) orif the silicon oxideinterfacehas many
37
fast interface states. In our observations, we obtained the value of S to be 59.9

mV/decadefor3.5nmdevicesand59.4mV/decadefor2.2nmdevices.So,wefindthat
thedecrementoftheoxidethicknessresultsinabetterresponsiveMOSFETasaswitch.
38
Chapter4
ModificationofThePhysicalAlphaPowerLaw
MOSFETModel
4.1Introduction
ThemodificationsofthephysicalalphapowerlawMOSFETmodelwasobviousdueto
theincorporationofthefastinterfacestatesinthemodel.Although,themodelwasquite
right in its manners to determine the MOS characteristics, the interface capacitance
determinesthecurrentresponseinaquiterealisticmanner.
4.2Interfacetrappedcharges
A detailed study of the MOS interfacestates ispresentedinchapter5in the following.

Butfortheconvenienceofourdiscussionwewouldliketohaveabirdseyeviewonit.
Generally, an interfacetrapped charge (also called fast interfacestate charge) exists at
theoxidesemiconductorinterface.Itiscausedbythedefectsattheinterface,whichgives
risetochargetrapsthesecanexchangemobilecarrierswiththesemiconductor,acting
asdonorsoracceptors[14].Theinterfacetrappedchargesareverynegligibleineffectin
caseofstronginversionbutifweconsiderthecaseofverythingateoxidesthenwefind
thetrappedchargesplayingavitalroleincaseofdeterminingMOScapacitance.
39
TheenergybanddiagramforaMOSstructureatpositivevoltageisasfollows:
Figure4.1:EnergybanddiagramofaMOSstructure.
From the above figure, we see the existence of interface trapped charges in the oxide
regionof theMOSFET.Usually incaseofsignificantly thick gateoxidesthesecharges
arenotofanysignificanceincalculatingtheMOScapacitance.But,aswesee,whenthe
oxide thickness is very thin then these charges existing near to the edge of the oxide
surface strongly take part during the application of electric field [5]. So, we see that
negligence abouttheexistenceofthesecharges isnotquite always righttodetermine a
bettercurrentresponsefromaMOSFEToperation.
4.3Modificationofthealphapowerlawmodel
Our study of the physical alphapower law MOSFET Model includes a modification
aboutMOScapacitance.Inthesubthresholdregion,theeffectsofdepletioncapacitance
and capacitance due to interface trapped charges are not included. As a consequence
revisedmodelispresentedwiththeemploymentofinterfacetrappedchargecapacitance
40
(Cit) and depletion capacitance (Cd). The revised model includes the arrangement of
capacitancesinthefollowingmanner[15]:
Figure4.2:ArrangementofcapacitancesinaMOStransistor
Nowitcomestoapointofdeterminingthedifferentcomponentsofthetotalcapacitance
(C). Oxide capacitance is varied from the flatband capacitance (CFB) to the intrinsic
valueoftheoxidecapacitance(ei/tox).Theflatbandcapacitanceisaseriescombination
ofDebye capacitance (Cdebye) andinsulator capacitance(Ci) [15]. It isassumedthat the
oxidecapacitance(Cox)varieslinearlywiththeapplicationofthegatebiasvoltage(VGS).
In our proposal we determine the gate to substrate voltage (VGS) or the gatebias from
surfacepotentials(fs)bythefollowingequation[14]:
VGS =VFB + fs + g f s + f t exp((f s - 2f F ) /f t )
(4.1)
Depletion capacitance (Cd) is determined by calculating depletion width (Wm) that is

directlyproportionaltothesquarerootofthesurfacepotential(fs)[3]:
2e f 2
e
Wm = s s Cd = s
Wm
qNa
(4.2)
41
Then we analyzed the interface trap distribution and measured its value to be equal to
65.771nF(SeeChapter5fordetail).Thuswetakeinterfacetrappedchargecapacitance,
Cit =65.771nF.Thenfollowingthecapacitorarrangementoffigure4.2wemeasuredthe
equivalentMOScapacitance(Cmos).ThecalculatedvalueoftheCmos isthenusedinthe
expressionsof the variousexpressions of physicalalphapower law MOSFET modelin
placesofCox.Andthusweobtainedaquiteremarkabledeviationinthemeasuredvalues
ofthedraincurrent,IDS.
4.4Revisedsimulations
Weusedthesamedevicesuseinchapter3(3.5nmoxideand2.2nmoxide)withsimilar
ambient conditions and performed the revised expressions for the operations and then
compared the obtained results with that obtained through the simulations of physical
alphapowerlawMOSFETmodel.
42
4.4.1IDS vs. VGS curve:

a) For3.5nmdevice
0.01
1E3
1E4
1E5
1E6
1E7
1E8
1E9
AlphaModel
RevisedModel
1E10
1E11
1E12
T=20C
VDS =50mV
tOX=3.5nm
1E13
1E14
1E15
1E16
1E17
0.0
0.5
1.0
1.5
Figure4.3:IDS vs.VGS curvefor3.5nmdevice
43
2.0
b) For2.2nmdevice
0.01
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1E10
AlphaModel
RevisedModel
1E11
1E12
1E13
T=20C
VDS =50mV
tOX=2.2nm
1E14
1E15
1E16
1E17
0.0
0.5
1.0
1.5
2.0
Figure4.4:IDS vs.VGS curvefor2.2nmdevice
Studying the IDS vs. VGS curves, we find a good impact of the newly engaged trapped
chargesanddepletioncapacitance.Forbothofthespecimens,theproposedmodelshows
lowervaluesattheinitialpointsofthesubthresholdregion.Intheinitialregion,physical
alphapower law MOSFET model shows a quite constant rise in the values of drain
current, where the proposed model shows a slightly curved rise in the values of drain
current. This may be taken as an effect of the appearance of the newly introduced
capacitances that are varied with the applied gate bias. These plots show that the
subthresholdslopeforproposedmodelshowsahighervalue(63.5mV/decade)thanthe
alphapowerlawMOSFETmodel(59.9mV/decade)incaseof3.5nmoxide.Similarly,
44
revisedmodelshowsahighervalue(62.4mV/decade)incaseof2.2nmdevicesthanthe
previousmodel(59.4mV/decade).
4.4.2IDS vs. VDS curve:

TheIDS vs.VDS curvesalsoshowaslightlyreducedamountofcurrentwhendevicesare
operatedunderfixedgatebiasvoltage,VGS.
1E3
AlphaModel
RevisedModel
1E4
T=20C
VGS =0.8V
tOX =3.5nm
1E5
0.0
0.5
1.0
1.5
Figure4.5:IDS vs. VDS curvefor3.5nmdevice(VGS =0.8volt)
45
2.0
1E3
AlphaModel
RevisedModel
1E4
T=20C
VGS =0.8V
tOX=2.2nm
1E5
0.0
0.5
1.0
1.5
46
2.0
0.01
AlphaModel
RevisedModel
1E3
o
T=20C
VGS =1V
tOX=3.5nm
1E4
0.0
0.5
1.0
1.5
Figure4.7:IDS vs.VDS curvefor3.5nmdevice(VGS =1volt)
47
2.0
0.01
AlphaModel
RevisedModel
1E3
T=20C
VGS =1V
tOX=2.2nm
1E4
0.0
0.5
1.0
1.5
Figure4.8:IDS vs.VDS curvefor2.2nmdevice(VGS =1volt)
48
2.0
AlphaModel
RevisedModel
0.01
T=20C
VGS =1.5V
tOX=3.5nm
1E3
1E4
0.0
0.5
1.0
1.5
49
2.0
0.1
AlphaModel
RevisedModel
0.01
T=20C
VGS =1.5V
tOX=2.2nm
1E3
1E4
0.0
0.5
1.0
1.5
50
2.0
0.1
AlphaModel
RevisedModel
0.01
T=20C
VGS =2V
tOX=3.5nm
1E3
1E4
0.0
0.5
1.0
1.5
Figure4.11:IDS vs. VDS curvefor3.5nmdevice(VGS =2volt)
51
2.0
0.1
AlphaModel
RevisedModel
0.01
T=20C
VGS =2V
tOX=2.2nm
1E3
0.0
0.5
1.0
1.5
2.0
Figure4.12:IDS vs. VDS curvefor2.2nmdevice(VGS =2volt)
AlltheaboveIDS vs.VDS curvesshowagoodadjustmentwiththecalculatedcapacitance
for the MOS devices model. As we have proceeded with the combination of the
capacitances, we obtained a decrement by an order of 10 in the value of the total
capacitancetothatofthecapacitanceusedinthealphapowerlawMOSFETmodel.All
the plots here show same amount of decrement in drain current value than that of the
alphamodel.
52
Chapter5
InterfaceStatesinMOSFETs
5.1Introduction
TheSiSiO2 interfaceistheonlyknowninterfacethatisgoodenoughtoenableoperation
of MOSFETs to industrial standards. Thus, the properties of silicon dioxide are
fundamentaltothesuccessofsiliconintegratedcircuittechnologies[16].
5.2PropertiesofSiSiO2 interface
Althoughtheoxideisnotacrystal,thesiliconandoxygenatomsarepackedinanorderly
manner, each silicon atom is bonded to four oxygen atoms and each oxygen atom is
bondedtotwosiliconatoms[16].
As the average distance between the oxygen atoms is larger than the average distance
betweenthesiliconatomsinthesilicon,thismeansthatsomeoftheinterfaceatomsfrom
thesiliconwillinevitablymissoxygenatomstocreateSiObonds.Thisisalsoknownas
dangling bond[16].
Atoms from the silicon that remain bonded only to three silicon atoms with the fourth
bond unsaturated, represents interface defects. The energy levels associated with the
fourthunsaturatedbondofthetrivalentsiliconatomsdonotappearintheconductionor
thevalanceband,ratherinthesiliconenergybandgap[16].
53
Everytrivalentsiliconatomintroducesapairofenergylevelsonecanbeoccupiedbyan
electron (acceptor type) and the other can be occupied by a hole (donor type) [17].
Electronsandholesthatappearontheselevelscannotmovefreelyasthereisarelatively
large distance between the neighbouring interfacial trivalent silicon atoms (these levels
arelocalizedandisolatedfromeachother)[16,17].
Astheselevelscan effectivelytrapthemobileelectronsandholes(fromtheconduction
and valence bands respectively), these are called interface states. Impurity atoms and
groups(suchasH,OHandN)canbebondedtotheunsaturatedbondsoftheinterfacial
trivalentsiliconatoms,whichresultinashiftofthecorrespondingenergylevelsintothe
conduction andvalenceband.Although thisprocesseffectively neutralizes the interface
states,itisnotpossibletoenforcesuchasaturationofalltheinterfacialtrivalentatoms,
whichmeansthatthedensityoftheinterfacestatescanneverbereducestozero[17].
5.3Propertiesofinterfacestates
Generallytherearetwotypesofinterfacestates,theacceptortypeandthedonortype.An
acceptor type interface state is electrically neutral when it is empty and negatively
chargedwhenfilledwithanelectron[16,18].
A donor type interface state is electrically neutral when it is filled with electron and
positivelychargedwhenempty[18].
Besidesbeingdonororacceptor,aparticularinterfacestateisalsocharacterizedby
1) Itspreciseenergylevelinthebandgap(eg:eVfromthevalencebandedge)
2) Itsspatiallocation(eg:distancefromthedrain)
3) Itsdensity(eg:numberofstatespercm2 fordiscretestates)
In MOSFETs, these interface states are also caused by hot carrier impacting on the
surface. Interface states are known to cause degradation in device parameters such as
54
transconductance, carrier mobility and threshold voltage and generally reduce device
reliabilityandlifetime[17,18and19].
5.4Locationofinterfacetraps
Figure5.1:LocationofInterfaceStatesinMOSFETs
InterfacestatesarelocatedattheSiSiO2 layerwhichseparatesthegatecontactfromthe
conducting channel, which is underneath the gate and between the source and drain
region.
5.5Energydistributionoftheinterfacestates
ThenetchargeintheinterfacestatesisafunctionofthepositionoftheFermilevelinthe
bandgap[18].
Theenergyor band gapof silicon is1.12 eV andgenerally, acceptor statesexistin the

upperhalfofthebandgapanddonorstatesexistinthelowerhalfofthebandgap[18].
55
An acceptor type interface state is neutral if the Fermi level is below the state and
becomesnegativelychargediftheFermilevelisabovethestate[18].
AdonortypeinterfacestateisneutraliftheFermilevelisabovethestateandbecomes
positivelychargedistheFermilevelisbelowthestate[18].
AccordingtothejournalbyDuval,byusinghightemperatureconductancespectroscopy,
the Fermi level of the acceptor type interface states was found tobe 0.4 eVbelow the
conductionbandofthesilicon,whilethedonortypeinterfacestatesis0.38eVabovethe
valenceband[20].
Figure5.2:Energydistributionoftheinterfacestates[20]
56
5.6ChangesinOccupancyandChargeStatewithGateBias
Thissection willillustratethechange inoccupancyandcharge statewithdifferentgate

bias voltage. For this section we apply a small DrainSource Voltage (VDS) of 0.1 volt
andgroundthesourceterminal.
5.6.1Accumulation
When the gate voltage, VG is less than zero, the MOSFET is said to operate in the
Accumulationmode.HolesaredrawntotheSiSiO2 interfaceandnoelectronflowsfrom
sourcetodrain[8].
DonortypeinterfacestatesthatareaboveFermilevelofthesilicon,EFS,willbeemptyof
electrons and become positively charged, while those that are below E FS will be filled
withelectronsandbeneutral[18].
Acceptor type interface states will be above EFS and be empty of electrons thus being
neutral[18].
Figure5.3:Energybanddiagraminaptypesemiconductorshowingthecharge
trappedintheinterfacestateswhentheMOSFETgatebiasisVG<0[18]
57
5.6.2Depletion
Whenthegatevoltage,VG,isslightlymorethanzero,thiscausesanetnegativechargeat
the surface ofthe semiconductor dueto the depletionof holesfromtheregionnear the
surface leaving behind uncompensated ionized acceptors [8]. The MOSFET is said to
operateinthedepletionmode.
Donor type interface states will be below E FS and will be filled with electrons and be
neutral. Acceptortypeinterfacestates willbe aboveEFS andbe emptyof electronsthus
beingneutral[18].
trappedintheinterfacestateswhentheMOSFETgatebiasisVG >0[18]
5.6.3Inversion
When the gate voltage, VG, is further increased, the semiconductor surface is inverted
fromptypetontype.TheMOSFETissaidtooperateintheInversionmode[8].
Donor type interface states will be below E FS and will be filled with electrons and be
neutral.AcceptortypeinterfacestatesthatarebelowEFS willbefilledwithelectronsand
becomenegativelycharged.TheacceptortypeinterfacestatesthatareaboveEFS willstill
beemptyofelectronsandremainneutral[18].
58
trappedintheinterfacestateswhentheMOSFETgatebiasisVG >>0[18]
5.7RelationshipbetweenGateLeakageCurrentandInterfaceStates
Gateleakagecurrenthadnotbeenamajorconcerninthepastastheamountissmalland
insignificant. However, it increases in integration density of the Integrated Circuits and
reduction of size of the MOSFETs makes leakage current associated to the interface
statestobesignificant[21].
Reductionintransistorsizeentailsveryimportantelectricfieldinthetransistorchannel.
ThiscausedinjectionofhotcarriersinthegateoxideandcreatesdefectsintheSiSiO2
interface (interface states). The defects I the SiSiO2 interface in turn cause leakage
currentinthegate[19,21].
This gate current is responsible for the degradation in device operating characteristics
with time. This reliability issue is of considerably importance as the lifetime of
electronicpartshastobeguaranteed[19,21].
59
5.7.1GateCurrent,IG
Based on the lucky electron model, electrons acquire enough energy from the electric
field in the channel to surmount the SiSiO2 barrier. Once the required energy to
surmount thebarrierhasbeenobtainedtheelectrons are redirected towardstheSiSiO2
interfacebysomefromofphononscattering[17,21].
Theseelectrons,whichsurmounttheSiSiO2 barrier,areinjectedintotheoxidecausing
gatecurrent,IG [21].
5.8FixedOxidecharge(Qf,Nf)
Fixed Charge is a positive charge in the oxide layer less than 2nm from the SiSiO2
interface.Thischargeisnotinelectricalcommunicationwithunderlyingcharge.Itisalso
assumedtobeunchangedbygatebias[22].Typically,avalueof1.82x1010 eV1cm2 is
representativefortheinterfacechargefoundinultrathinoxidesiliconMOSdevices.
60
Chapter6
DeterminationofInterfaceTrappedChargesin
UltrathinOxideMOSFETs
6.1Introduction
TrapsattheSiSiO2 interfaceplayanimportantroleindeterminingthethresholdvoltage,
inversionlayermobilityandlowfrequencynoiseofMOSFETs.Properdevicemodeling
requirestheknowledgeofthedensityofinterfacestatesthroughoutthebandgap.
InMOSFETs,interfacetrapshavebeencharacterizedinthreeways:
1)
As an average value over both the surface energy bandgap and

channellength,Nit (cm2)[23,5]
2)
Asanaverageoverthebandgap,butnotchannellength,
Nit(x)(cm2)[5]
3)
Asanaverageoverchannellength,butnotsurfacepotentialenergy
inthebandgap,Dit(y)(eV1cm2)[24,25and26]
Usually two methods are widely in use as deterministic tools for interface trapped
charges.Theseare:
1)
ChargePumpingorCPMethod
2)
CapacitanceVoltageorCVMethod
TomentionthatinplaceofusingCVmethod,wehaveemployedanimprovedversion
oflowfrequencyCVmethod.
61
ThischapterdealswithdifferentexperimentsrunondifferentultrathinoxideMOSFETs
withtheaboveprocesses.
6.2ChargePumpingorCPMethod
In1969, Brugler andJespers [6]presentedtheideaof chargepumping inMOSdevices

and thus it became quite helpful day by day and this process is still used in some
modified[27,28]versionstodeterminetheinterfacestatedensity,interfacetrapcapture
crosssectionsetc.Inthechargepumpingtechnique,apulseisappliedtothegateofthe
MOSFET which alternatively fills the traps with electrons andholes, thereby causing a
recombination current (Icp) to flow in the substrate. If we further discuss the basic
experimentofCPmethodthefollowingsetupwouldbequitehelpful.
Figure6.1:BasicMOSChargePumpingExperiment
Inthisexperiment,the substratecurrentofaMOStransistorissmoothedbyacapacitor
andisfedtoadcammeter.Sourceanddrainareshortedandreversebiased(VR <0).In
the absence of any gate pulses, the ammeter simply indicated the junctions negative
leakage currents. When the ntype substrate is periodically inverted by negative gate
62
pulsesofwidthT S,thecurrentreversespolarityandbecomespositive.Itisalsoobserved
thatitsmagnitudeincreaseswithfrequency.
1.20E05
1.00E05
8.00E06
6.00E06
4.00E06
2.00E06
0.00E+00
0
2000000
4000000
6000000
8000000
10000000
12000000
Figure6.2:DCsubstratecurrent(IB inYaxis)inAvs.
Gatepulsefrequency(finXaxis)inHz
ThislinearityisclearlyindicativeofaChargePumpingactionwherebyafixedcharge
ismeasuredateachgatepulse.SincenoDCcomponentofthemeasuredmagnitudecan
flowthroughtheoxide,thischargemustbeinjectedacrossthejunctions.Acurrentof1.3
nA is measured at a1kHz frequency, sowehaveobtainedtherecordof the amountof
chargestoredtobe1.3pCperpulse.Interestingtonotethatthiscurrentisabletoflowin
theforwarddirection,oppositetotheleakagesevenifthejunctionsarereversebiased.So
wecansaythatatthissituation,powerisbeingtransferredfromthepulsesourcetothe
battery. Astudy ofthegateleakagecurrentshows thattheratioof the leakagecurrents
from two individualdeviceswithdifferentamountofgate areasisroughly equalto the
ratiooftheirrespectivegateareas.
Comingtothedescriptionofthebasicexperiment,thepumpedcurrentphenomenonis
relatedtothechargestoredunderthegateelectrodeateachcycle.Thisisunderlinedby
thefactthatthecurrentisalinearfunctionofthefrequency(Fig:6.2)andalsobythefact
63
that this current is roughly proportional to the gate area. The phenomenon may be
interpreted as a loss of a fraction of the total charge stored under the gate which
recombineswithmajoritycarriersofthesubstrateattheendofeachcycle.Toseewidely,
the sudden application of a gate voltage producing inversion generally results in a
situation of nonequilibrium. In the absence of a junction and without illumination the
requiredminoritycarriersmayonlycomefromthefollowingvarioussources:
1. Surfacegeneration
2. Generationinthedepletedregion
3. Diffusioninthebulkwithinadiffusionlengthfromthe
borderline of the depleted region, followedby a sweep
acrossthedepletedregion.
It isevident that after suddenapplicationof adc voltageto the gate, a nonequilibrium

situation occurs in which no inversion layer at all exists but only a depletion layer
extendingfarbeyond itssteadystatewidth.Then,withtheincreaseof time the various
sources of minority carriers listed above contribute to the formation of the inversion
layer,whilethedepletionregionreducesinwidth.
IfthereisajunctionpresentitiseasytounderstandthatthetransientbehaviourofaMOS
devicewillbequitedifferentfromthatdescribedabove,sincetheoppositeconductivity
region provides a fourth source of minority carriers for the substrate inversion layer.
Whenanegativegatevoltageisapplied,thepotentialbarrieracrossthejunctionwillbe
reducedunderitsequilibriumvalueforaveryshorttimeaccordingtotheconsiderations
developedabove,and thiswill allowalargeflowof freecarriers from thep+ regionto
thenregioninordertorestoreequilibrium.Theinversionlayercannowbuildupfastand
itseemsareasonableassumptiontoconsiderthatthecontributionofthesubstrateto the
inversion layer may be completely neglected. This is the situation in MOS transistor
structures, where the gate area is populated by carriers drawn from the source and the
drain.
64
Whenthegatepulseis removed there isevidencethat the inversionlayerdisappearsin

thesame manneras it wascreated.Aslong asthe fieldapplied tothesemiconductor is
large, thecarriersflowbackto the regionthey came from throughthecontactprovided
bythep+region(Fig:6.1).Progressively,theboundarybetweenthep+andtheinverted
n regions again gets the characteristics of a junction. A minority carrier, however,
continue to flow back to the p+ region until a new and opposite situation of non
equilibrium occurs that sweeps the minority carriers finding themselves within a
diffusion length from the transition across the slightly reverse biased junction. Before
reachingthefinalsteadystateconditions,someoftheexcessminoritycarriersarelostin
the substrate where they recombine with majority carriers, giving rise to the pumped
current.
So as an essence of the charge pumping methods, we can say, when the gate pulse is
applied, charge is drawn into the inversion layer from the transistor source and drain
regions, and when the gate pulse is removed, some of the charge recombines with the
majoritycarriersinthesubstrate.
6.2.1DeterminationofinterfacestatedistributionusingCPmethod
ThebrieflydiscussedmethodofCPintheprevioussectionwasproposedbyBruglerand
Jespers[6]whohavesuggestedthedeterminationofinterfacestatedistributionfromthe
risingedgeof thecurrent vs.gatevoltage characteristics,using thesurfacepotentialvs.
gatevoltagedependence.ButElliot[29]provedthisprocesstobedefectiveasduringthe
riseofthischaracteristic,thepotentialbarrierbetweensourceanddrainandthesubstrate
preventsthecarriersfromflowingintothechanneltofilltheemptystates.Hesuggested
usingtherisingedgeofhiscurrentvs.gatepulsebaselevelIordertoobtainthesurface
state distribution. This includes the dependence of surface potential on gate voltage
whichistobeobtainedbylowfrequencyCVmethod.However,inviewoftheemission
phenomenon, this method by Elliot is equally invalid, for the same reasons as those
mentioned earlier. Indeed, as long as the channel remains in the depletion region, the
majority carriers of the substrate cannot recombine with the trapped carriers in the
65
surfacestatesbecauseofthepotentialbarrierbetweenthesubstrateandthesurface.Only
when the surface potential reaches the flatband condition will trapping occur and the
filledstatescanrecombinewithholes.Thosmeansthattherisingedgeofthecurrentvs.
gate pulse base level only gives information in a very small region of a few kiloteslas
aroundtheflatbandposition,andnotoverthewholerangefromflatbandtoinversion.
Nowtakingtheemissionprocessinaccountwecanobtainthesurfacestatedistribution
overalargepartoftheforbiddenenergygapbydoingasimpleexperimentandwithout
needingthedependenceofsurfacepotentialongatevoltage.
When applying square pulses with variable fall times while keeping the rise time
constant, the scanning of the energy range in the upper half of the bandgap between
conduction band and midgap. On the other hand, when varying the rise time while
keepingthefalltimeconstant,theenergystatesinthelowerhalfofthebandgaparealso
scanned.Thechargewhichrecombinesduringeachcyclecanbewrittenas
E2
Qss = qAG Dit (E)dE
(6.1)
E1
whereE 1 andE2 aretheboundariesoftheenergyrangewhichisscannedandDit(E)isthe

interfacestatedensityatenergyE.thederivativeofQss withrespecttothefalltimeti of
thegatepulseisgivenby
dQss
dE
dE
= qAG Dit (E2 ) 2 - Dit(E1) 1
dti
dti
dti
(6.2)
When keeping the rise time constant, for example, while changing the fall time, it is
obtained
dQss
dE
= qAGDit(E2 ) 2
dtf
dtf
(6.3)
66
SinceE1 isdependentoffalltime.
Accordingtothesimpletheoryofemissionofcarriersfromsurfacestates,thefollowing
expressions can be derived by using a Taylor series expansion of the exponent time
dependencetermin[30,equation(31)]
(Ei- EF,inv) /kT
(EF,acc- Ei) /kT
Eem,e - Ei = -kTln uths nnitem,e + e
(6.4)
(6.5)
and
Eem,h - Ei = -kTln uths pnitem,h + e
where tem,e and tem,h are the times of nonsteadystate emission for electrons and holes,
respectively, andtheexponential termsareintroduced toaccount for the case when the
emission levels aresituated closer to thebandedges than the quasiFermi levels. Now,
accordingtoequation(6.4)E2 canbewrittenas
VFB - VT
E 2 = Ei - kTlnuths nni
tf
DVG
where, t em,e =
andso,
VFB - VT
DVG
(6.6)
(6.7)
tf
dE 2
kT
= dtf
tf
(6.8)
Therefore, accordingtoequation (6.3),while takinginto accountequation (6.8), Dit(E2)

canbefoundfrom
Dit(E2 )=-
tf
dQss
qAGkT dtf
(6.9)
67
Since,Qss=Icp/f,Dit(E 2)isgivenby,
tf
Dit (E2 )= -
dIcp
(6.10)
qAGkTf dtf
Bykeepingthefalltimeofthegatepulseconstantandchangingtherisetime,inasimilar
mannerweobtain,
Dit(E1)= -
dIcp
tr
qAGkTf dtr
(6.11)
Bymeasuringthechargepumpingcurrentwithvariablefallandrisetimesconsecutively,
theenergydistributionofthesurfacestatesinalargepartoftheforbiddenenergygapcan
beeasilyobtained.
Now itsourdestinationto accountforthechargepumpingcurrent,Icp.Consideringall

thevariableswefindthatchargepumpingcurrentbasicallyvariesaccordingtotheshape
ofthegatepulse.Fromcalculationwefindthatforsquareandsawtoothshapedpulses,
theexpressionforthechargepumpingcurrentcomesouttobeasfollowsrespectively:
V - V
Icp = 2qDit f.AG.kTlnuthni s ns p + ln FB T
DVG
tf :tr

VFB - VT
Icp = 2qDit f.AG.kTlnuthni s ns p + ln
DV
G
a (1- a )
(6.12)
(6.13)
These expressions have been verified for an nchannel device. It can be done for p
channelMOSFETs.
68
Tomentionthat snand sp,thecapturecrosssectionsforelectronsandholesrespectively,

are energy independent, which is probably not correct. It is observed that around the
middleoftheforbiddengap,thesecapturecrosssectionsarealmostenergyindependent
andthereforetheobtainedenergydependentDit isreliableinthisregion.Asanexample
of the discussed model above, the following figure shows the distribution of interface
statesobtainedincaseofannchanneldevice(ontheconductionbandside):
Dit [cm eV ]
1E11
1E10
1E9
0.4
0.3
0.2
0.1
0.0
0.1
0.2
0.3
0.4
Energy(eV)
Fig6.3:Energydistributionofinterfacetrappedchargedensities
The above distribution is obtained using 1 KHz frequency and at 20oC (293 K). Our
studies also revealed that by decreasing frequency one could measure closer towards
bandgap because maximum fall and rise time increase. By increasing the temperature,
deeperlevelscanalsobereachedbecauseofthetemperaturedependenceoftheemission
process.
69
6.3LowFrequencyCapacitanceVoltage(LFCV)Method
An improved version of the lowfrequency CapacitanceVoltage (LFCV) method [31,

32]forMOSinterfacetrapextractionisdiscussedhere.Arobustprocedureisemployed
to determine the integration constant in the calculation of surface potential, while an
accuratephysicalmodelisusedtoobtainatheoreticalCVcurve,properlyaccountingfor
quantization effects. The technique represents a substantial advance over the
conventional LFCV and highlow frequency methods for fast and reliable
characterizationofMOSinterfacetraps.
TheLFCVtechniqueoftwosteps[31,32].First,thesurfacepotential y s,definedasthe
potentialdropbetweenthesubstrateandtheSiSiO2 interface,isobtainedbyintegration
ofthegatecapacitance,thatis
1 G
ys(VG ) = y + (VG - V ) Cg,tot (VG' )dVG'
Cox V0
0
s
0
G
(6.14)
WhereVG isthegatevoltage,Cg.tot isthetotallowfrequencycapacitancemeasuredatthe

gate and C ox is the oxide capacitance. After the ys(VG ) has been determined, the
interfacetrapcapacitance,Cit,canbeobtainedfromasplitCVmeasurement[32]as
C it =
CgcCox
Cox - Cg,tot
- Cinv
(6.15)
Where Cinv istheinversionlayer capacitance, definedasthederivative ofthe inversion

chargewithrespecttothesurfacepotentialandCgc isthegatechannelcapacitance.
TheconventionalLFCVmodelsuffersinpracticefromseverallimitations.Fringeeffects
and overlap capacitances can be an important source of error. Also, most practical
70
devicesexhibitpolysilicongatedepletion,withanassociatedvoltagedropinsidethegate.
Toaccountfortheseeffects,(6.14)mustbereplacedby
ys(VG ) = y s0 + (VG - VG0) -
1 G
0
(Cg,tot -Cpar )dVG' - (Vpoly - Vpoly
)
Cox V0
(6.16)
Theparasitic capacitance, Cpar, inequation(6.16) ifoftenmarkedly nonlinear, therefore

the improvement is partial unless Cpar is accurately measured or computed for all bias
points. Also, the correction for thepolysiliconvoltagedropVpoly (typically 100200 mV
fromaccumulationtoinversion)cannotalwaysbeveryaccurate,sinceinpracticeonlyan
effective doping concentration inside the polysilicon can be measured [33]. We finally
notedthattheerrorduetotheneglectofthepolysiliconseriescapacitancein(6.15)isof
the order of a few percent at most, since in the nearthreshold regime the polysilicon
depletion is still weak and the series capacitance is much higher than the oxide
capacitance.
Thecalculationof y s requiresthepreciseknowledgeofthesurfacepotential y s0 atsome
gatevoltageVG0.Usually,abiaspointinstronginversionoraccumulationisused,where
thesurfacepotentialisknownwithgoodaccuracy[31,34and35].Asanalternative,the
flatbandvoltage[35]orthepointwherethesurfacebecomesintrinsic[32]maybeused.
However,itisclearfrom(6.16)thatthelargeristhedifferencebetweenVG andVG0,the
larger is the effect of Vpoly and Cpar. Fro most practical purposes, only traps in the
minoritycarriersideofthebandgapareofinterest(i.e.,forVG veryclosetoinversion).
These considerations, along with the wellknown difficulties in the accurate
determinationoftheflatbandvoltage,discouragetheuseofareferencevoltageVG0,the
conventional method is till affected by an important inaccuracy, due to channel
quantization.Infact,heavydopingofthesubstrateleadstoanarrowingofthepotential
well at the silicon/oxide interface and to a splittingof the electron states. With current
valuesofsubstratedopingoftheorderof10171018 cm3,anerrorof50100mVon y s0 is
madeiftheclassicalmodelisassumed[37],affecting(6.16)directly.
71
Fortheabovereasons,themodificationsofconventionalLFCVmodelweredoneintwo
respects.First,thesurfacepotentialandinversioncapacitancehavebeenobtainedfroma
self consistent solution of the coupled Schrodinger and Poisson equations [38], thus
accounting for quantization effects. The simulation also includes the effect of gate
polysilicon depletion, allowing the direct estimation of Vpoly from the numerical
simulation. The doping concentration of the polysilicon is determined from an
experimental technique such as that of [33], while the oxide thickness is obtained by
fittingthetheoreticalcurvetotheexperimentaldatainthestronginversionregion.This
procedureismoreaccuratethanapproximatingtheoxidecapacitancewiththemeasured
capacitanceinstronginversionoraccumulation,sincetheseriescapacitancesofthegate
andsubstratearealsotakenintoaccount.
The second modification of the LFCV method regards the determination of the
integrationconstant in(6.16).Asdiscussed above, toreducetheerrorto a minimum, a
referencevoltageVG0 closetothresholdmustbeused.Letsobservethefollowingfigure:
Figure6.4:Crosses:measuredgatecapacitances,Cgc.Solidline:simulated
capacitance.Dash dotline:positionoftheFermilevelwithrespecttothe
conductionbandedge,fromthenumericalsimulation
72
The previous figure compares the experimental gatechannel capacitance Cgc (crosses)
with the theoretical result (solid line), for a psubstrate MOS capacitor with channel
doping3.8X1010 cm3 anda12nmoxide.Thenpolysilicongatedopingwasestimated
as4X1019 cm3.Thesteeprisingedgebetween1.0and1.3Vcorrespondingtotheonset
of strong inversion can be used as a common reference for the theoretical and
experimental curves. So wehave assumed that the surfacepotential is the same for the
two curves when Cgc reaches a fixed fraction of g of the oxide capacitance Cox. This
assumption is valid with excellent accuracy if the trap capacitance is smaller than Cox,
whichiscertainlythecasefordevicegradeoxides.
Dit (statescm2eV1)
1E12
1E11
1E10
0.5
0.4
0.3
0.2
0.1
EEC(eV)
Figure6.5:Solidline:densityofinterfacestatesobtainedfromtheimprovedLFCV
method,shownasafunctionofenergywithrespecttotheconductionbandedgeEC.
Starline:densityofinterfacestates,alsoaccountingforinterfacialnonuniformities.
Crosses:resultobtainedwiththeimprovedmethod,whenanintentionalerrorof
10%isintroducedinthedopingconcentration.
73
Thesolidlineintheabovefigureshowstheexperimentalinterfacestatedensityextracted
from the data of fig. 6.4, using (6.14) and (6.15) with the improved method for the
calculationoftheintegrationconstant, y s0.Foralltheresultsoffig.6.5andthefollowing
fig.6.6,Cpar wasapproximatedbyaconstantvalue.
Dit (statescm2eV1)
1E12
1E11
1E10
0.50
0.45
0.40
0.35
0.30
0.25
0.20
EEC (eV)
Fig6.6: Solid line: result obtainedfromthe improved LFCV method(sameas the
solid line in fig. 6.5). Up triangle: LFCV result not including polysilicon voltage
drop, and using a conventional calculation of the surface potential. (O): Not
includingpolyvoltage drop,but with the improvedmethod forcomputing y s.(e):
LFCV result obtained from the improved method for the calculation of y s, but
withoutaccountingtheeffectsofquantumeffects.
Atthemeasurementfrequency1KHz,assumingacapturecrosssectionof1015 cm2,the
methodcandetectelectrontrapsintheupperhalfofthebandgap,startingabout0.45eV
below the conduction band. The upper limit of validity is given by the point were the
74
inversioncapacitanceCinv becomescomparablewithCit [12],whichisaroundVG=0.9V

for the simulated curve of fig. 6.4. The figure also shows on the right hand axis the
positionoftheFermilevel,asobtainedfromnumericalsimulation.Atagatevoltageof
0.9 VtheFermi level liesabout0.2eVbelowtheconductionband.Abovethisenergy,
theextractedvalueofDit canbeaffectedbyinaccuraciesinthemodelingoftheinversion
capacitancein(6.15).Toillustratethispointthestarlineinfig.6.5showsthetrapdensity
obtained by taking into account he effect of interfacial nonuniformities [39]. These
effects were modeled as a Gaussian fluctuation of the threshold voltage. The rms
amplitudeofthefluctuation(85mV)wasobtainedbyanempiricalfitting,assumingthe
worst case (i.e. the largest fluctuation consistent with the experimental data). The
discrepancy between the two results defines the largest error that canbe expected, and
confirmsthegoodaccuracyofthemethodoveranenergyrangeofabout300meV.
Thecurveshownascrossesinfig.6.5wasobtainedbyintroducinganintentionalerrorof
10%in the substratedopingconcentration,stillmaintaining anexcellent match. Infact,
the calculation based on (6.15) and (6.16) only depends on the local behavior of the
y s(VG ) curve at threshold, which is very weakly affected by changes in the doping
profile.Anegligibleerrorwasalsoobservedbyintroducingartificialerrorsintheoxide
thicknessandpolysilicondoping.
Fig.6.6comparestheresultoftheimprovedLFCVmethod(solidline)withtheresultsof
other techniques. The triangles represent the result of a trap extraction using the
conventionalmethodforthesurfacepotentialcalculation[31],neglectingthepolysilicon
voltage drop in (6.16). The reference point VG0 was taken at VG = +3V, i.e. about2 V
abovethreshold.Alargehorizontaldistortionofthetrapdensitycanbeobserved,mostly
duetotheeffectofVpoly.Forcomparison,thecurveshownascircleswasalsoobtained
neglecting Vpoly, butusing theimproved methodforthedeterminationof y s0.The good
agreement with the more accurate result confirms the robustness of the technique with
respecttononidealitiesofthedevice.Theresultshowninsquaresinfig.6.6wasobtained
from the LFCV procedure previously described, but without accounting for channel
quantization. Theneglect of the finite electron eigenenergies results in a corresponding
75
shifttowardmidgap,andtoanoverestimationofthetrapdensitybyaboutafactoroftwo.
ThereforewemayconcludethatwhiletheimpactofCpar andVpoly islargelyreduced,the
modelingofquantizationeffectsiscriticaltothistechnique.
6.4ExperimentalcomparisonbetweenCPandCVmethod:
CapacitanceVoltage(CV)andchargepumping(CP)techniquesarewidelyemployed
for the characterization of MOS interface of interface traps [5, 32]. However, since the
teststructuresaredifferent(largeareacapacitorsforCVandsmallertransistorsforCP).
Over a number of experiments, performed on samples of varying doping and oxide
thickness,CVandCPmeasurementswerefoundtoshowsystematicdifferences.
Figure 6.7 shows typical results of the two methods when applied to the same test
structures.ThesampleswerenMOSgateddiodeswithachanneldopingof8 1016 cm3
o
anda 200A drygateoxide.Thedeviceareawas4 104cm2 withann+ contactperimeter

of2cm.SamplesAhavestandardthermaloxide,whiletheoxideofbatchBwasnitrided
at N2O,1000oC. Figure6.7shows that:(a)CP gives aninterfacestatedensity about10
times higher inthedirectionofthemidgapregion,(b)theCP curvesfeature a weaker
energydependence.
76
1E12
Dit [cm2eV1]
1E11
1E10
A:CP
B:CP
A:CV
B:CV
1E9
1E8
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
EEC[eV]
Figure6.7:InterfacestatedensitiesderivedfromCVandCPmeasurementsonthe
samesamples.Theenergiesarereferredtothesiliconconductionbandedge.
The CV extractions were based on the comparison between the experimental low
frequency CV curves measured at 1 KHz, and the theoretical capacitance numerically
computedby a self consistent Schrodinger Poissonsimulator, accounting for channel
quantizationandpolysilicondepletion[32,38,40].CPcharacterizationswereperformed
alongthelinesof[5],usingtriangularwaveforms.
77
Chapter7
ProposalandEvaluation
7.1Discussion
A detailed study on ultrathin MOSFET structure, operation and modeling has been
performed throughout this thesis. For MOSFET modeling, a highly reliable model
(Physical alphapower law model) has been studied and modified with some necessary
changesintheexpressions.Theroleofinterfacetrappedcharges,raisedduetoimpurities
in MOSFETs, has been considered with high importance as their impact on ultrathin
MOSdevicesisverysignificant.
Awellorganizedstudyofthetwomajorprocessestodetermineinterfacetrappedcharges
has been presented. These two processes being the Charge Pumping Technique and
CapacitanceVoltageMethodhavealsobeenledtoacomparativeanalysisbetweenthem
forasetofsimilarsamples.Theircomparativestudiesraiseagoodinterest.
7.2Futurescopeofwork
A goodprospect liesin thisworkasitdealswith thereliable approachofmodeling the

ultrathin oxide MOSFETs. Further studies may lead to a set of more accurate
expressions.Inmanycasesapproximatelyequalvalueshavebeenusedandthisleavesa
scopeforthedeterminationofperfectenergybanddistributionofinterfacetrapcharges
in ultrathinMOSFETs. Besides, we performed an analysis of energy band distribution.
78
But a study can be performed on thedistribution of trappedcharges along thechannel

lengthalso.
Ultrathin oxide MOSFETs are widely used today. So, a sound approach to reduce the
existence of interface trapped charges through the introduction of advanced fabrication
wouldmakeawidescopeofresearchinthisrespectivesectorofsolidstatephysics.
79
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StateElectronics,Vol.21,pp.10821089,1978.
(2) K. Yamabe and Y. Miura, Discharge of Trapped Electrons from MOS

Structure, Journal of Applied Physics, Vol. 51, No. 12, pp. 62586264,
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(3) Q.D.M.Khosru,N.Yasuda,K. TaniguchiandC.Hamaguchi,Generationand

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Chapter1

Chapter 2: In this chapter, the physics and operation of MOS devices

portion of this chapter an analysis of the subthreshold slope of the

Chapter 4: This chapter deals with the development of the physical

Chapter5: Adetaileddescriptiononthelocationandpropertiesof the

Chapter 6: This chapter deals with two types of determination process

We assumethat the insulator layer hasinfiniteresistance, preventing any chargecarrier

Indeed, the ability toinduceand modulateaconductingsheetofminoritycareers at the

At stationary conditions, no net current flows in the direction perpendicular to the

Figure2.4:BanddiagramforMOScapacitorinweakinversion(j b <y s <2j b)

n s=ni2 ps = np0 exp(ys Vth )

where np0 =ni2 Na istheequilibriumconcentrationoftheminoritycarriers(electrons)in

where es isthesemiconductorpermittivityandthespacechargedensity r(x)isgivenby

n =np0 exp(y Vth )

Itistobenotedthat,deepinsidethesemiconductor,wehave y(a) =0.

Ingeneral,theaboveequationsdonothaveananalyticalsolutionfor y(x). However,the

is called the Debyelength. In(2.10),apositivesign shouldbechosenfora positive y s

where ei isthepermittivityoftheoxidelayerand Fs istheconstantelectricfieldinthe

QdT =-qNaddT = - 4esqNaj b

FsT =- QdT es = 4qNaj b /e s

Hence, substitutingthethreshold valuesof y s andFs in(2.14),weobtainthefollowing

VT =VFB + 2jb + 4e sqNaj b ci

VT = VFB + 2jb + 2e sqNa(2j b - VB ) ci

Asdiscussedabove, thethreshold voltage separatesthesubthreshold regime,where the

here, C s0 = Se s LDp isthesemiconductorcapacitanceattheflatbandcondition(i.e.,for

The semiconductor capacitance can formally be represented as the sum of two

In the highfrequency limit, the time constant of the generation/recombination

regime depends onthe frequency, with a value of Cmos

1 Cmin =1CdT + 1Ci

ThenwecalculatethedopingdensityNa using(2.23)with y s=2jb and(2.2)for jb.this

n s =2n0 ln1+ exp

In the MOSFET, an inversion layer at the semiconductoroxide interface acts as a

Typical currentvoltage characteristics of a longchannel MOSFET, where pinchoff is

I DSAT W COX m effVDSSAT VGS -VT - (h /2)VDSSAT

Where, (W/L) is thechannel widthtolengthratio, Cox istheoxidecapacitanceperunit

[1+ q (VGS - VT )][1+ VDS /(ECL)]

Fromtheaboveequationthevalueof a atVGS isobtained.Theexpressioncomesoutto

VDSSAT VGS - VT - (h 2)VDSSAT

The above equation expresses theparameter, a, as a function of VGS. A simplified and

VGS = (VDD +VT )/2

WCOX (VGS - VT )u sat

3.4.1IDS vs. VGS curve:

3.4.2IDS vs. VDS curve:

3.4.2.1IDS vs. VDS curve(VGS =0.8volt):

3.4.2.2IDS vs. VDS curve(VGS =1volt):

3.4.2.3IDS vs. VDS curve(VGS =1.5volt):

3.4.2.4IDS vs. VDS curve(VGS =2volt):

As we see, from the mathematical representation of the alpha powerlaw MOSFET

fast interface states. In our observations, we obtained the value of S to be 59.9

A detailed study of the MOS interfacestates ispresentedinchapter5in the following.

VGS =VFB + fs + g f s + f t exp((f s - 2f F ) /f t )

Depletion capacitance (Cd) is determined by calculating depletion width (Wm) that is

4.4.1IDS vs. VGS curve:

4.4.2IDS vs. VDS curve:

4.4.2.1IDS vs. VDS curve(VGS =0.8volt):

4.4.2.2IDS vs. VDS curve(VGS =1volt):

4.4.2.3IDS vs. VDS curve(VGS =1.5volt):

4.4.2.4IDS vs. VDS curve(VGS =2volt):

Theenergyor band gapof silicon is1.12 eV andgenerally, acceptor statesexistin the

Thissection willillustratethechange inoccupancyandcharge statewithdifferentgate

As an average value over both the surface energy bandgap and

In1969, Brugler andJespers [6]presentedtheideaof chargepumping inMOSdevices

It isevident that after suddenapplicationof adc voltageto the gate, a nonequilibrium