JawaharlalNehruEngineeringCollege

LabManual

AnalogandDigitalCircuits

For

SE(Rev)(EEP)Students

AuthorJNEC,Aurangabad

PREFACE

ItismygreatpleasuretopresentthislaboratorymanualforsecondyearEEPstudentsforthesubjectof
ADC. The practical involved in this subject are broadly divided as analog circuits and digital circuits.
Students are advised to thoroughly go through this manual rather than only topics mentioned in the
syllabus, as practical aspects are the key to understanding and conceptual visualization of theoretical
aspectscoveredinthebooks.GoodLuckforyourEnjoyableLaboratorySessions.

PriyankaBorude

Author


Jawaharlal Nehru Engineering College

Technical Document

This technical document is a series of Laboratory manuals of Electrical Electronics and Power,
is a certified document of Jawaharlal Nehru Engineering College. The care has been taken to
make the document error free but still if any error is found kindly bring it to the notice of subject
teacher and HOD.

Technical document No. EEP/Techdoc /21st May 2013/.

Recommended by,

HOD

Approved by,

Principal

Copies:

1. Departmental Library
2. Laboratory
3. HOD
Experiment 1.

AIM: To study Schmitt trigger using IC 741.

Apparatus: IC 741, resistors, frequency generator ,CRO probes, dual power supply.

Diagram:

Theory:

Schmitt trigger implemented by an inverting comparator

In the inverting version, the attenuation and summation are separated. The two resistors R1 and
R2 act only as a "pure" attenuator (voltage divider). The input loop acts as a simple series voltage
summer that adds a part of the output voltage in series to the circuit input voltage. This series
positive feedback creates the needed hysteresis that is controlled by the proportion between the
resistances of R1 and the whole resistance (R1 and R2). The effective voltage applied to the op-
amp input is floating; so, the op-amp must have a differential input.

The circuit is named inverting since the output voltage always has an opposite sign to the input
voltage when it is out of the hysteresis cycle (when the input voltage is above the high threshold
or below the low threshold). However, if the input voltage is within the hysteresis cycle (between
the high and low thresholds), the circuit can be inverting as well as non-inverting. The output
voltage is undefined; it depends on the last state and the circuit behaves as an elementary latch.

To compare the two versions, the circuit operation will be considered at the same conditions as
above. If the Schmitt trigger is currently in the high state, the output will be at the positive power
supply rail (+VS). The output voltage V+ of the voltage divider is:

The comparator will switch when Vin = V+. So must exceed above this voltage to get the
output to switch.
Once the comparator output has switched to VS, the threshold becomes to

switch back to high. So this circuit creates a switching band centered around zero, with trigger

levels (it can be shifted to the left or the right by connecting R1 to bias voltage).
The input voltage must rise above the top of the band, and then below the bottom of the band, for
the output to switch off (minus) and then back on (plus). If R1 is infinity or R2 is zero (i.e., an
short circuit), the band collapses to zero width, and it behaves as a standard comparator.

In contrast with the parallel version, this circuit does not impact on the input source since the
source is separated from the voltage divider output by the high op-amp input differential
impedance.

Applications :

Schmitt triggers are typically used in open loop configurations for noise immunity and closed
loop configurations to implement function generators.

Procedure:

1) Give 14v supply to pin 7 of IC741 and -14 V to pin no.4.

2) Make connections as in figure.
3) Observe input and output waveforms.
4) Plot the waveform on graph paper.
5) Draw hysteresis loop.

Graph of hysteresis loop:

 Calculation:

Vut: R1/(R1+R2)* (+V sat)

Vlt: R1/(R1+R2)* (-V sat)

Conclusion:

So by using op-amp we can implement Schmitt trigger which converts irregular waveform to
square wave .
Experiment No .2

AIM: To study half wave rectifier ckt using OPAMP IC 741.

Apparatus: IC 741,diodes,resistors frequency generators, CRO probes, dual power supply.

Theory:

Procedure:

1) Give 14v supply to pin 7 of IC741 and -14 V to pin no.4.

2) Make connections as in figure.
3) Observe input and output waveforms.
4) Plot the waveform on graph paper.

Conclusion: Thus at the output we get half wave rectified output with the input as full wave, due
to action of precision rectifier.
Experiment No 3

AIM: To study the square wave generator.

APPARATUS: IC 741, frequency generator, CRP probes, dual power supply.

THEORY

DIAGRAM:

GRAPH:

Procedure:

1) Give 14v supply to pin 7 of IC741 and -14 V to pin no.4.

2) Make connections as in figure.
3) Observe input and output waveforms.
4) Calculate input and output peak amplitude.
5) Plot the waveform on graph paper.

Conclusion: Thus by using IC 741 opamp at the output we get square wave output with the
input as sine wave.
Experiment No 4

AIM: To study op amp as an integrator.

Apparatus: Resistor , CRO, Frequency generator, capacitor, IC 741.

Diagram and Thoery:

Procedure:

1) Give input voltage as Vpp=1.6 V.

2) Make connections as in figure.
3) For different frequencies calculate output voltage.
4) Find out gain as Vout \ Vin.
5) Observe input and output waveforms.
6) Plot the graph of gain Vs. Frequency.

Observation table:

frequency Output Voltage Gain(Vo\Vin)

Conclusion:

Thus an Opamp can be used as an Integrator in different applications as ADC,Wave shaping

ckts etc.
 Experiment No 5

AIM: To study op amp as a differentiator:

Apparatus: Resistor, CRO, Frequency generator, capacitor, IC 741.

Theory:

Procedure:

1) Give input voltage as Vpp=1.6 V.

2) Make connections as in figure.
3) For different frequencies calculate output voltage.
4) Find out gain as Vout \ Vin.
5) Observe input and output waveforms.
6) Plot the graph of gain Vs. Frequency.

Observation table:
 frequency Output Voltage Gain(Vo\Vin)

Graph:

Conclusion:

Thus an Opamp can be used as an differentiator in different applications as ADC,Wave shaping

ckts etc.
Experiment No 6

AIM: To study 3-STATE 1-of-8 Line Data Selector/Multiplexer

Thoery:

DM74LS251

These data selectors/multiplexers contain full on-chip binary decoding to select one-of-eight data
sources, and feature a strobe-controlled 3-STATE output. The strobe must be at a low logic level
to enable these devices. The 3- STATE outputs permit direct connection to a common bus. When
the strobe input is HIGH, both outputs are in a high impedance state in which both the upper and
lower transistors of each totem-pole output are OFF, and the output neither drives nor loads the
bus significantly. When the strobe is LOW, the outputs are activated and operate as standard
TTL totem-pole outputs. To minimize the possibility that two outputs will attempt to take a
common bus to opposite logic levels, the output control circuitry is designed so that the average
output disable time is shorter than the average output enable time.

Features
n 3-STATE version of DM74LS151
n Interface directly with system bus
n Perform parallel-to-serial conversion
n Permit multiplexing from N-lines to one line
n Complementary outputs provide true and inverted data
n Maximum number of common outputs: 129
n Typical propagation delay time (D to Y): 17 ns
n Typical power dissipation: 35 mW
Diagram:

Function Table
H HIGH Logic Level
L LOW Logic Level
X Don't Care
Z High Impedance (OFF)
D0, D1D7 The level of the respective D input
Order Number Package Number Package Description
DM74LS251M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150
Narrow
DM74LS251N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300
Wide
Inputs Outputs
Select Strobe
YW
CBAS
XXXHZZ
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
H H H L D7 D7
Procedure:

1) Give input voltage as Vpp=16 V to Vcc.

2) Connect pin no 8 to ground.
3) Connect step input enable to pin no.7.
4) Connect respective data inputs.
5) Depending on input the input gate is selected and output is observed same as the input.

Conclusion: Thus with the help of multiplexer the output line gets selected according to select
lines.
Experiment No 7

AIM: To study 3-STATE 3-of-8 Line Data Selector/ demultiplexer

Thoery:
Conclusion: Thus we have studied 3-STATE 3-of-8 Line Data Selector/ demultiplexer
Experiment No 8

AIM: To Study CLOCK PULSE JK FF.

THOERY:

General Description
The JK Flip-flop

From the previous tutorial we now know that the basic gated SR NAND flip-flop suffers from
two basic problems: number one, the S = 0 and R = 0 condition or S = R = 0 must always be
avoided, and number two, if S or R change state while the enable input is high the correct
latching action may not occur. Then to overcome these two fundamental design problems with
the SR flip-flop, the JK flip-Flop was developed.

This simple JK flip-Flop is the most widely used of all the flip-flop designs and is considered to
be a universal flip-flop circuit. The sequential operation of the JK flip-flop is exactly the same as
for the previous SR flip-flop with the same "Set" and "Reset" inputs. The difference this time is
that the JK flip-flop has no invalid or forbidden input states of the SR Latch (when S and Rare
both 1).

The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are equal
to logic level "1". Due to this additional clocked input, a JK flip-flop has four possible input
combinations, "logic 1", "logic 0", "no change" and "toggle". The symbol for a JK flip-flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of
a clock input.
The Basic JK Flip-flop

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs

IC 7476 :

This device contains two independent positive pulse triggered J-K flip-flops with complementary
outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the
clock is LOW the slave is isolated from the master. On the positive transition of the clock, the
data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K
inputs are disabled. On the negative transition of the clock, the data from the master is
transferred to the slave. The logic state of J and K inputs must not be allowed to change while the
clock is HIGH. The data is transferred to the outputs on the falling edge of the clock pulse. A
LOW logic level on the preset or clear inputs will set or reset the outputs regardless of the logic
levels of the other inputs.
CONCLUSION: Thus we have studied CLOCK PULSE JK FF and verified truth table of
JKFF.