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A microprocessor is a programmable integrated device that has computing and decision-making

capabilities similar to that of the CPU of a computer.

A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device

that reads binary instructions from a storage device called memory, accepts binary data as input and
processes data according to those instructions, and provides results as output.

A microcomputer is a computer that uses a microprocessor as its CPU.

A microcontroller is a devices that has the functionalities of a microprocessor but also has on-chip
memory and i/o devices.

Microprocessors are typically used as CPUs of computers while microcontrollers are used in
embedded devices.

Each microprocessor has a fixed set of instructions in the form of binary patterns called a machine
language.

The binary instructions are given abbreviated names, called mnemonics, which form the assembly
language for a given microprocessor.

Intel was developing a programmable calculator. The original design needed 12 different chips with
hardwired logic functions. Ted Hoff suggested a general-purpose chip that could perform various
logic functions which could be activated by providing patterns of 0s and 1s. Intel coined the term
microprocessor and in 1971 released the first microprocessor as the Intel 4004.

Gordon E. Moore predicted that the number of transistors will double in integrated circuits
manufactured in every 18 months. (Moores law)

Evolution: 4004
4040
8008
8080
8085
8086
8088
80186
80188
80286

80386
80486
Pentium
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Chapter 2
8086 Machine Organization

Overview

Intel 8086
- Designer: Stephen Paul Morse
- Released in 1979
- HMOS technology
- 40-pin DIP
- CPU clock rate = 5 MHz to 10 MHz (higher than Intel 8085)
- 16-bit ALU
- 16-bit data bus and 20-bit address bus
- Lower-order address bus and data bus multiplexed
- Better support for high-level languages than previous microprocessors
- 24 addressing modes
- Bit, byte, word, and block operations
- 8- and 16-bit signed and unsigned arithmetic in binary or decimal including multiply and
divide
- Memory segmentation
- 6-byte instruction pipeline
- Hardware-level support for program debugging

Block diagram:

EU: Execution unit

BIU: Bus interface unit
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Memory Structure

The memory is a sequence of up to 220 bytes or 1 MB.

Only 256 KB can be addressed at a time.
A word is two consecutive bytes in memory; address of the lower-order byte is used as the address
of the word.
Lower-order bits of the data are stored in the lower-order byte; higher-order bits of the data are
stored in the higher-order byte.
8086 supports both byte- and word-instructions.
However, 16-bits of data are transferred in both cases.
A word starts with a byte with an even address.
So, more data transfer if an instruction operates on a word with an odd address; programmers can
use such instructions.

Memory Segmentation

1 MB memory is abstracted as an arbitrary number of segments.

A segment can be of up to 216 bytes.
A segment begins at an address that is divisible by 16, i.e. its four least significant bits are 0000.
A program can access 4 such segments at a time:
- Current code segment
- Current data segment
- Current stack segment
- Current extra segment
We identify the segments by storing the sixteen most significant bits of the address of its first byte in
special registers called segment registers.
Segments may overlap.
We address bytes and words in a segment using a 16-bit offset value.
Address = segment register<< 4 + offset.

Input/output Structure

Devices can be connected to 8086 through ports.

8086 can access up to 216 ports.
Ports have unique 16-bit addresses.
Ports can be used similar to memory addresses.
Two consecutive ports can be used a 16-bit port.
All ports are considered to be in one segment.

Register Structure

General registers:
15 8 7 0
AX AH AL Accumulator
BX BH BL Base
CX CH CL Count
DX DH DL Data
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Pointer and index registers:

15 0
SP Stack pointer
BP Base pointer
SI Source index
DI Destination index

Segment registers:
15 0
CS Code
DS Data
SS Stack
ES Extra

Instruction pointer and flags:

15 0
IP
FLAGS D O I T S Z A P C

IP is not directly accessible to the programmer.

Status flags:
- Carry flag (CF)
- Auxiliary carry flag (AF)
- Parity flag (PF) set if there are even numbers of 1s in the result.
- Zero flag (ZF)
- Sign flag (SF)
- Overflow flag (OF) indicates a signed result that is out of range.

Control flags:
- Direction flag (DF) direction of string manipulation instructions.
- Interrupt-enable flag (IF) enables / disables external interrupts.
- Trap flag (TF) puts processor in a single-step mode for program debugging.

Instruction Operands and Operand-addressing Modes

Format 1: Single-operand instruction with the operand in a 16-bit register. (Register addressing
mode)
opcode reg

reg 16-bit register 8-bit register

000 AX AL
001 CX CL
010 DX DL
011 BX BL
100 SP AH
101 BP CH
110 SI DH
111 DI BH
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Format 2: Single-operand instruction with the operand in an 8- or 16-bit register. (Register

addressing mode)
opcode w mod opcode reg
1 1
mode = 11

Width field (w)

If w = 0: 8-bit operand.
If w = 1: 16-bit operand.

Format 3: Single-operand instruction with the operand in memory. (Indirect addressing mode) (3
variants)
opcode w mod opcode m

mode = 00, 01, 10.

Offset = base register + index register + displacement.
m specifies the base register and index register.
mod specifies how to calculate the 16-bit displacement.

m Base register Index register

000 BX SI
001 BX DI
010 BP SI
011 BP DI
100 - SI
101 - DI
110 BP -
111 BX -
Not applicable if mod=11.
Not applicable if mod=00 and m=110.

If BX is used, then operand is in current data segment.

If BP is used, then operand is in current stack segment.

mod Displacement Additional bytes

00 00000000 00000000 0
01 00000000 next-byte 1
10 next-to-next-byte next-byte 2
Not applicable if mod=00 and m=110.

Address = segment register << 4 + offset.

Format 4: Use of segment overriding prefix.

Operands can be fetched from all four current segments; not just the current data segment and
current stack segment.
The instruction should have a 1-byte prefix.
seg
0 0 1 1 1 0
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seg Segment
00 Current extra segment
01 Current code segment
10 Current stack segment
11 Current data segment

Format 5: Single-operand instruction with the operand in memory. (Direct addressing mode)
opcode w opcode lower-order data higher-order data
0 0 1 1 0

Format 6. Two-operand instruction with both operands in registers. (Register addressing mode)
opcode d w mod reg1 reg2
1 1
mode = 11

Destination field (d)

If d = 0: result stored in reg2.
If d = 1: result stored in reg1.

Format 7. Two-operand instruction with one operand in a register and another in memory. (Indirect
addressing mode)
opcode d w mod reg m

mode = 00, 01, 10

Format 8. Immediate-operand instruction. (Immediate addressing mode) (2 variants)

opcode w reg lower-order data higher-order data

higher-order data present only if w = 1

Format 9. Immediate-operand instruction with one operand in a register. (Immediate addressing

mode) (2 variants)
opcode w mod opcode reg lower-order data higher-order data
1 1
mode = 11
higher-order data present only if w = 1

Format 10. Immediate-operand instruction with one operand in memory. (Immediate addressing
mode) (2 variants)
opcode w mod opcode m lower-order data higher-order data

mode = 00, 01, 10

higher-order data present only if w = 1

Format 11. Immediate-operand instruction with s field with one operand in a register. (Immediate
addressing mode) (2 variants)
Sign-extend field (s)
If s = 0: 16-bit immediate operand
If s = 1: 8-bit immediate operand
Applicable only if w = 1.
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opcode s w mod opcode reg lower-order data higher-order data

1 1 1
mode = 11
higher-order data present only if s = 0
One byte is eliminated by using s field.

Format 12. Immediate-operand instruction with one operand in memory. (Immediate addressing
mode) (2 variants)
opcode s w mod opcode m lower-order data higher-order data
1 1 1
mode = 00, 01, 10
higher-order data present only if s = 0

Exercise> Analyze the following instructions.

(a) 01000101 Format 1, INC
(b) 11111110 11000001 Format 2, INC
(c) 11111111 01000100 01011100 Format 3, INC. Assume SI = 10100000 10000110
(d) 00100110 11111111 01000100 01011100 Format 4, INC
(e) 11111110 00000110 11110000 01011010 Format 5, INC
(f) 00000010 11101011 Format 6, ADD
(g) 10111111 00001111 11110000 Format 8, MOV
(h) 11000111 00000111 00001111 11110000 Format 10, MOV
(i) 10000011 00000111 00001111 Format 12, ADD
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Chapter 3
8086 Instruction Set

Overview

Several instructions have a general (long) form as well as a restricted (short) form.
The short form
- uses fewer bytes
- less options for choosing operands
- used for frequently used cases
Programmer need not worry, assembler will choose proper form.

Instructions
- data transfer instructions
- general-purpose transfers
- accumulator-specific transfers
- address-object transfers
- flag transfers
- arithmetic instructions
- addition
- subtraction
- multiplication
- division
- formatting
- logical instructions
- Boolean
- shift and rotate
- string instructions
- elementary
- complex
- transfer of control instructions
- unconditional transfer
- conditional transfer
- interrupt instructions
- flag instructions
- synchronization instructions
- synchronization with subordinate processors
- resource sharing

Data Transfer Instructions

A segment register can be used as an operand. No sense of modifying a segment register; so no

other instruction has a segment register as an operand.

General-purpose transfers

 MOV
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Move register/memory from/to register.

100010 d w mod reg r/m

Move immediate to register/memory.

1100011 w mod 000 r/m lower-order data higher-order data

Move immediate to register.

1011 w reg lower-order data higher-order data

Move memory to accumulator.

1010000 w lower-order offset higher-order offset

Move accumulator to memory.

1010001 w lower-order offset higher-order offset

Move register/memory from/to segment register.

100011 d 0 mod 0 seg r/m
What happens if we modify CS?

 PUSH
Used for a word.

Push register/memory.
11111111 mod 110 r/m

Push register.
01010 reg

Push segment register.

000 seg 110

 POP
Used for a word.

Pop register/memory.
10001111 mod 000 r/m

Pop register.
01011 reg

Pop segment register.

000 seg 111

 XCHG

Exchange register/memory with register.

1000011 w mod reg r/m

Exchange with accumulator.

10010 reg
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Accumulator-specific transfers

 IN

Input to AL/AX.
1110010 w port
Direct addressing mode.
Can access only the first 256 ports.

Input to AL/AX.
1110110 w
Indirect addressing mode.
Use DX as port address.
Can access only all 216 ports.

 OUT

Output from AL/AX.

1110011 w port

Output from AL/AX.

1110111 w

 XLAT (Translate)
Transfer a byte from a table to AL.
Base of table stored in BX and index in AL originally.
Implied addressing mode.

Address-object transfers

 LEA (Load effective address)

Copy offset of m to reg.
10001101 mod reg r/m
mod = 00, 01, 10
Used to pass the offset of a variable from one part of a program to another part.
Used to implement call by reference.

 LDS (Load pointer to DS)

11000101 mod reg r/m
mod = 00, 01, 10
reg mem+1, mem
DS mem+2, mem+3
Used to set segment start address and offset.
The combination of segment start address and offset is called a pointer.

 LES (Load pointer to ES)

11000100 mod reg r/m
mod = 00, 01, 10
reg mem+1, mem
ES mem+2, mem+3
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Flag transfers

 LAHF (Load AH with flags)

Lower-order flags only.

 SAHF (Store AH into flags)

 PUSHF (Push flags)

Push lower-order flags first then higher-order flags.

 POPF (Pop flags)

Arithmetic Instructions

Add and subtract instructions set CF if the result, as interpreted as a unsigned number, is out of
range.
Add and subtract instructions set OF if the result, as interpreted as a signed number, is out of range.

Exercise> Add as signed and unsigned numbers.

(a) 00000111 + 11111011
(b) 00001001 + 01111100

Addition

 ADD

Add register/memory with register.

000000 d w mod reg r/m

Add immediate with register/memory.

100000 s w mod 000 r/m lower-order data higher-order data
higher-order data present only if s = 0.

Add immediate with accumulator.

0000010 w lower-order data higher-order data

 ADC (Add with carry)

Add with carry register/memory with register.

000100 d w mod reg r/m

Add with carry immediate with register/memory.

100000 s w mod 010 r/m lower-order data higher-order data
higher-order data present only if s = 0.

Add with carry immediate with accumulator.

0001010 w lower-order data higher-order data

 INC
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Increment register/memory.
1111111 w mod 000 r/m

Increment register.
01000 reg

Subtraction

 SUB

 SBB (Subtract with borrow)

 DEC

 NEG

Negate register/memory.
1111011 w mod 011 r/m

 CMP (Compare)
Similar to SUB except the operands are not affected.

Destination ____ to Source CF ZF SF OF

Equal 0 1 0 0
Signed Less than x 0 1 0
Less than x 0 0 1
Greater than x 0 0 0
Greater than x 0 1 1
Unsigned Less than 1 0 x x
Greater than 0 0 x x

Multiplication

8-bit 16-bit
Multiplicand AL AX
Multiplier Operand Operand
Product AX DX AX

 MUL

Unsigned multiply.
1111011 w mod 100 r/m

 IMUL

Signed multiply.
1111011 w mod 101 r/m
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Division

8-bit 16-bit
Dividend AX DX AX
Divisor Operand Operand
Quotient AL AX
Remainder AH DX

 DIV

Unsigned divide.
1111011 w mod 110 r/m

 IDIV

Signed divide.
1111011 w mod 111 r/m

Formatting

 CBW (Convert byte to word)

Extends sign bit of AL into all bit of AH.

 CWD (Convert word to double word)

Extends sign bit of AX into all bit of DX.

 DAA (Decimal adjust for addition)

 DAS (Decimal adjust for subtraction)

 AAA (ASCII adjust for addition)

 AAS (ASCII adjust for subtraction)

 AAM (ASCII adjust for multiplication)

 AAD (ASCII adjust for division)

Logical Instructions

Boolean

 NOT

 AND

 OR

 XOR

 TEST
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Same as AND but operands are not modified.

Shift and rotate

 SHL (Shift logical left)

CF Destination 0
Used for unsigned numbers.

 SHR (Shift logical right)

0
Destination
CF

 SAL (Shift arithmetic left)

CF Destination 0
Used for signed numbers.

 SAR (Shift arithmetic right)

Sign bit
Destination
CF

 ROL (Rotate left)

 ROR (Rotate right)

 RCL (Rotate left through carry)

 RCR (Rotate right through carry)

String Instructions

A string is a sequence of bytes or words in the memory.

A string operation is one that is performed on each element of a string.
Intel 8086 supports string instructions that decreases the time required for performing string
operations.
This is achieved by reducing the time taken to process each element and eliminating overhead and
bookkeeping.

Elementary

 MOVS (Move string elements)

CX contains the number of bytes or words to be moved.
DS and SI specify the source.
ES and DI specify the destination.
DS = ES (may be).
Overlapped source and destination?

1111001 w

Direction flag (DF)

If DF = 0: progress in forward direction.
If DF = 1: progress in backward direction.
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 SCAS (Scan string elements)

CX contains the number of bytes or words in the string.
DS and SI specify the source.
AL or AX contains the value being searched.

 CMPS (Compare string elements)

CX contains the number of bytes or words in the string.
DS and SI specify the source.
ES and DI specify the destination.

 LODS (Load string elements)

DS and SI specify the source.
Load in AL or AX.

 STOS (Store string elements)

Store in AL or AX.
ES and DI specify the destination.

 REP (Repeat)

 REPNE/REPNZ (Repeat while not equal/not zero; ZF=0)

 REPE/REPZ (Repeat while equal/zero; ZF=1)

REP, REPNE/REPNZ and REPE/REPZ are 1-byte repeat prefixes.

MOVS is typically used with REP.
SCAS and CMPS are typically used with REPNE/REPNZ or REPE/REPZ.

Complex

 JCXZ (Jump if CX contains zero)

11100011 Difference
Difference is a signed number.

 LOOP
Decrements CX and then jump.

11100010 Difference

 LOOPNZ/LOOPNE

1110000 z Difference

 LOOPZ/LOOPE
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Transfer of Control Instructions

Unconditional transfer

Jump, call and return instructions may be either intra-segment or inter-segment.

Inter-segment jump, call and return instructions changes the value of CS, transfer the control to an
arbitrary segment which becomes the current code segment.
An inter-segment call saves the CS and IP on the stack; while an inter-segment return removes two
words from the stack and places them in CS and IP.
Intra-segment call and return save and restore IP only.

 JMP

Jump direct intra-segment.

11101001 diff-low diff-high

Jump direct intra-segment (short).

11101011 diff

Jump indirect intra-segment.

11111111 mod 100 r/m

Jump direct inter-segment.

11101010 offset-low offset-high seg-low seg-high

Jump indirect inter-segment.

11111111 mod 101 r/m

 CALL

Call direct intra-segment.

11101000 diff-low diff-high

Call indirect intra-segment.

11111111 mod 010 r/m

Call direct inter-segment.

10011010 offset-low offset-high seg-low seg-high

Call indirect inter-segment.

11111111 mod 011 r/m

 RET

Return intra-segment.
11000011

Return intra-segment, adding immediate to SP.

11000010 data-low data-high
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Return inter-segment.
11001011

Return inter-segment, adding immediate to SP.

11001010 data-low data-high

Conditional transfer

No conditional call and return supported.

Only short intra-segment jumps supported.
J?? diff

 JE/JZ
 JNE/JNZ
 JL/JNGE (SF xor OF) = 1
 JNL/JGE (SF xor OF) = 0
 JLE/JNG ((SF xor OF) xor ZF)= 1
 JNLE/JG ((SF xor OF) xor ZF)= 0
 JB/JNAE CF = 1
 JNB/JAE CF = 0
 JBE/JNA (CF xor ZF) = 1
 JNBE/JA (CF xor ZF) = 0
 JP/JPE
 JNP/JPO
 JO
 JNO
 JS
 JNS

Interrupt Instructions

2 pins: Non-maskable interrupt (NMI) and interrupt (INTR).

NMI may be interrupted by a peripheral and is serviced irrespective of the status of IF.
INTR may be interrupted by a peripheral or the processor itself.
An interrupt type may be specified with INTR.
A table contains the starting addresses of the interrupt service routines.
The table starts at memory location 0, and has 256 entries.
Each entry is of 4 bytes, and contains the CS and IP corresponding to the starting address of the
interrupt service routine.
Processor saves flags, CS and IP before starting an interrupt service routine.
Interrupt types 0 to 31 are reserved, and are serviced irrespective of the status of IF.
Interrupt type 0: division by zero.
Interrupt type 1: single stepping.
Interrupt type 2: NMI.
Interrupt type 3: 1-byte INT instruction.
Interrupt type 4: signed overflow.
Interrupt types 5-31: future use.
Processor generates an interrupt type 0 when it attempts to divide by zero.
Signed overflow does not automatically generate an interrupt.
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 INT

Interrupt of specified type.

11001101 type

Interrupt of type 3.
11001100
Used to set breakpoints in a software debugger.

 INTO (Interrupt on overflow)

INTO should follow every signed arithmetic instruction where there is a chnce of overflow.

 IRET (Interrupt return)

IRET restores values of CS, IP and flags.
Restoring of flags is the only difference with inter-segment return.

 HLT
HLT stops processing and leaves CS and IP pointing to the instruction following HLT.

TF is used to implement single-stepping mode.

There is no instruction to directly read or write TF.

Flag Instructions

 CLC (Clear carry)

 CMC (Complement carry)

 STC (Set carry)

 CLD (Clear direction)

 STD (Set direction)

 CLI (Clear interrupt enable)

 STI (Set Interrupt enable)

Synchronization Instructions

Subordinate processors

 ESC (Escape)
Seek help of a subordinate processor.

11011 x mod y r/m

X denotes the subordinate processor.
Y denotes the operation.
mod and r/m denote memory location of operand.
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 WAIT
Waits for subordinate processor to complete processing.
When subordinate processor completes it send a signal to the TEST pin.
WAIT should precede ESC.

Resource sharing

1-byte LOCK prefix to synchronize with other processors.

Puts a high signal on the LOCK pin during the execution of the following instruction.

[Last updated on 1 September 2016]