1.

If a magnetic disc has 100 cylinders, each containing 10 tracks of 10 sectors, and each sector can
contain 128 bytes, what is the maximum capacity of the disk in bytes?
2. Which interrupt is used for which hardware automatically transfers the program to a specific
memory location? Explain how it works?
3. Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an
output in binary number equal to the square of the input number.
4. A bus is a set of wires connecting computer components. A computer may have several buses,
e.g. a system bus, an internal bus, and special purpose local buses. All communication between
the various components takes place over one of these buses. For example, data transfer
between the CPU and memory normally occurs on the system bus, while movement of data
between registers and the ALU takes place on a bus internal to the microprocessor chip. The
speed at which data can be transferred is dependent on the number of data lines in the bus and,
in the case of synchronous buses, the clock speed of the bus. The transfer rate or bandwidth of a
particular system bus can be calculated from the number of cycles required for transfer, the
length of the cycle and the number of data lines. For example, if a bus has S data lines, requires
4 cycles to transfer data,(1609) CSE301 4 and each cycle is 250 nsecs then the bandwidth of the
bus is 1 byte per 1000 nsecs. This is equivalent to 1 byte per microsecond or 1
megabyte/second.

Answer the following questions :

(a) In order to execute a program instructions must be transferred from memory along a bus to
the CPU. If the bus has 8 data lines, at most one 8 bit byte can be transferred at a time. How
many memory access would be needed in this cast to. transfer a 32 bit instruction from memory
torithc;, CPU? Explain.

(b) Suppose that a bus has 16 data lines and reares 4 cycles of 250 nsecs each to transfer data.
11C bandwidth of this bus would be 2 Mega byte sec If the cycle time of the bus was reduced to
12Q"-nsecs and the number of cycles required WI transfer stayed the same, what would the
bandwidth of the bus?

(c) Nam: the buses that computer must at least consist of during circuit designing.

5. Design an arithmetic circuit with one selection variable 'S' and two n-bit data inputs A and B.
The circuit generates the following four arithmetic operations in conjunction with the input
carry C in. Draw the logic diagram for the first two stages.
S Cin = 0 Cin = 1
0 D = A + B (Add) D = A + 1 (Increment)
1 D = A – 1 (Decrement) D = A + B +1 (Subtract)

5. The content of PC in the basic computer 1s 3 F (all nun1bers are in hexadecimal) . The content of
AC is 7EC3 . The content of memory at address 3AF is 832E. The content of memory at address
32E is 09AC. The content on memory at address 9AC is 5A8E. Calculate the following:
(a) What is the instruction that will be fetched and executed next?
 (b) Show the binary operation that will be performed in the AC when the instruction is
executed?
(c) Give the contents of register PC, AR, DR, AC and IR in hexadecimal and the values of E, I and
the sequence counter SC in binary at the end of the instruction cycle?
6. Calculate the following.
(a) How many 128 x 8 RAM chips are needed to provide a memory capacity of 2048 bytes?
(b) How many lines of the address bus must be used to access 2048 bytes of memory? How
many of these lines will be common to all chips?
(c) How many lines must be decoded for chips select? Specify the size of decoder.
7. A non- pipelined system takes 50ns to process a task. The same task can be processed in a six-
segment pipelined with a clock cycle of 10ns. Determine the speedup ratio of the pipeline for
100 tasks. What is the maximum speedup that can be achieved?
8. A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is
stored in one word of memory. The instruction has four parts: an indirect bit, an operation code,
a register code part to specify one of the 64 registers, and an address part.
(a) How many bits are there on the operation code, the register code part, and the address
[art?
(b) How many bits are there in the data and address inputs of the memory?
9. A bus organized CPU has 16 registers with 32 bits in each, an ALU and a destination decoder.
(a) How many multiplexers are there in the A bus, and what is the size of each multiplexer and
how many selection inputs are needed for MUX A and MUX B?
(b) How many inputs and outputs are there in the ALU for data, including input and output
carries?
(c) Formulate a control word for the system assuming that the ALU has 35 operations.
10. How many switch points are there in a crossbar switch network that connects p processors to m
memory modules? 2 marks
11. How many 128 x 8 memory chips are needed to provide a memory capacity of 4096 x 16 ? 2
marks
12. Show that adding B after the operation A+B+1 restores the original value of A. What should be
done with the end carry?
Why should the sign of the reminder after a division be the same as the sign of the dividend?
13. A computer employs RAM chips of 256 x 8 and ROM chips of 1024 x 8. The computer systems
need 2K bytes of RAM, 4K bytes of ROM, and four interface units, each with four registers. A
memory-mapped I/ O configuration is used. The two highest-order bits of the address bus are
assigned 00 for RAM, 01 for ROM, and 10 for interface registers.
(i) How many RAM and ROM chips are needed?
(ii) Draw a memory-address map for the system.
(iii) Give the address range in hexadecimal for RAM, ROM and interface.
14. An output program resides in memory starting from address 2300. It is executed after the
computer recognizes an interrupt when FGO becomes a 1 (while 1EN = 1)
(i) What instruction must de placed at address 1?
(ii) What must de the last two instructions of the output program?
15. The 8-bit register AR, BR, CR and DR initially have the following values:
AR 11110010
 BR = 11111111
CR = 10111001
DR = 11101010
Determine the 8-bit values in each register after the execution of the following sequesnce of
micro operations.
AR AR + BR
CR CR /\ DR, BR  BR + 1
AR  AR – CR

16. The content of the top of a memory stack is 5320. The content of the stack pointer SP is 3560 . A
two-word call subroutine instruction is located in memory at address 1120 followed by the
address field of 6720 at location 1121. What are the contents of PC, SP and the top of the stack.
(i) Before the call instruction is fetched from memory?
(ii) After the call instruction is executed?
(iii) After the return from subroutine?
17. A DMA controller transfers 16 bit words to memory using cycle stealing. The words are
assembled from a device that transmits characters at a rate of 2400 characters per second. The
CPU is fetching and executing instructions at an average rate of 1 million instructions per
second. By how much will the CPU be slowed down because of the DMA transfer?
Give at least six status conditions for the setting of individual bits in the status register of an
asynchronous interface.