Assignment 1

Subject: Computer System Architecture

Subject Code: INFO 119

Total marks: 100

Ques 1:

a) Reduce the following functions using K maps: (2 marks each)

i)

ii)

b) Convert SR Flip Flop to JK Flip Flop (6 marks)

Ques 2:

a) Implement the following functions with a 8:1 MUX (5 marks)

i) F(w,x,y,z) = ∑ m(0,1,3,5,8,9,15)
ii) F(A,B,C) = πM(2,3,4,7)

b) What is a Priority encoder? Design a 4 –bit priority encoder (Truth table+ K map
Simplification+ Logic diagram) (5 marks)

Ques 3:
a. Convert the following decimal numbers (a,b,c) to the bases indicated:
(4 marks)
i) 756 to octal
ii) 1930 to hexadecimal
iii) 175 to binary
iv) (4A52)16 to octal
 b. You went to Capri Trade center On Chakrata Road, Dehradun just for buying some
computer accessories. You went to a computer shop X, where you overhear a customer
asking the owner of computer Shop X-“what is the fastest computer in the store that he
can buy”. The owner of shop X replies,“You’re looking at our Macintoshes. The fastest
Mac we have runs at a clock speed of 1.2 gigahertz. If you really want the fastest
machine, you should buy our 2.4-gigahertz Intel Pentium IV instead.” Is Billy Bob
correct? What would you say to help this customer? (3 marks)

c. Perform the arithmetic operations in binary using signed 2’s complement representation
for negative numbers. Check if anyone has overflow or not.( Represent number in 9 bits).

(3 marks)
i) (+40) + (131)
ii) (-40)-(-131)
iii) (-150)+(-250)

Ques 4:

a. A digital computer has a common bus system for 16 registers of 32 bits each. The bus is
constructed with multiplexers. (3 marks)

i) How many selection inputs are there in each multiplexer?

ii) What size of multiplexers are needed?
iii) How many multiplexers are there in the bus?

b. The 8-bit registers AR, BR, CR, and DR initially have the following values: (4 marks)

AR = 11110010

BR = 11111111

CR = 10111001

DR = 11101010

Determine the 8-bit values in each register after the execution of the following sequence of
microoperations.

i) AR <- AR + BR Add BR to AR
ii) CR <- CR ^DR, BR<^BR + 1 AND DR to CR, increment BR
iii) AR <- AR - CR Subtract CR from AR

c. What is Von Neumann Bottleneck? (3 marks)

Ques 5:
a) A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is
stored in one word of memory. The instruction has four parts: an indirect bit, an operation code,
a register code part to specify one of the 64 registers, an operation code and an address part.
(5 marks)

i) How many bits are there in the operation code, the register code part and the address
part
ii) Draw the instruction format and indicate the number of bits in each part
iii) How many bits are there in data and address inputs of the memory

b) How Reduced Instruction Computer Architecture (RISC) is different from Complex

Instruction set computers (CISC). (5 marks)

Ques 6:

a) A two word instruction is stored in memory at an address designated by the symbol W.

the address field pf the instruction stored at W+1 is designated by the symbol Y. The
operand used during the execution of the instruction is stored at an address symbolized by
Z. an index register contains the value X. state how Z is calculated from the other addresses
if the addressing mode of the instruction is (5 marks)
i) Direct
ii) Indirect
iii) Relative
iv) Indexed

b) A non- pipelined system takes 50 ns to process a task. The same task can be processed in a
six segment pipeline with a clock cycle of 10 ns. Determine the speed up ratio for 100
tasks. What is the maximum speedup that can be achieved? (5 marks)

Ques 7:

a. What is the difference between a branch instruction, a call subroutine instruction and a
program interrupt? (5 marks)

b. Give five examples of external and internal interrupts? Differentiate between a software
interrupt and a subroutine call? (5 marks)

Ques 8:

The content of PC in the basic computer is 3AF (all numbers are in hexadecimal).The content of
AC is 7EC3. The content of memory at address 3AF is 932E. The content of memory at address
32E is 09AC. The content of memory at address 9AC is 8B9F. (10 marks)
 i) What is the instruction that will be fetched and executed next?
ii) Show the binary operation that will be performed in the AC when the instruction is
executed.
iii) Give the contents of registers PC, AR, DR, AC, and IR in hexadecimal and the values of
E, I, and the sequence counter SC in binary at the end of the instruction cycle

Ques 9:

a. Explain the conflicts/hazards in Instruction pipeline. (5 marks)

b. Consider 32 bit processor with 16 bit external bus driven by 8 MHz clock. This processor
has a bus cycle time of 4 clock cycles. (5 Marks)

i) What is the maximum data transfer rate across the bus in bytes/second?
ii) What will be the data transfer rate if we double the clock rate?
iii) What will be the data transfer rate if we made the external data bus 32- bit wide?

Ques 10: Explain and Design asynchronous MOD 10(decade) counter. (5 marks)