IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO.
7, OCTOBER 2020
Design of an 8-bit Bit-Parallel RSFQ Microprocessor
Pei-Yao Qu , Guang-Ming Tang , Jia-Hong Yang , Xiao-Chun Ye , Dong-Rui Fan,
Zhi-Min Zhang, and Ning-Hui Sun
Abstract—With Moore’s law approaching its physical limits,
low-temperature computing technology is ushering in unprece-
dented development opportunities. Rapid single-flux-quantum
(RSFQ) circuit technology is currently the most mature supercon-
ducting integrated circuit technology. Based on the current fabrica-
tion process, we propose an 8-bit bit-parallel RSFQ microprocessor.
The proposed microprocessor processes 8-bit data each clock cycle.
Ten different instructions are executed. The microprocessor mainly
consists of an on-chip instruction memory, two data registers, an
instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and
a program counter. The microprocessor contains 7702 JJs (based
on the Open Dataset of CONNECT Cell Library for AIST ADP2)
without considering splitters, Josephson transmission lines, and
passive transmission lines. We perform a logic-level simulation of
the proposed microprocessor. The simulation results show correct
operation with a target frequency of 16.7 GHz.
Index Terms—Digital circuit, rapid single-flux-quantum
(RSFQ), superconducting microprocessor.
I. INTRODUCTION
NERGY-EFFICIENT computing technology is required
E by many large-scale computing systems. Superconducting
computing may be able to serve the needs of these systems
significantly better than conventional technology [1]. Rapid
single-flux-quantum (RSFQ) circuit technology [2] is currently
the most mature superconducting integrated circuit technology,
whose clock frequency can be up to tens of gigahertz and energy
dissipation can be down to several milliwatt. Several RSFQ
derivatives have been developed, such as ERSFQ [3], LR-RSFQ
[4], and RQL [5], etc. We propose an 8-bit bit-parallel RSFQ
microprocessor based on the Open Dataset of CONNECT Cell
Library for AIST ADP2.
Manuscript received December 29, 2019; revised May 26, 2020 and August
13, 2020; accepted August 15, 2020. Date of publication August 18, 2020; date
of current version August 28, 2020. This work was supported in part by the
Innovation Program of Institute of Computing Technology, Chinese Academy
of Sciences under Grant 20186120, in part by the Strategic Priority Research
Program of Chinese Academy of Sciences under Grant XDA18000000, and
in part by the National Natural Science Foundation of China under Grant
61732018. This article was recommended by Associate Editor N. Yoshikawa.
(Corresponding author: Guang-Ming Tang.)
Pei-Yao Qu and Dong-Rui Fan are with the State Key Laboratory of Computer
Architecture, Institute of Computing Technology, Chinese Academy of Sci-
ences, Beijing 100190, China, and also with the University of Chinese Academy
of Sciences, Beijing 100049, China.
Guang-Ming Tang, Jia-Hong Yang, Xiao-Chun Ye, Zhi-Min Zhang, and Ning-
Hui Sun are with the State Key Laboratory of Computer Architecture, Institute of
Computing Technology, Chinese Academy of Sciences, Beijing 100190, China
(e-mail: tangguangming@ict.ac.cn).
Color versions of one or more of the figures in this article are available online
at https://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TASC.2020.3017527
1051-8223 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
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1302706
So far, several RSFQ microprocessors have been developed.
An 8-bit bit-serial microprocessor FLUX has been designed and
fabricated [6], [7]. 8-bit bit-serial microprocessors CORE series
[8]–[11] have been designed, fabricated, and demonstrated. A
bit-serial asynchronous microprocessor (SCRAM2) [12] and a
bit-serial 8-bit microprocessor (CORE e4) [13] have been de-
signed. A prototype of a 32-bit superconducting microprocessor
based on 4-bit bit-slice architecture has been presented at ASC
2016 [14].
Besides, some RSFQ datapath circuits have been designed.
Arithmetic logic unit (ALU) is the most important component of
a microprocessor. An 8-bit parallel ALU was developed. It was
demonstrated successfully at low frequency tests [15] and high
frequency tests [16], respectively. An 8-bit parallel ALU [17]
with a target frequency of 30 GHz was developed. A serial ALU
[18] with a frequency of 80 GHz was developed. A 4-bit bit-slice
ALU [19] for a 32-bit RSFQ microprocessor was demonstrated
successfully. A logic design of a 16-bit bit-slice ALU [20] for
32-/64-bit RSFQ microprocessors was proposed.
In this article, we propose an 8-bit bit-parallel RSFQ micro-
processor. The proposed microprocessor processes 8-bit data
in one clock cycle. The throughput is higher than bit-serial
processing and bit-slice processing in previous work. Ten in-
structions are executed, including addition (ADD), immediate
addition (ADDI), input (IN), output (OUT), loading immediate
(LOADI), shift right logic (SRL), data movement (MOV), PC-
relative branch (JB), no operation (NOP), and stop operation
(HALT) instructions.
The remainder of this article is organized as follows. Section II
describes the microarchitectural and logic design of the 8-bit bit-
parallel microprocessor. Section III shows the simulation results.
Section IV evaluates the results of our design. Finally, Section V
concludes this article.
II. 8-bit BIT-PARALLEL RSFQ MICROPROCESSOR
The proposed microprocessor is based on Harvard architec-
ture. It includes an on-chip instruction memory (IM) and two
data registers. The IM and the data registers are addressable by
4-bit address and 1-bit address, respectively. It can be imple-
mented using present-day fabrication processes. The proposed
microprocessor can execute seven different types of instructions.
A. Instruction Set
Table I lists the instruction set of the proposed microprocessor.
“D” and “S” represent the destination register and source register
 1302706
Fig. 1. Microarchitecture of the proposed microprocessor (the red lines show the datapath of IN and OUT instructions).
number, respectively. “I” represents the immediate data. “A”
represents the immediate address.
The instruction set includes seven different types of instruc-
tions, including ALU instructions (ADD, MOV), immediate
instructions (ADDI, LOADI), conditional branch (JB), shifter
instruction (SRL), data I/O instructions (IN, OUT), no operation
instruction (NOP), and halt instruction (HALT). Among them,
immediate instructions set four least significant bits of instruc-
tion code with sign extension as immediate data. JB instruction
sets four least significant bits of instruction code with zero
extension as immediate address. In addition, NOP instruction is
implemented by moving the data from R0 to R0, which is used
to generate a bubble between two dependent instructions. HALT
instruction is implemented by looping the operation moving the
data from R1 to R1, which is used to halt the microprocessor
until an external signal start it again.
B. Microarchitecture
Fig. 1 shows the microarchitecture of the proposed micropro-
cessor. We only consider using on-chip memory and registers to
store instructions and data. The instructions and data are loaded
by hand. The main circuit components are six multiplexers
(MUXs), a 4-bit program counter (PC), an instruction decoder
(ID), an on-chip 8-bit IM, two 8-bit data registers (DRs), a
control signal buffer, an 8-bit bit-parallel ALU, and I/O port
registers.
To illustrate the steps how the microprocessor executes the
instructions, we take IN and OUT instructions for example. The
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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO. 7, OCTOBER 2020
TABLE I
INSTRUCTION SET
red lines in Fig. 1 show the datapath for executing IN and OUT
instructions. At the first step, PC sends a 4-bit address to IRs. At
the second step, according to the address, IN instruction is read
out to ID, meanwhile, PC is generating the next address to fetch
OUT instruction. At the third step, ID sends the control signals
M1 and STORE_R1 to the buffers, meanwhile, OUT instruction
is read out to ID. At the fourth step, MUX1 sends the input data to
R1 according to M1, meanwhile, ID sends the control signals M2
and OUT_OP to the buffers. At the fifth step, R1 stores the input
data according to STORE_R1 and send it to MUX2. At the sixth
step, MUX2 sends the data to output register according to M2.
Finally, according to OUT_OP, the data output to external. The
other instructions can be executed in the same way according to
the corresponding control signals.
C. Logic Design
We have designed the logic circuits of all the components
in the proposed microprocessor. XOR gate, AND gate, NOT
gate, D flip-flop (DFF), dual-port D flip-flop (D2FF), resettable
D flip-flop (RDFF), confluence buffer (CB), and nondestructive
readout (NDRO) based on the Open Dataset of CONNECT Cell
Library for AIST ADP2 are used. The data of delays, timing
constraints, number of JJs, area units, and power consumption
are included in the dataset. Fully synchronous timing is adopted
in the microprocessor, which means that there is only one clock
source.
1) Arithmetic Logic Unit: ALU is the main component of
datapath for the proposed microprocessor. It is used for the
 QU et al.: DESIGN OF AN 8-bit BIT-PARALLEL RSFQ MICROPROCESSOR 1302706

TABLE II
DECODING TRUTH TABLE

implementation of ADD, ADDI, LOADI, and SRL instructions.

The instruction set and the logic circuit design of the ALU are
defined in [21]. It contains 1180 JJs and 6 gate-level pipeline
stages.
2) Multiplexers: We use the MUXs as arbitration circuits
in the microprocessor to release the required data. We have
designed synchronous and asynchronous MUXs. A synchronous
MUX contains 17 DFFs, a NOT gate, 16 AND gates, 8 CBs,
which consists of two gate-level pipeline stage, and 409 JJs. An
asynchronous MUX consists of a DFF, a NOT gate, 16 RDFFs,
and 8 CBs, which consists of only one gate-level pipeline stage
and 233 JJs. In order to reduce the gate-level pipeline stage and
hardware consumption, asynchronous timing method is adopted
in MUXs.
3) Instruction Memory and Instruction Decoder: Table II
lists the decoding truth table of the ID. I0–I7 represent the 8-bit
instruction code. Z0 and Z1 are used to represent weather the
data from R0 and R1 equals to 0, respectively. Mn(0 < n < 7)
represent the control signals of MUXn. STORE_R0 and
STORE_R1 control the operations of data register R0 and R1,
respectively. OUT_OP is the control signal of output port reg-
ister. FINISH signal is used to control the HALT instruction
executes or not.
Considering the fabrication process and the further physical
layout, we adopt the simplest cells to implement the ID, as shown
in Fig. 2. It contains 7 NOT gates, 22 AND gates, 2 XOR gates,
12 CBs, and 38 DFFs, which consists of 719 JJs and 3 gate-
level pipeline stages. The on-chip IM is realized by 128 NDROs
and 12 CBs, which contains 2248 JJs. The delay for reading an
instruction from the on-chip IM is the main factor to limit the
minimum clock cycle.
4) I/O Port Registers: Input and output in the proposed mi-
croprocessor are achieved by simple port registers. If an 8-bit Fig. 2. Logic design circuit of the ID.

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 1302706
TABLE III
TESTBENCH OF THE PROPOSED MICROPROCESSOR
data are presented to the input port by an external device, the data
then are moved into the microprocessor to be processed. Con-
versely, the data from the output port register can be displayed
externally. The I/O port registers totally contain 208 JJs.
III. SIMULATION
We have performed logic-level simulation of the designed
microprocessor with Icarus Verilog [22] and GTKWave software
[23]. We used Verilog hardware description language [24] to
do the logic-level simulation based on the Open Dataset of
CONNECT Cell Library for AIST ADP2. The simulation results
show that the proposed microprocessor operates correctly at the
target frequency of 16.7 GHz. As mentioned earlier, the delay for
reading an instruction from the on-chip IM limits the clock cycle.
From the results, the delay for on-chip IM is 46.8 ps. According
to the data from the Open Dataset of CONNECT Cell Library
for AIST ADP2, the maximum setup time of the cells we used
is 7.4 ps, and the maximum hold time of the cells we used is
4.1 ps. Thus, we set the clock period as 60 ps. The simulation
results of the datapath circuits for the proposed microprocessor
are shown in [21].
To verify the functionality of the whole design, we have
defined a testbench for the proposed microprocessor, as shown
in Table III. The testbench includes all instruction types. In
Table III, “NC” means “not necessary” and “ … …” means omit-
ting the instructions between JB and OUT instructions. In the de-
sign, we use software bubble to avoid data and structural hazards.
Because the latency for an instruction to execute completely is
twice that of PC to generate an address, a NOP instruction is
inserted between two dependent instructions and before or after
JB instruction to ensure the correctness of program execution.
This method cuts the number of available IM, but it can reduce
the hardware cost to some extent.
We have successfully obtained correct results for the proposed
microprocessor. Fig. 3 shows the simulation results of the mi-
croprocessor. In the figure, the first trace is the clock signal.
The next eight traces are the instructions read from the on-chip
IM according to corresponding address. The next eight traces
are 8-bit input data from external. The next eight traces are
8-bit output data to external, which represent the corresponding
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IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO. 7, OCTOBER 2020
output of the microprocessor. The nine traces at the bottom are
the control signals of the microprocessor, which determine the
corresponding operation based on the instructions.
According to the test vectors in Fig. 3, at 541.9 ps, the IN
instruction is read from the IM. After 12 clock cycles (60 ps per
clock cycle), control signal M1 = 1, an 8-bit data (0011 0011)
is input into the microprocessor. At the next clock cycle, control
signal STORE_R1 = 1, 0011 0011 is stored in data register R1. At
1981.9 ps, the SRL instruction is read from the IM. The control
signals M4 and STORE_R0 = 1. After 13 clock cycles, the result
after shifting right 0001 1001 stores in R0. At 3421.9 ps, the
LOADI instruction is read from the IM. According to M3, M5
and STORE_R1 = 1, after 13 clock cycles, the immediate 0000
0110 is loaded into R1. At 4861.9 ps, the ADD instruction is
read from the IM. After 3 clock cycles, control signal M2 = 0,
M4 = 1, 0001 1001 and 0000 0110 are released by the MUX2
and MUX4, respectively. After 8 clock cycles, M3 = 1, MUX3
releases the result from ALU (0001 1111). After 2 clock cycles,
control signal STORE_R1 = 1, 0001 1111 is stored in data
register R1. At 6301.9 ps, the JB instruction is read from the
IM. The address 1100 is sent to PC. After PC+1, the OUT
instruction is read from the IM. After 3 clock cycles, control
signal M2 = 0, 0001 1111 from R0 is released by the MUX2. At
the next clock cycle, control signal OUT_OP = 1, then the 8-bit
data (0001 1111) is output to external. At 9181.9 ps, the HALT
instruction is read from the IM. Then, the microprocessor stops
all operations, although the clock signal is still input.
From the waveform, it shows a 16.7-GHz clock frequency,
but also shows 24 cycles (24 cycles × 60 ps = 1440 ps) between
executable instructions. There is a NOP instruction between
every two executable instructions. Thus, the clock per instruction
(CPI) of the microprocessor is 12. The value of CPI includes
the NOP operation. There is room for improvement if a system
clock is adopted. Among the 12 cycles, the delay for PC waiting
the input address amounts to six cycles and the delay for PC
calculating the output address amounts to six cycles.
From the simulation results, the delay of ALU amounts to
385.8 ps, the delay of the ID amounts to 133.2 ps, every 720 ps,
PC sends an address to the IRs. The latency for executing
the designed testbench (IN-SRL-LOADI-ADD-JB-OUT-HALT)
is 9181.9 ps at 16.7 GHz.
IV. EVALUATION
According to the RSFQ logic circuits of all the components
for the proposed microprocessor. The number of cells and JJs
used in the microprocessor circuits is shown in Table IV with-
out considering splitters (SPLs), Josephson transmission lines
(JTLs), and passive transmission lines (PTLs). Table IV lists
that the number of JJs for on-chip IM is much larger than other
components, whereas the number of JJs for I/O port registers is
the least. Also, the number of DFFs is larger than other cells,
most of which are used as buffers to synchronize the data and
control signals.
We compared the previous works with the proposed micro-
processor in Table V. From the results, the million instructions
per second (MIPS) of the proposed microprocessor is the most.
 QU et al.: DESIGN OF AN 8-bit BIT-PARALLEL RSFQ MICROPROCESSOR
Fig. 3. Simulation results of the proposed microprocessor.
TABLE IV
HARDWARE CONSUMPTION OF THE PROPOSED MICROPROCESSOR
TABLE V
COMPARISON OF 8-bit MICROPROCESSOR
We have to declare that the result is just based on simulation but
not the physical realization. After taking this into account, the
useful peak throughput will be negatively impacted. As a result,
the advantage will decline.
V. CONCLUSION
We have designed the RSFQ logic circuits of all the com-
ponents for the proposed microprocessor and simulated the
microprocessor at the gate level. It contains 7702 JJs (without
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1302706
considering JTLs, PTLs, and SPLs) among which 2248 is for
the on-chip IM, 1310 is for the MUXs, and 1180 is for the ALU.
The hardware cost of the microprocessor is relatively low, which
is possible to be fabricated with current fabrication process.
The simulation results show it operates correctly at the target
frequency of 16.7 GHz.
In this article, we only design and logically simulate the
proposed microprocessor, but not do physical realization and
simulation. There are two challenges of wiring and precise
timing control when the physical design of the microprocessor is
implemented. We will realize the physical design in next work.
ACKNOWLEDGMENT
The authors would like to thank Nagoya University, Yoko-
hama National University, and AIST in Japan for providing Open
Dataset of CONNECT Cell Library for AIST ADP2.
 1302706 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 30, NO. 7, OCTOBER 2020
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