CH9-1

CH9-2
CH9-3
CH9-4
variations in element values

Vo/Vo=2%

Output voltage ripple spec.: 1~10%

CH9-5
CH9-6
ve vref Hv
vc Gc (s)ve
CH9-7
 Diode
snubber
Snubber LP

Gc(s) H( s )
Snubber

PWM IC 3842

CH9-8
Direct duty cycle (voltage mode)
control

carrier

CH9-9
Direct duty cycle (voltage mode) control

CH9-10
 Current Mode control

Inner loop

Outer loop

vc directly control iL and thus Vo

Ideally, vc should act to directly control average
of iL for fastest response
CH9-11
Current Mode control

CH9-12
 H(s)

vc ( s )
Tc (s)
ve ( s )
ve ( s )

H(s)
CH9-13
 ve vref Hv

The objective is to make Hv=vref (i.e. ve=0), so v(s)

accurately follows vref(s) regardless of
disturbances or variations in the other portion of
system
In practice, ve0 but nonetheless small, adding
Gc(s) can obtain small error ve vref Hv
vc Gc (s)ve vevc Gc (s)
Large Gc gain leads to small error, and output
follows reference input with good accuracy
CH9-14
 d(s) 1 v(s)
Tm (s) Tp (s) Gvd (s)
vc (s) VM
d( s )

v fb (s) R1
H(s)
v(s) R1 R2 Ch2, 3, 5, 7 SC model
vc (s) Gc 0 1 s / z
Gc (s) ( e.g. type II )
ve ( s )
s 1 s / p
1 Gvg(s)
Gc(s) VM
Gvd(s)

T(s)
vfb(s)=H(s)v(s)

H(s)
Loop gain T(s): product of forward & feedback path
gain 1
T(s)=Gc(s) Gvd(s) H(s)
VM CH9-15
 If loop gain T(s) is large in magnitude, the
disturbance influence on v is small ve vref Hv
Large loop gain also cause ve0, then v vref(s)/H(s)
but nonetheless small, adding Gc(s) can obtain
small error
Simple phase margin (PM) criterion for
assessing stability is used. When the PM of loop
gain T(s) is positive, then the feedback system is
stable
Increasing PM causes system transient response
to be better behaved, with less overshoot &
ringing
CH9-16
 Compensator is designed to attain adequate PM
& good rejection of expected disturbances
Lead compensator (PD controller) are used to
improve PM & extend feedback loop bandwidth.
Better rejection of high-frequency disturbance
Lag compensator (PI controller) are used to
increase low-frequency loop gain. Better
rejection of low-frequency disturbance and very
small steady-state error

CH9-17
Power stage

CH9-18
 (9.1)

Disturbances vg and iload propagate to the output

through the transfer function Gvg and the output
impedance Zout.
If the disturbances vg and iload are known to have
some maximum worst-case amplitude, then Eq. (9.1)
can be used to compute the resulting worst-case
open-loop variation in v

CH9-19
CH9-20
 (9.1)
v (s) Gvd (s)d (s) Gvg (s)v g (s) Zout (s)iload (s)

CH9-21
 Y ( s) forward path gain G
TF
R( s) 1 loop gain 1 GH

Loop gain T(s)=Product of the gains around the

forward and feedback paths of the loop
CH9-22
v variation resulting from vg variation is
attenuated by feedback loop CH9-23
CH9-24
 1
Gc (s), , Gvd (s)
VM

v sensitivity to forward path gains is

reduced, but increased to H & vref
CH9-25
f p1 f z f p 2
T0: dc gain

H (s)Gc (s)Gvd (s)

T (s)
VM

0dB
CH9-26
f << fc
f >> fc

f << fc

f >> fc

CH9-27
asymptote

At low frequency is At high frequency,

0 dB follow T

CH9-28
 H (s)Gc (s)Gvd (s)
T (s)
VM f << fc

f >> fc

feedback CH9-29
Disturbances: vg and iload

Gvg (s)
1 T ( s)
Zout (s)
1 T ( s)

CH9-30
At low frequency, follow 1/ T
CH9-31
At low frequency, T is large, disturbance transfer
function from vg and ilaod to v are

v (s) Gvg (s) Gvg (s)

v g (s) 1 T (s) T ( s)

v (s) Zout (s) Zout (s)

iloadg (s) 1 T (s) T (s)

The magnitude of closed-loop T.F. is reduced by

the factor 1/ T , at f << fc
Ifwe want to reduce this TF by a factor of 20 at 120
Hz, then we need a loop gain T at least 20 26
dB at 120 Hz
CH9-32
At high frequency, T is small, disturbance transfer
function from vg and ilaod to v are

v (s) Gvg (s)

Gvg (s)
v g (s) 1 T (s)

v (s) Zout (s)

Zout (s)

iloadg (s) 1 T (s)

This is the same as the original TF (open loop) and

output impedance. So the feedback loop has no
effect on the disturbance TF at f >> fc

CH9-33
CH9-34
 N ( s)
T ( s)
D(s)

CH9-35
CH9-36
 Phase Margin (PM) Test
PM : m 180 T ( j 2 fc )
o

A special case of the theorem known as the phase margin

test is sufficient for designing most voltage regulators
If has one crossover frequency only, and if the loop gain T(s)
contains no RHP poles, then the quantities 1/(1 + T) and T/(1
+ T) contain no RHP poles when the PM is positive
Using a simple test on T(s), we can determine the stability
of T/(1 + T) and 1/(1 + T). This is an easy-to-use design.
When T contains RHP poles (i.e., the original open-loop
system is unstable), then the PM test cannot be used. The
more general Nyquist stability theorem must be employed

CH9-37
Phase & Gain Margin

CH9-38
 PM:

When exist multiple crossover frequencies, PM test may be ambiguous. If

T contains RHP poles, PM test cannot be used (Nyquist stability theorem)
CH9-39
Positive PM- Stable system
CH9-40
Negative PM implies that T/(1+T)
& 1/(1+T) each contain at least
one RHP pole CH9-41
 A small PM (in T) causes the closed-loop T.F. T/(1 + T) and 1/(1 + T)
to exhibit resonant poles with high Q
As the PM is reduced, these characteristics become worse (higher
Q, longer ringing) until, PM<0, for the system becomes unstable
CH9-42
 1 1
f f
f f0 and f0 f f2 , T (s) 0
0 f0 f
1 1
2 f2 f0 f2
f f2 , T (s)
0 2 f0 f 2 f 2
CH9-43
CH9-44
f0 f2

c 02

CH9-45
f2 f0

CH9-46
(9.25)

CH9-47
Homework#16 Derivation of Eq. (9.25)
Hint
1
T (s)
s s
1
0 2
Let T ( j ) 1 find cross over frequency c [c f (0 , 2 )]
find m 180o T ( j 2 f c ) [m f (0 , 2 ) f (Q)]
o f0 f0
Q Q
2

2 fc f2

1 1 4Q4 sinm
tanm
2Q 4
cosm
CH9-48
 1
T (s)
s s
1
0 2

obtaining real poles (Q < 0.5) requires a phase margin of at least 76. To
obtain Q = 1, a phase margin of 52 is needed
The system with a phase margin of 1 exhibits a closed-loop response
with very high Q
With a small phase margin, T ( j) is very nearly equal to 1 in the vicinity of
the crossover frequency. The denominator (1 + T) then becomes very
small, causing the closed-loop transfer functions to exhibit a peaked
response at frequencies near the crossover frequency fc
CH9-49
 1
T (s)
s s 1 T ( s)
1 Output response Inverse Laplace
0 2 s 1 T ( s)

f 2 4 f 0 , Q 0.5, complex poles, underdamped

f 2 4 f 0 , Q 0.5, a Hi and a Lo freq. real poles, overdamped

f 2 4 f 0 , Q 0.5, 2 real poles at 2 f 0 , critical damped CH9-50

()
CH9-51
 1
T (s)
s s
1
0 2

High-Q poles lead to overshoot and ringing. In most power

applications, overshoot is unacceptable
For example, in a 3.3 V computer power supply, the voltage
must not be allowed to overshoot to 5 or 6 volts when the
supply is powered onthis would likely destroy all of the
integrated circuits in the computer!
So the Q-factor must be sufficiently low, often 0.5 or less,
corresponding to a phase margin of at least 76 in this case
CH9-52
 v ( s) Z ( s)
out
iloadg ( s) 1 T ( s) Load regulation

v ( s) Gvg ( s)

v g ( s) 1 T ( s) Line regulation

response time can be shortened by increasing

the feedback loop crossover frequency

Low Q-factor

CH9-53
 Effect of load current variations on v regulation
v (s) Zout (s)


i ( s ) 1 T ( s )
load

if T is sufficiently large, then the closed-loop output

impedance will be less than the given limit
Effect of vg variations (120 Hz rectification harmonics) on
v regulation
v (s) Gvg (s)

v g (s) 1 T (s)
output voltage ripple can be reduced by increasing T
that at ripple frequency (100 or 120 Hz)

CH9-54
 Transient response time: when large disturbance
occurs, the v may undergo a transient and it will
deviate from specified allowable range. Eventually,
feedback loop should operate to return v within
tolerance. Increasing feedback loop crossover
frequency can shorten the transient time
Overshoot & ringing: allowable overshoot &
ringing should be limited, such requirement
implies the PM must be sufficiently large
Each of these requirements imposes constraints on
the loop gain T(s). Therefore, the design of the
control system involves modifying the loop gain, a
compensator network is added for this purpose
CH9-55
 fp
Gc (s jf max f z f p ) Gc 0
fz

fz f p

fz sufficiently far
below the fc
Often application
in systems contain
two-pole response
Feedback loop bandwidth can be extended while
maintaining an acceptable PM CH9-56
 s
1
z
PD type compensator Gc (s ) Gc 0
s
1
p

Max. Phase occurs at the frequency fmax given

f max fz fp (geometrical mean of f z and f p )

To obtain maximum improvement in PM, let fmax = fc

2
1 j (1 ) j( )
z zp z p
Gc (s j ) Gc 0 Gc 0
2
1 ( )
1 j p
p
CH9-57
 2
1 j (1 ) j( )
z zp z p
Gc (s j ) Gc 0 Gc 0
2
1 ( )
1 j p
p

Phase of Gc(s) at fmax

f max fz fp
max max f max f max

z p fz fp
Gc ( max ) tan 1
tan 1

max
2
f2max
1 1
zp fz fp
fp fz

1
f max ( f p f z ) 1
fz fp ( fp fz ) 1
fz fp
tan tan tan (9.34)
2 fz fp 2 fz fp 2
CH9-58
Derivation of (9.35)

fp fz

fz fp fp fz
Gc ( f max ) tan 1
2 tan
2 fz fp
fpfz fp f 1
4 tan 2 , Let x z
2

fz fp fz fp x
x 2 ( 2 4 tan 2 )x 1 0,
( 2 4 tan 2 ) ( 2 4 tan 2 )2 4 ( 2 4 tan 2 ) 4 tan 1 tan 2
x
2 2
( 2 4 tan 2 ) 4 tan sec sin 2 sin
2 1 2
2 cos 2 cos 2
2 sin 2 2 sin cos 2 (1 sin )2 (1 sin )2

cos
2
cos 2
1 sin 2
1 sin
(9.35)
1 sin
CH9-59
Derivation of (9.36)
fp 1 sin
fc fz fp , x ( 9.35)
f z 1 sin
fz 1 1 sin
f z fc fc fc
fp x 1 sin
fp 1 sin
f p fc fc x fc ( 9.36)
fz 1 sin
Derivation of (9.37) s
fc 2 1
1 ( ) z
fz Gc ( s) Gc 0
Let Gc ( f f c ) 1 Gc 0 s
fc 2 1
1 ( )
fp p
fz
Instituting fc f z f p Gc 0 (9.37)
fp
CH9-60
 s
1

Gc (s ) Gc 0 z

s
fz f p 1
p
CH9-61
 s
1

Gc (s) Gc 0 z

s
1
p

CH9-62
 fp/10 10fz

Loop gain T(s) contains two poles CH9-63

 ( f / f L )1 f f L
Gc Gc 1 ( L )2
Gc f f L
Inverted Zero

L
Gc (s j ) Gc 1 j

1 L

90 o
f fL
Gc tan o
0 f f L

Inverted zero is added
At low f, the inverted zero causes compensator to integrate
error signal CH9-64
Uncompensated loop gain Tu 0
Tu (s)
s Single pole
PI type compensator 1
0
L
Gc (s) Gc 1
s
Compensated loop gain L
1
T (s) Tu (s)Gc (s) Tu 0Gc s
s
1
0
L L L
1 j (1 ) j ( )
T G 0 0
T (s j ) Tu 0Gc
u 0 c
2
1 j 1 ( )
0 0
L 2 L
1 ( )
1 0
T Tu 0Gc , T tan
2 L
1 ( ) 1
0 0 CH9-65
 L 2 L
1 ( )
T Tu 0Gc , T tan 1 0
2 1 L
1 ( )
At high f 0 0

Tu 0Gc Tu 0Gc
T , at f f c , T 1 f c Tu 0Gc f 0
( f / f0 ) ( fc / f 0 )
fc
for desired f c Gc
Tu 0 f 0

Corner frequency fL<<fc, such that an adequate

PM is maintained

CH9-66
 PI Gc makes low freq. loop gain
increase, but PM unchanged

Gc
Gc

f0
10 -20db/dec

fL
10

L
1
T( s) Tu ( s)Gc ( s) Tu0Gc s
s
1
0 CH9-67
 1
1 , Low f , T large
T
1 T
1, High f , T small

CH9-68
 Zout (s) Gvg (s)
(9.30), (9.31)
1 T ( s) 1 T ( s)

At f < fL, the PI compensator improves the rejection of

disturbances
At dc, the Gc magnitude approaches , the magnitude of
1/(1 + T) tends to zero
Hence, the closed-loop disturbance-to-output transfer
functions, such as Eqs. (9.30) and (9.31), tend to zero at dc
CH9-69
 Combined (PID) Compensator
Combining lead & lag compensators merit to obtain
both wide bandwidth & zero steady-state error
At low frequencies, the PID integrates the error signal,
leading to large low-frequency loop gain and accurate
regulation of the low-frequency components of the
output voltage
At high frequency (in the vicinity of the crossover
frequency), the PID introduces phase lead into the loop
gain, improving the phase margin

CH9-70
 fL f z f p1 f p 2

-20dB/dec. +20dB/dec. -20dB/dec.

-45o/dec.

+45o/dec. -45o/dec.

CH9-71
 Inverted zero at fL functions in the same manner
as PI compensator
Zero at fz adds phase lead in vicinity of cross-over
frequency, as in PD compensator
High frequency poles fp1 & fp2 must cause the gain
to roll off at high frequencies and to prevent
switching frequency ripple from disrupting the
operation of PWM
fc of loop gain is choose to be greater than fL & fz,
but less than fp1 & fp2

CH9-72
Output: 15V/5A

CH9-73
 CCM

VM4V

D 1
Vc DVM
Vc VM
Vref
ve vref Hv 0 H
V CH9-74
CH9-75
Gd0=15/0.536
L=50H, C=500F

R=3
CH9-76
CH9-77
CH9-78
 Gc ( s) H ( s) V 1
T ( s)
VM D 1 s s
( )2
Q00 0

H=1/3, V=15V, 5kHz

D=0.536, VM=4
Q0, 0, Tu0, are known, then let Tu =1 to determine fc and PM
CH9-79
 Uncompensated Gc ( s) 1
H ( s) V 1 1
T ( s) Tu 0
VM D 1 s s s s
( ) 2
1 ( )2
Q00 0 Q00 0
Q0 9.5, 0 2 fo 2.68 1kHz 2680 rad / s
Tu 0
Tu ( s j )
2
1 ( 2680 ) j 25460

Q0, 0, Tu0, are known, then let Tu(=c) =1 to

determine crossover frequency fc , then use Tu(jc)
to find PM at fc Uncompensated Gc ( s) 1
fc 1.8kHz, PM 50
CH9-80
 s


z
1
Gc (s) Gc 0
s
(1/20)fs 1
p

-20.26
0.097 Tu (w 2 5kHz) 0.097

+20.26dB=10.3
(9.36)

HW#17
CH9-81
 1 HV
Tu ( s) Tu0 , Tu 0 2.33, Gc 1
s s 2 DVM
1 ( )
Q00 0
1 2.33
Tu Tu0 0.097 20.3dB
f fc
c 2 2 c 2 24
[1 ( ) ] ( )
0 Q00
Q0 9.5, 0 2 1k , c 2 5k c 2
1 ( )
z
Gc ( f f c ) 10.3( 20.3dB) Gc 0
c 2
1 ( )
p
c 2 5k , z 2 1.7k , p 2 14.5k
10.3
Gc 0 3.51 10.91dB 11dB
2.935
CH9-82
 52o

fz 1.7kHz
fp 14.5kHz

CH9-83
2.333.51=8.178=18.25 dB fz 1.7kHz
fp 14.5kHz
dc gain

fz
10
fp
10 10 f z

-128o

fp
please verify T ( jc ) 128
o
10
f 10 f z PM 52o
CH9-84
 1
1 , low f , T large
T
1 T
1, high f , T small
1 1
v ( Dvg ) (0.536 1V ) 0.062V
T 8.6

If vg(t) contains 100 Hz variation of amplitude 1 V, with closed-loop

control, it attenuates the variation by 1/8.6, then 100 Hz output voltage
variation has magnitude 0.062V CH9-85
 PM

500Hz

CH9-86
 1
1 , low f , T large
T
1 T
1, high f , T small

CH9-87
D=0.536

CH9-88
Supplementary
Materials for
Compensator
Design
CH9-89
Compensated Error Amplifier

TOL ( s ) T1 ( s )Tc ( s )
vo ( s ) vo ( s ) d ( s )
T1 ( s ) Tp ( s )Tm ( s )
vc ( s ) d ( s ) vc ( s )
Tc ( s ) T.F. of compensated EA
For a given T1(s), Tc(s) must be properly tailored so that
TOL(s) meets performance requirements expected of power
supply CH9-90
 Desired Characteristics of Open-
loop TF
1. Low-freq. Gain should be high to minimize
steady-state error in PS output
2. Crossover freq. should be high but an order of
magnitude below switching freq. to allow quick
response for transients
3. Phase margin (PM): PM=OL+1800 (PM should be
positive quantity, determines transient response
of Vo in response to sudden change in load & Vd)
OL = phase angle of TOL at crossover freq. (negative)
Desired phase margin range: > 450
CH9-91
 General Compensated EA

In addition to a pole at origin, one of options in

selection of Tc(s) is to introduce a pole-zero pair

A>0, z < p
CH9-92
 General Compensated EA

Parameters can be chosen to

minimize phase lag in Tc(s)
occurs at desired crossover
p0 freq. of the overall TOL(s)

Due to zero

Pole at origin Pole at p CH9-93

Type 2 CEA
A( s z ) vc ( s) Zf
TC ( s)
s( s p ) vo ( s) Zi
1 1
Zi R1 , Z f ( R2 )//
sC1 sC2
1 1
( R2 )
vc ( s) SC1 SC2

vo ( s) R1 ( R2
1

1
)
SC1 SC2
1
Type 2 CEA S
R2C1

C1 C2
R1C2S( S )
R2C1C2
CH9-94
 Type 2 CEA

If C2 C
1 then

1 1
S S
vc ( s) R2C1 R2C1

vo ( s) C1 C2 1
R1C2S( S ) R1C2S( S )
R2C1C2 R2C2
C1 C2 1
poles 0 p
R2C1C2 R2C2
1
zero z
R2C1 CH9-95
 Type 2 CEA

Middle-
frequency gain
Gc = R1/R2

CH9-96
 Type 2 CEA
Control Loop TF Frequency Response
(Type II)

z p
cross
1
20 log
Power stage & Filter VP
20log Gvd

Middle-frequency gain and CEA TF pole & zero

location must be designed to provide desired
PM & GM required for stability
CH9-97
 Type 2 CEA Design
1 s z
Tc ( s )
R1C2 s( s p )
vc ( j) j z C C2
s j z
1
, p 1
vo ( j) R1C2 j( j p ) R2C1 R2C1C2
cross
K p
For middle Freq. ( z , p ) z cross

vc ( j) j 1 R2
Gain :
vo ( j) R1C2 j p R1C2 (
1
) R1
R2C2
1 1
Phase : CEA 180 tan ( ) 90 tan ( )
0 0

z p

1 1
= 270 tan ( ) tan ( )
0

z p
CH9-98
Type 2 CEA Design Procedure
1. Choose desired crossover freq. of total open-loop
T.F., usually around an order of magnitude less
than converter switching freq.
2. Except for CEA, determine all units TF & freq.
response that in control circuit
3. Determine mid-frequency gain of CEA required
to achieve overall desired crossover freq., this
obtain R2/R1 ratio
4. Choose desired phase margin needed to assure
stability, typically > 450. From middle-freq. gain
obtain R1, R2; C1, C2 are determined by pole & zero
CH9-99
 K-Factor Method
11
Phase : CEA = 270 tan ( ) tan ( )
0

z p
Phase angle of CEA at crossover freq. is
cross
1 1 cross
CEAcross 270 tan (
0
) tan ( )
z p
cross p
Let K
z cross
1 1 1
CEAcross 270 tan K tan ( )
0

K
Pole & zero freq. selectionK-factor method (D. Venable, The K factor: A
New Mathematical Tool for Stability Analysis and Synthesis, Proceedings
Powercon, 1983) CH9-100
 K-Factor Method
Using trigonometric identity
1 1 1 1
tan ( x ) tan ( ) 90 tan ( ) 90o tan 1 ( K )
1 o

x K
1 1
CEAcross 270 tan K tan ( ) 2 tan 1 ( K ) 360 o
0 1

K
2 tan 1 ( K ) (1)
CEAcross
K tan (2)
2
from (1), 0o CEAcross 180o for 0 K
CEAcross PM converter (3)
The K can be calculated from (2) if the CEA-cross is determined
from (3). Where PM is the desired phase margin
CH9-101
 K-Factor Method
Accordingto desired phase margin (PM ) and control
loop phase shift (converter ), the needed CEA-cross can
be obtained form (3), then K is determined by (2)
cross & K are known, then z & p can be obtained,
If
C1, C2 are then found
cross p
K
z cross
1 cross K
z C1
R2C1 K cross R2
1 1
p K cross C 2
R2C 2 cross R2 K
CH9-102
 Design Example: Type 2 CEA
A Buck converter: Vs=10V, Vo=5V, fs=100 kHz,
L=100 H with SR=0.1, C=100F with ESR = 0.5
, R = 5 , VP = 3V in PWM circuit. Design a type
2 CEA that results in a stable control system (PM
450).
Solution
1. Let fco=10 kHz < fs
2. Pspice simulation shows that (at 10 kHz): power
stage & filter gain: 2.24 dB, phase angle: -1010 ,
PWM gain=1/VP=1/3=-9.54 dB. The combined
gain= 2.24 dB+(-9.54 dB)=-11.78 dB (= G1) CH9-103
Design Example: Type 2 CEA

3. CEA should have a Mid-freq. gain

+11.78 dB (at 10 kHz) to make loop
gain 0 dB, then
11.78
vc vc ( )
11.78 dB 20log 10 20
3.88
vo vo
R2
3.88 Let R1 1k, then R2 3.88k
R1

CH9-104
 Design Example: Type 2 CEA
4. PM=450, converter= -1010 , then

CEA-cross= PM - converter =450 + 1010 = 1460

CEAcross 146 0

K tan tan 3.27
2 2
K 3.27
C1 13.4nF
2f co R2 2(10k )(3.88k )
1 1
C2 1.25nF
2f co R2 K 2(10k )(3.88k )3.27
CH9-105
 Implemented Type 2 CEA circuit

C2 = 1.25 nF

R2 = 3.88 k
R1=1 k
C1 = 13.4 nF
V0
VC
+
V0,ref

A Pspice simulation of the implemented control loop

gives a crossover frequency of 9.41 kHz and a phase
margin of 460
CH9-106
Pspice Simulation

CH9-107
 Type 3 CEA Design

Type 2 CEA is sometimes not capable of

providing sufficient phase margin (PM )
greater than 450 for stability criterion
Type 3 CEA provides an additional phase
angle boost compared to type 2 CEA and is
used when an adequate PM is not
achievable by using type 2 CEA

CH9-108
Small-signal Transfer Function for
Type 3 CEA

1 1 1 1
R
2
/ / s s
vc ( s) Zf sC sC R R3
R C
2 1 R R C
1 2 1 3
( )
GCEA ( s) 1 3

vo ( s) Zi 1 R1R3C2 C1 C2 1
R1 / / R3 s s s
sC 3 R C C
2 1 2 R C
3 3

(1)

CH9-109
 Vref is dc and has no effect on small-signal TF.
Assuming C2 << C1 & R3 << R1, then

1 1 1 1
s s s s
R1 R3 R2C1 ( R1 R3 )C3 1 R C
2 1 R C
1 3
GCEA ( s) ( 2)
R1R3C2 C1 C2 1 R3C2 1 1
s s s s s s
R C C
2 1 2 R C
3 3 R C
2 2 R C
3 3

There are 2 zeros and 3 poles

CH9-110
 There are 2 zeros and 3 poles in the G(s)
1 1
s s
For C2 << C1 & R3 << R1 GCEA ( s)
1 R2C1 R1C3
R3C2 1 1
s s s
j z1 j z 2 R2C2 R3C3
1
GCEA ( s j) (3)

R3C2 jp1 j p 2 j p 3
1 1
1 1 1 s s
z1 , z 2 G ( s)
v ( s)

R R
c 1 3
R2C1 ( R1 R3 )C3
R2C1 ( R1 R3 )C1 R1C3
CEA
v ( s) RRC C C2 1
o 1 3 2
s s 1 s
R2C1C2 R3C3
C1 C2 1 1
p1 0 , p 2 , p 3
R2C1C2 R2C2 R3C3
from (3), phase angle of the CEA
1 1 1
1

CEA 180 tan
0
tan 90 tan
0
tan
z1 z 2 p 2 p 3
1 1 1
1

270 tan
0
tan tan tan ( 4)
z1 z 2 p 2 p 3
CH9-111
 Type 3 CEA Design

The k-factor method can be used for type 3

in a similar way as it was used in type 2
The zeros are placed at the same frequency
to form a double zero
The 2nd & 3rd poles are placed at the same
frequency to form a double pole
i.e. z = z1 = z2 , p = p2 = p3 , p1 = 0

CH9-112
 Type 3 CEA Design
The double zeros & poles are placed at frequencies
GCEA ( s j)
1 j z1 j z 2
co
(3)

R3C2 jp1 j p 2 j p 3
z , p co K (5)
K type 2

j z
2 1
z cross
1
From (3), GCEA ( j)
R2C1 K

R3C2 j j
2 1
p K cross
p R2C 2

jco z
2
1
At crossover freq. GCEA ( jco )
R3C2 j j
2
co co p

The CEA phase at crossover freq.

co
1

1 co

CEAco 270 2 tan
0
2 tan ( 6)
z p CH9-113
 Type 3 CEA Design
co
1

1 co

CEAco 270 2tan
0
2tan
z p
co
1 1
co
From (5), CEA -co 270 2tan 2tan
/ K K
0

co co
1 1 1
270 2 tan K tan
0

K
1 1 1 1 1
tan x tan 90 tan
0
90 0 tan1 K
x K
CEA -co 900 4tan1 K
2
CEA -co 90
0
K tan (7)
4
CEA -co 900 ~ 270 0 for 0 K CH9-114
 Type 3 CEA Design
The maximum angle of the type3 CEA is 2700, but
the type2 is 1800 1 1 1
z1 , z 2
R2C1 ( R1 R3 )C1 R1C3
C C2 1 1
p1 0, p 2 1 , p 3
CEA -co PM converter (8) R2C1C2 R2C2 R3C3

At the crossover freq. (middle freq.: co z , co p )

jco z jco 1 jco

2 2
1 1
GCEA ( jco ) (9)

R3C2 j j R3C2 j R3C2
2 2 2
co co p co p p

K 1 1 1
From (5), co K z , p 2p
R1C3 R2C2 R3C3 R2C2 R3C3
K
j
1 jco 1 R1C3 R2
GCEA ( jco ) ( j K ) (10)

R3C2 2
p
R3C2 1
R2C2 R3C3
R1
CH9-115
 Type 3 CEA Design
1 jco j KR2 R2 GCEA ( jco )
GCEA ( jco ) (11)

R3C2 2
p
R1 R1 K

First choose R1 and then compute R2 from (11)

Other component values can be found by
co 1 1 1 1
z , p co K
K R2C1 R1C3 R2C2 R3C3
G( jco ) R1 K K 1 1
R2 , C1 , C2
K co R2 2fco R2 co R2 K 2fco R2 K
K K 1 1
C3 , R3
co R1 2fco R1 coC3 K 2fcoC3 K
CH9-116
 Design Example: type 3 CEA
A Buck converter: Vs=10V, Vo=5V, fs=100 kHz, L=100
H with SR=0.1, C=100F with ESR = 0.1 , R = 5
, VP = 3V in PWM circuit. Design a type 3 CEA
that results in a stable control system (PM 450).

Solution
1. Select fco=10 kHz < fs
2. Pspice simulation shows that (at 10 kHz): power
stage & filter gain: 10.5 dB, phase angle: -1440 ,
PWM gain=1/VP=1/3=-9.5 dB. The combined gain
= 10.5dB+(-9.5 dB)=-20 dB (= G1)
CH9-117
 Design Example: type 3 CEA

3. PM=450, converter= -1440 , then

CEA-cross= PM - converter =450 + 1440 = 1890

2
CEAcross 90

0 2
K tan tan 69.75 7.35
0

CH9-118
 Design Example: type 3 CEA

4. CEA should have a Mid-freq. gain +20 dB

(at 10 kHz) to make loop gain 0 dB, then
20
( )
20 dB 20 log GCEA ( jco ) GCEA ( jco ) 10 20
10
1 jco j K R2 R2 GCEA ( jco )
GCEA ( jco )

2
R3C2 R1 R1 K
p

R2 GCEA ( jco ) 10
3.6885
R1 K 7.35
R2
3.7 Let R1 1k , R2 3.7 k
R1
CH9-119
 Design Example: type 3 CEA
5. Calculating the other component values

K K 7.35
C1 11.6nF
co R2 2fco R2 2(10k )(3.7k )
1 1 1
C2 1.58nF
co R2 K 2fco R2 K 2(10k )(3.7k ) 7.35
K K 7.35
C3 43.1nF
co R1 2fco R1 2(10k )(1k )
1 1 1
R3 136
coC3 K 2fcoC3 K 2(10k )( 43.1n ) 7.35
CH9-120
 Design Example: type 3 CEA
6. Implemented type 3 CEA

C2=1.58nF

C3=43.1nF R =3.7k
R3=136 2

C1=11.6nF

R1=1k

CH9-121
 Design Example: type 3 CEA

A Pspice simulation of the implemented

control loop gives a crossover frequency of 10
kHz with a phase margin of 490
Notethat attempting to use type 2 CEA for this
converter is unsuccessful because the required
phase angle (1890) is greater than 1800
Comparing this converter with previous type 2
example, the ESR of the capacitor is smaller.
Low capacitor ERS often necessitate use of the
type 3 rather than type 2 CEA
CH9-122
Flyback in CCM: CEA Design
May be necessary to use an CEA has two pairs
of poles & zeros (type III) in addition to the
pole at origin for a proper compensation
C2
R3 C3
R2 C1
R1
V0
VC
+
V0,ref
type III CEA
CH9-123
 Exercise: CCM Flyback CEA
Design
A flyback converter the Bode plots of Tp(s) are given,
Tm(s)=-9.37 dB. The crossover freq. and phase margin
are required to be 5103 rad/s and 30o, respectively.
a. Is the type II CEA suitable for compensation
effectively? If not, why?
b. Designing a type III CEA to meet the above
requirements. [reference: R. P. Severns & G. E. Bloom,
Modern DC-to-DC switch Mode Power Converter
Circuits, Van Nostrand reinhold, New York, 1985. ]
CH9-124
Exercise: CCM Flyback CEA Design

C2
R3 C3
R2 C1
R1
V0
VC
+
type III CEA
V0,ref
CH9-125
Manual Placement of Poles &
Zeros in Type 3 CEA
In addition to the K-factor method, the poles &
zeros assignment at specified frequencies can be
used to design the type 3 CEA
A frequency of particular interest is the resonant
frequency of the LC filter in the converter (neglect
any resistance in the L & C)

1 1
LC fLC
LC 2 LC
CH9-126
 Zero or Pole Expression Placement
First zero z1 = 1/R2C1 50% to 100% of LC
Second zero z2 = 1/(R1+R3)C3 1/R1C3 At LC
First pole p1 = 0 --
Second pole p2 = (C1+C2)/R2C1C2 At the ESR zero = 1/rCC
1/R2C2
Third pole p3 = 1/R3C3 At one-half the switching
frequency, 2(fsw/2)

The 1st zero is commonly placed at (50~100%) of fLC

The 2nd zero placed at fLC
The 2nd pole placed at ESR zero of the filter TF,
1/rCC
The 3rd pole placed at (1/2) fsw
CH9-127
More about other compensators (type I, II,
III, ), please refer to

Abraham I. Pressman, Keith Billings, Taylor

Morey , Switching Power Supply Design/
Ch12, Third Edition, 2009.

CH9-128
G1 G2

CH9-129
CH9-130
CH9-131
CH9-132
CH9-133
CH9-134
CH9-135
CH9-136
CH9-137
CH9-138
Neglet the injection source impedance. The current source is converted into
voltage source using Thevenin-equivalent circuit

CH9-139
i ( s) v z ( s) G1v e ( s) , i ( s) v z ( s)
y x
Z1 Z2
Z
Z1
G

v z ( s) Z2ix ( s) iy ( s) 2 ix ( s) 1 HG2 Z2ix ( s)
Z1

iy ( s) Z2 Z2 Z1 Z2
Ti ( s) (1 G1HG2 ) (1 T ( s) )
i ( s) Z1 Z1 Z2
x

Z2 Z2
T ( s) 1
Z1 Z1 CH9-140
CH9-141
CH9-142
CH9-143
CH9-144
CH9-145