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Input/Output Organization: Accessing I/O Devices I/O Interface Input/output Mechanism
Input/Output Organization: Accessing I/O Devices I/O Interface Input/output Mechanism
I/O interface
Input/output mechanism
Memory-mapped
y pp I/O
/
Programmed I/O
Interrupts
Direct Memory Access
Buses
Synchronous Bus
Asynchronous Bus
I/O in CO and O/S
Programmed I/O
Interrupts
DMA (Direct memory Access)
A bus is a shared communication link,, which uses one
set of wires to connect multiple subsystems.
Address Decoder
Control Circuits
Data registers
Status registers
Memory
Address
Processor Data
Control
I/O
/O
Address
Add Control
C t l Data
D t andd status
t t
Interface
Decoders circuits registers
Input
p device (s)
( )
Memory mapped I/O
Input Output
Programmed I/O
mechanism
h i
Interrupts
Reason why
R h b
bus ddesign
i is
i so difficult
diffi lt :
- the maximum bus speed is largely limited by physical
factors: the length of the bus and the number of devices.
These physical limits prevent us from running the bus
arbitrarily fast.
DataRdy:
D t Rd Used
U d tot indicate
i di t that
th t the
th data
d t word
d is
i now ready
d on the
th
data lines; asserted by: Output/Memory and Input/I_O Device.
Memory
- Move DATAIN, R0
reads the data from DATAIN and stores them into processor
register R0;
User p
programs
g are p
prevented from issuing
g I/O
/
operations directly because the OS does not provide access to
the address space assigned to the I/O devices and thus the
addresses are protected by the address translation.
DATAOUT
7 6 5 4 3 2 1 0
Interrupt-driven
Interrupt driven I/O,
I/O employs I/O interrupts to
indicate to the processor that an I/O device needs attention.
Pull-up
Pull up
resister
Supply
pp y
R
INTR Pull-up
Processor resister
INTR
Enabling and Disabling Interrupts
Device activates interrupt signal line and waits with this
signal activated until processors attends
What
h if the
h same d
device
i iinterrupts again,
i within
i hi an ISR ?
Disabling Interrupts
Processor automatically disables interrupts before
starting the execution of the ISR
The processor saves the contents of PC and PS (status
register) before performing interrupt disabling.
The interrupt-enable is set to 0 no further interrupts
allowed
When return from interrupt instruction is executed the
contents of the PS are restored from the stack, and the
interrupt enable is set to 1
Special
p Interrupt
p line
Multiple
p devices can initiate interrupts
p
They
y uses the common interrupt
p request
q line
Techniques
q are
Polling
Vectored Interrupts
p
Interrupt Nesting
Daisy
y Chaining
g
Polling Scheme
Pre
Pre-Emption
Emption of low priority Interrupt by another high
priority interrupt is known as Interrupt nesting.
Disabling
Di bli I t
Interrupts
t during
d i th execution
the ti off the
th ISR
may not favor devices which need immediate attention.
INTR1 INTRp
ocessor
INTA 1 INTA p
Organizing
g g I/O
/ devices in a p
prioritized structure.
INTR
Processor
r
..
P
D i 1
Device D i 2
Device D i
Device n
INTA
Daisy Chaining with Priority Group
Combining Daisy chaining and Interrupt nesting to form
priority
p yggroup
p
Each group has different priority levels and within each
group devices are connected in daisy chain way
INTR1
cessor
Device 1 Device 1
INTA 1
. ..
.
Proc
INTR p
D i 1
Device D i 1
Device
INTA p
Priority arbitration circuit
The
h word
d count
Starting address
Word count
In DMA interface
g
First register stores the starting
g address
Second register stores Word count
Third register contains status and control flags
Bits and Flags 1 0
R/W READ WRITE
Done Data transfer finishes
IRQ Interrupt request
IE Raise interrupt (enable) after Data
Transfer
Processor Main memory
Disk/DMA DMA
Printer Keyboard
controller controller
Network
Disk Disk Interface
Conflicts in DMA:
The next device can take control of the bus after the
current master relinquishes control
BR
Processor
P r
DMA DMA
controller 1 controller 2
BG1 BG2
BR
Processor
DMA DMA
controller 1 controller 2
BG1 BG2
- The full
full-speed
speed rate of 12 Mbit/s (
(~1.43
1.43 MB/s) is the
basic USB data rate defined by USB 1.1. All USB hubs support
full-bandwidth.
SuperSpeedd (USB
( 3.0)
) rate produces
d upto 4800 Mbit/s
bi /
(~572 MB/s or 5 Gbps)
Each node of the tree has a device called a hub, which
acts as an intermediate control point between the host and
the I/0 devices.
devices
At the root of the tree, a root hub connects the entire
tree to the host computer.
p The leaves of the tree are the I/0
/
devices being served. The tree structure enables many
devices to be connected while using only simple point-to-
point serial links.
Each hub has a number of ports where devices may be
connected, including g other hubs. In normal operation, a hub
copies a message that it receives from its upstream
connection to all its downstream ports.
As a result,
A lt a message sentt b
by the
th host
h t computer
t is
i
broadcast to all I/O devices, but only the addressed device
will respond to that message.
A message from an I/O device is sent only upstream
towards the root of the tree and is not seen by other devices.
H
Hence, th
the USB enables
bl th
the h
hostt tto communicate
i t with
ith the
th I/O
devices, but it does not enable these devices to communicate
with each other.
The USB operates strictly on the basis of polling. A
device may send a message only in response to a poll
message from the host.
host
USB protocols
and
USB FRAME