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Nhap Mon PIC PDF
Nhap Mon PIC PDF
I. PHN L THUYT
Hin nay c kh nhiu dng PIC v c rt nhiu khc bit v phn cng, nhng
chng ta c th im qua mt vi nt nh sau :
l i din cho cc chn cng A, PORTB l i din cho cc chn cng B v.v. Cc
thanh ghi ny c a ch xc nh v khng c dng cho cc mc ch khc
Cc thanh ghi a mc ch c dng t bin trong mt chng trnh ng
dng ca vi iu khin. Nhn vo bn b nh RAM, ta thy bin c th t t
a ch 20F n 7Fh trong bank nh 0, A0h-EFh, 120h-16Fh, 1A0h-1EFh.
Tr li vn v cc cng, ti y ta c th a ra nhn xt:
Thanh ghi PORTA phn nh trng thi ca cc chn cng A, ngha l mun tn hiu u
ra ca cc chn cng A nh th no ta ch vic a gi tr vo cc bit tng ng trn
thanh ghi PORTA. Cng nh khi c gi tr ca thanh ghi PORTA ta s bit c trng
thi ca cc chn cng A.
V d:
Mun RA0 mc logic 1 (mc 5V), RA1 mc logic 0 (mc 0V), RA2 mc logic 1,
RA3 mc logic 0, RA4 mc logic 1, RA5 mc logic 1, ta ch vic gn gi tr
000110101 cho thanh ghi PORTA.
X X 1 1 0 1 0 1
RA5 RA4 RA3 RA2 RA1
RA0
X: khng quan tm.
Tng t nh vy vi PORTB,PORT C,PORTD,PORTE.
Tnh a chc nng ca mt chn trn vi iu khin:
Nhn vo s chn ca vi iu khin, ta c th thy mt s chn ca vi iu khin c
tn gm nhiu phn vi du gch cho. V d: RA0/AN0, RC7/RX/DT, RC6/TX/CK
y chnh l tnh a chc nng ca mt chn trn vi iu khin hay cn gi l s dn
knh.
ngha ca n l:
Bnh thng nu khng c ci t th tc c cc chn trn 5 cng A, B, C, D, E l cc
chn vo ra s I/O.
Nu trong chng trnh ta c ci t mt chc nng no nh RS232, ADC hoc PWM
v.v th cc chn tng ng vi chc nng s hot ng theo chc nng . Khi
chn ny s khng c dng lm chn vo ra s nh bnh thng na.
V d: bnh thng chn RA0/ANO l chn vo ra s RA0, nu chc nng ADC vi knh
vo tn hiu analog l knh 0 c ci t khi chn RA0 /AN0 s l chn vo ca b
ADC, tc l hot ng theo chc nng AN0.
Tng t nh vy, khi ci t giao tip vi thit b ngoi vi theo chun RS232, chn vo
ra s RC7/RX/DT s hot ng nh u vo d liu RS232 tc l chc nng RX ca
chn ny.
Gi d nh l:
chn RB.m (m=0-7) l u ra, tc Output th gi tr TRISB.m l 0
L u vo, tc Input th gi tr TRISB.m l 1
Tng t nh vy i vi cc chn trn cc cng cn li
2. Ngn ng lp trnh cho vi iu khin PIC- CCS:
2.1 Cc ngn ng lp trnh cho vi iu khin PIC:
Ngn ng lp trnh cho vi iu khin PIC c 2 loi:
- Ngn ng lp trnh cp thp- Hp ng: c phn mm MPLAB
- Ngn ng lp trnh bc cao: c nhiu loi, c pht trin theo ngn ng C, nh:
CCS, HTPIC, PIC BASIC v.v
u im ca hp ng l gip ngi hc v lp trnh hiu r hn v cu trc bn trong ca
vi iu khin PIC, cng nh ti u ha b nh chng trnh. Tuy nhin, nhn chung
phng php tip cn hp ng l kh v kh nng pht trin ng dng l hn ch, mt
delay_ms(2);// S dng hm to tr 2 ms
output_high(PIN_A4); // s dng hm a gi tr chn RA4 ln mc cao
output_b((MAP[n%10]) ^ 0x00);
output_low(PIN_A5);
delay_ms(2);
output_high(PIN_A5);
}
// Kt thc chng trnh con hin th
//============================================
// Bt u chng trnh chnh
// y l ni vi iu khin bt u chy lnh
//============================================
void main()
{
int i,count;
count=0;
while(TRUE)
{
for (i=0;i<=50;i++)
display(count); // dispay 50 times
count=(count==99) ? 1: count+1;
}
}
2.2.2 Cu trc ca mt chng trnh vit bng CCS:
2.2.2.1 Khai bo tin x l:
Bt u mt chng trnh vit bng ngn ng CCS l phn khai bo tin x l:
1. u tin l phn khai bo file header: #include <tn chip dng.h>
V d: # include <16f877a.h>
Vic khai bo ny thc cht l chp c file 16f877a.h vo chng trnh ny.
}
Cng nhc li l trong mt chng trnh CCS , vi iu khin s chy t chng trnh
chnh, hay ni cch khc l t dng lnh u tin sau void main().
Cc chng trnh con ch c gi ti cc li gi chng trnh con trong chng trnh
chnh hoc t cc chng trnh con khc. Chng trnh con phc v ngt ch c chy
khi c ngt xy ra, v ngt c cho php (s bn k hn trong cc bi hc sau).
2.2.3 Cc cu trc thut ton ca ngn ng CCS:
Cu trc thut ton ca ngn ng CCS k tha 100% t ngn ng C. y xin nhc li
mt s cc cu trc hay dng:
- Cu trc IF:
o If (biu thc)
Lnh1;
Else lnh2;
V d: if (x==25)
x=1;
else
x=x+1;
- Cu trc lp While:
o While (biu thc)
{
Cc lnh;
}
V d: While (count<20)
{
Output_B(count);
Count=count+1;
}
Ch : while(1) s thc hin cc lnh trong khi while ny mi mi
- Cu trc lp FOR:
V d: for (i=1;i<=10;++i)
A=a+i;
V d: switch (cmd)
break;
break;
default:printf("bad cmd");
break;
PHN L THUYT:
Hin nay, trong hu ht cc thit b nhng u c s dng cc khi hin th. Mc ch cho ngi
dng gim st, ci t v hin th cc thng s ca thit b cng nh i tng cn gim st iu
khin.
- Hin th cnh bo, bo li: thng thng dng led n. C th hin th theo kiu dng
nhiu mu khc nhau hoc bt tt v.v
- Hin th s liu: dng led 7 on, LCD hoc LCD ha v.v
- Hin th trn my tnh: dng cc phn mm iu khin gim st, kt ni thit b v my
tnh thng qua chun RS232 hoc cc chun mng (gim st t xa)
Trong bi ny s gii thiu 2 cch hin th u, phn hin th bng my tnh s c cp trong
bi hc v chun giao tip RS232.
Thng thng cch hin th ny dng bo mt trng thi no y ca thit b nh trng thi
lm vic ca ngun (li hoc khng li), cng nh cc khi chc nng khc.
C rt nhiu loi led n dng hin th. Phng php n gin nh sau:
Suy ra, in p ri trn tr l 3V. Dng qua led chnh l dng qua in tr v bng 15mA.
(in tr tiu chun: 10, 11, 12, 13, 15, 16, 18, 20, 22, 24, 27, 30, 33, 36, 39, 43, 47, 51, 56, 62,
68, 72, 82, 91 v cc bi s)
C 2 loi:
Nh gii thiu phn trn, thc cht led 7 on gm 8 hoc 7 led n ni vi nhau. V vy
iu khin thanh led n sng, cch thc hin phn cng nh hnh 2.1.
Nh trn hnh 2.4 trn, led 7 on hin th s 2 th cc led a,b,d,e,g sng; cc led c, f tt. Gi tr
sng tng ng chn vi iu khin ni vo mc 0, gi tr tt tng ng vi chn vi iu khin
ni vi mc 1.
0 0 1 0 0 1 0 0
y l m led 7 on ca s 2
M led tng ng vi cc s t 0 n 9 l:
0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90
i chiu vi cch hin th 1 led 7 on, ta ngh n gin ch l dng 1 cng hin th s 3, 1 cng
khc hin th s 5.
Nh vy ta mt 2 cng. Hin th 4 led th mt 4 cng => ton b chn trn vi iu khin dng cho
vic hin th ledKhng cn chn giao tip vi cc thit b khc nh bn phm, u vo s
khc v.v Khng kh thi!
Chn ngun ca 2 led c iu khin bi 2 chn trn vi iu khin, chng hn chn RA4 v
RA5 nh trn hnh, thng qua cc B ca 2 transistor pnp.
- Cho chn RA4 (chn ni vi led hng chc) xung mc thp, transistor th nht m do
tip gip BE thun, chn RA5 ln mc cao (chn ni vi led hng n v), transistor th
hai khng m. Vy ch c led hng chc c cp ngun.
- Cho cng B xut d liu m led ca s 3. Ch c led hng chc c cp ngun nn ch
c led ny sng
- To thi gian tr 10-20ms
- iu khin tng t cho led hng n v c cp ngun, led hng chc khng cp
ngun, xut d liu m led s 5 ra cng B. Led n v hin th s 5.
- To thi gian tr 10-20ms
- Quay li bc th nht
Nh vy, s 3 hin th 10ms, s 5 hin th 10ms v quay vng nh vy. Thi gian ny rt nhanh,
do hiu ng ca mt, ta cm gic nh s 35 hin th cng lc. Bi ton c gii quyt, ta ch mt
c 10 chn iu khin 2 led.
Cng gii thch thm l do dng transistor ni vo RA4, RA5. Do chn vi iu khin c dng
khong vi chc mA, y l chn cp ngun cho led 7 on, mi led n trong Led 7 on mt
20mA vy c led 7 on mt trn 100mA. V vy ta phi dng transistor khuch i dng.
LM016L
VDD
VSS
VEE
RW
RS
D0
D1
D2
D3
D4
D5
D6
D7
E
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Hnh 2.6: Cc chn LCD
VSS: Chn t
RS:
R/W:
E: Chn cho php (Enable). Sau khi lnh hoc d liu c chun b trn ng d
liu, to xung mc cao-mc thp s bt u qu trnh LCD nhn d liu hoc lnh t vi
iu khin.
M lnh nh gii thiu trong phn trn ty thuc vo tng lnh, y gii thiu mt s lnh
c bn nh sau:
. Lnh ci t ch lm vic:
0 0 1 DL N F - -
DL:
= 1: 8 bit
= 0: 4 bit
N:
= 1: 2 dng
= 0 1 dng
F:
0 0 0 0 0 1 I/D S
I/D:
= 1 tng a ch
= 0 gim a ch
S:
0 0 0 0 1 D C B
C: ci t hin th con tr
B: nhp nhy v tr k t
. Lnh t v tr hin th ca k t:
1 C C C C C C C
a ch dng 1: 00- 0F
a ch dng 2: 40-4F
Qu trnh gi k t gm cc bc sau:
File: LCD_lib_4bit:
#include <stddef.h>
#separate void LCD_SetPosition ( unsigned int cX );//Thiet lap vi tri con tro
#separate void LCD_PutChar ( unsigned int cX );// Ham viet1kitu/1chuoi len LCD
#separate void LCD_PutCmd ( unsigned int cX) ;// Ham gui lenh len LCD
#separate void LCD_SetData ( unsigned int cX );// Dat du lieu len chan Data
LCD_SetData ( 0x00 );
LCD_PulseEnable();
LCD_PulseEnable();
LCD_PulseEnable();
LCD_PulseEnable();
LCD_SetData ( swap ( cX ) );
LCD_PulseEnable();
output_high ( LCD_RS );
LCD_PutCmd( cX );
output_low ( LCD_RS );
LCD_PulseEnable();
LCD_PulseEnable();
output_high ( LCD_EN );
delay_us ( 3 ); // was 10
output_low ( LCD_EN );
delay_ms ( 3 ); // was 5
LCD1
LM016L
C1
30pF UDK
X1 13
OSC1/CLKIN RB0/INT
33
VDD
VSS
VEE
RW
14 34
RS
D0
D1
D2
D3
D4
D5
D6
D7
CRYSTAL OSC2/CLKOUT RB1
C2
E
35
RB2
2 36
RA0/AN0 RB3/PGM 1
2
3
4
5
6
7
8
9
10
11
12
13
14
3 37
RA1/AN1 RB4
30pF 4 38
RA2/AN2/VREF-/CVREF RB5
5 39
RA3/AN3/VREF+ RB6/PGC
6 40
RA4/T0CKI/C1OUT RB7/PGD
7
RA5/AN4/SS/C2OUT
15
RC0/T1OSO/T1CKI
8 16
RE0/AN5/RD RC1/T1OSI/CCP2
9 17
RE1/AN6/WR RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL
23
RC4/SDI/SDA
1 24
MCLR/Vpp/THV RC5/SDO
25
RC6/TX/CK
R9 RC7/RX/DT
26
4K
19
RD0/PSP0
20
RD1/PSP1
21
RD2/PSP2
22
RD3/PSP3
27
RD4/PSP4
28
RD5/PSP5
29
RD6/PSP6
30
RD7/PSP7
PIC16F877A
#include <16f877A.h>
#include "LCD_LIB_4BIT.c"
VOID MAIN()
LCD_INIT();
LCD_PUTCHAR('X');
DELAY_MS(1000);
LCD_PUTCHAR('I');
DELAY_MS(1000);
LCD_PUTCHAR('N');
DELAY_MS(1000);
LCD_PUTCHAR(' ');
DELAY_MS(1000);
LCD_PUTCHAR('C');
DELAY_MS(1000);
LCD_PUTCHAR('H');
DELAY_MS(1000);
LCD_PUTCHAR('A');
DELAY_MS(1000);
LCD_PUTCHAR('O');
Lp trnh thc hin hin th h tn, thay i cc ch hin th bng cch gi lnh ln LCD
BI 3: B NH THI - TIMER
Trong cc ng dng ca vi iu khin trong thc t, vic nh thi (to mt khong thi gian gia
2 s kin) cc thao tc l vic thng xuyn xy ra.
3.2.1 Ch nh thi:
Ngc li, ta mun thc hin nh thi khong thi gian t sau mt s kin 1 nh sau:
- S kin 1
- To khong thi gian tr t
- S kin 2
Ta lm cc bc:
- S kin 1
- Gn gi tr ban u cho TMR =
- Kim tra bit c
- Khi bit c = 1, thc hin s kin 2.
Vy khong thi gian t sau s kin 1 (khi TMR bt u c gn) n s kin 2 (ngay sau khi
bit c c set) l t ng nh yu cu ca ta.
V d: nh thi 200 (s) dng Timer0 (8 bit; n=1; gi tr ti a l 255) ta cho TMR0= 255-
200=55 ri bt u cho m ln.
3.2.2 Ch b m:
Khi c ci t trong ny, mt chn chc nng trn vi iu khin s tr thnh chn u vo xung
ca b m. V d: chn RA4 i vi Timer0 v RC0 i vi Timer1. Hot ng ca n c nt
ging vi ch nh thi.
3.3 Timer 0:
hot ng ch nh thi, ta cho bit T0CS (bit 5 ca thanh ghi Option_Reg) mc 0. Khi
, gi tr ca thanh ghi TMR0 s t ng tng ln 1 n v sau mi chu k lnh ca vi iu khin.
Lu l ngi lp trnh phi xa TMR0IF bng chng trnh ( ghi nhn ng cc ln trn k
tip).
Ngoi ra, tng thi gian nh thi hoc s xung m u vo ti a ca Timer 0, vi iu khin
cn cho php vic la chn t l Prescale cho u vo ca Timer 0 bng 3 bit PS2-PS0 (bit 2-0
ca thanh ghi
Nh vy, thi gian nh thi ti a cng nh s xung m c khi TMR0 trn s tng ln 64 ln.
Tng t vi cc t l khc.
= 1: TMR0 hot ng ch b m
= 0: Xung sn ln
= 1: Xung sn xung
Bit TMR0IE: Bit ny bng 1 cho php ngt Timer 0. S kin ngt xy ra khi c s trn
TMR0 t 255 xung 0.
- RTCC_INTERNAL: ch nh thi
- RTCC_EXT_L_TO_H: ch b m vi xung dng sn ln
- RTCC_EXT_H_TO_L: ch b m vi xung dng sn xung
3.4 Timer 1:
- TMR1CS = 0: Ch nh thi
- TMR1CS = 1: Ch b m. C 2 dng c phn bit bi bit T1SYNC (bit 2 ca
T1CON)
o T1SYNC = 0: B m ng b
o T1SYNC = 1: B m khng ng b
T1CKPS1-T1CKPS0 T l chia tn s
00 1:1
01 1:2
10 1:4
11 1:8
- =1: RC1
- =0: RC0
- =1: Khng ng b
- =0: Khng ng b
- =1: Ch b m
- =0: Ch b nh thi
- =1: Bt Timer 1
- =0: Tt Timer 1
Bit TMR1IF l bit c ca timer 1. Bit c set ln gi tr 1 khi xy ra trn 2 thanh ghi TMR1L v
TMR2H t 65535 v 0.
BI TP:
C1
30pF
X1
CRYSTAL
C2
30pF
U1
13 33
14
OSC1/CLKIN RB0/INT
34
R1
OSC2/CLKOUT RB1
35
RB2 268
2 36
RA0/AN0 RB3/PGM
3 37
RA1/AN1 RB4
4 38 R2
RA2/AN2/VREF-/CVREF RB5
5 39
RA3/AN3/VREF+ RB6/PGC
6 40
RA4/T0CKI/C1OUT RB7/PGD 220
7
RA5/AN4/SS/C2OUT
15
RC0/T1OSO/T1CKI
8 16
9
RE0/AN5/RD RC1/T1OSI/CCP2
17
R3
RE1/AN6/WR RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL 222
23
RC4/SDI/SDA
R9 1
MCLR/Vpp/THV RC5/SDO
24
25
4K RC6/TX/CK
26
R4
RC7/RX/DT
220
19
RD0/PSP0
20
RD1/PSP1
21 R5
RD2/PSP2
22
RD3/PSP3
27
RD4/PSP4 220
28
RD5/PSP5
29 R6
RD6/PSP6
30
RD7/PSP7
220
PIC16F877A
R7
220
R8 Q1
PNP
4K
R10 Q2
PNP
10k
30pF
X1
C2 CRYSTAL
30pF
U1
13 33 R1
OSC1/CLKIN RB0/INT
14 34
OSC2/CLKOUT RB1
35
RB2 268
2 36
RA0/AN0 RB3/PGM
3 37
RA1/AN1 RB4
4 38 R2
RA2/AN2/VREF-/CVREF RB5
RC 5
RA3/AN3/VREF+ RB6/PGC
39
4K 6 40 220
RA4/T0CKI/C1OUT RB7/PGD
7
RA5/AN4/SS/C2OUT
15
RC0/T1OSO/T1CKI
8 16 R3
RE0/AN5/RD RC1/T1OSI/CCP2
9 17
RE1/AN6/WR RC2/CCP1
10 18 222
RE2/AN7/CS RC3/SCK/SCL
23
RC4/SDI/SDA
R9 1
MCLR/Vpp/THV RC5/SDO
24
4K 25 R4
RC6/TX/CK
26
RC7/RX/DT
220
19
RD0/PSP0
20
RD1/PSP1
21 R5
RD2/PSP2
22
RD3/PSP3
27 220
RD4/PSP4
28
RD5/PSP5
29 R6
RD6/PSP6
30
RD7/PSP7
220
PIC16F877A
R7
220
R8 Q1
PNP
4K
R10 Q2
PNP
10k
30pF
X1
CRYSTAL
C2
30pF
LCD1
U1 LM016L
13 33
OSC1/CLKIN RB0/INT +12v
14 34
OSC2/CLKOUT RB1
35
RB2 +12v
2 36
RA0/AN0 RB3/PGM
3 37
RA1/AN1 RB4
4 38
RA2/AN2/VREF-/CVREF RB5
VDD
VSS
VEE
5 39
RW
RS
D0
D1
D2
D3
D4
D5
D6
D7
RA3/AN3/VREF+ RB6/PGC
E
6 40
RA4/T0CKI/C1OUT RB7/PGD
7
RA5/AN4/SS/C2OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
RC0/T1OSO/T1CKI
15 RV?
8 16 1k
RE0/AN5/RD RC1/T1OSI/CCP2
9 17
RE1/AN6/WR RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL
23
RC4/SDI/SDA
1 24 +88.8
MCLR/Vpp/THV RC5/SDO
R9 RC6/TX/CK
25
4K 26
RC7/RX/DT
19
RD0/PSP0
20
RD1/PSP1
21
RD2/PSP2
22
RD3/PSP3
27
RD4/PSP4
28
RD5/PSP5
29
RD6/PSP6
30
RD7/PSP7
PIC16F877A
BI 4: NGT
4.1 Ngt l g:
Ngt hiu theo ngha n gin l cc s kin ngu nhin lm gin on qu trnh ca mt s kin
ang xy ra. c th d hiu khi nim mi ny ta cng a ra mt v d trong thc t nh sau:
V d: Trong gi hc trn lp, ta ang hc bi, c chung in thoi hoc c bn gi, ta phi
dng hot ng hc bi li tr li in thoi hoc ra gp bn. S kin in thoi reo chung,
hay bn b gi c gi l s kin ngt, vic ta tr li in thoi hay ra gp bn l chng trnh
phc v ngt. Vic ang hc bi c xem l chng trnh chnh.
Ngt c thc hin khi v ch khi ci t cho php n. Nh trong v d trn, nu s kin ngt-
in thoi reo xy ra, nu gio vin v bn thn ta cho php mnh tr li in thoi khi ang hc
bi th khi c in thoi ta mi nghe.
- Ngun ngt: ngun ngt l nguyn nhn gy ra ngt. Nh trong v d trn, ngun ngt c
th
L in thoi gi hoc bn gi
- Lp ngt c bn: bao gm cc ngt c bn nh ngt trn timer 0, ngt ngoi, ngt thay
i trng thi ca cc chn PortB (RB4-RB7). Bit cho php ngt v bit c tng ng l
#INCLUDE <16F877A.H>
#USE DELAY(CLOCK=8000000)
INT SODEM;
#INT_EXT
VOID NGATNGOAI()
CLEAR_INTERRUPT(INT_EXT);
DISABLE_INTERRUPTS(GLOBAL);
SODEM++;
ENABLE_INTERRUPTS(GLOBAL);
VOID HIENTHI(INT A)
HC=A/10;
HDV=A%10;
OUTPUT_LOW(PIN_A4);
OUTPUT_D(MAP[HC]);
DELAY_MS(15);
OUTPUT_HIGH(PIN_A4);
OUTPUT_LOW(PIN_A5);
OUTPUT_D(MAP[HDV]);
DELAY_MS(15);
OUTPUT_HIGH(PIN_A5);
VOID MAIN()
SET_TRIS_B(0xFF);
ENABLE_INTERRUPTS(INT_EXT);
EXT_INT_EDGE(H_TO_L);
ENABLE_INTERRUPTS(GLOBAL);
WHILE(1)
HIENTHI(SODEM);
Nh vy, lc vit chng trnh c dng ngt bng CCS, ta c nhng lu sau:
- Trong chng trnh chnh (main), chng ta ci t ngt: cho php ngt c th, cho php
ngt ton cc. i ngt
- Chng trnh con x l ngt l chng trnh con nm ngay sau ch th bin dch
#INT_XXX, trong XXX l tn ca ngt c th. V d: #INT_EXT: ngt ngoi
- Trong chng trnh con x l ngt: xa c ngt, cm ngt ton cc phng khi ang x
l ngt c ngt xy ra. Sau khi x l d liu trong chng trnh con x l ngt, ta cho
php ngt ton cc li.
Trong phn tip theo, ta s kho st mt s ngt tiu biu nh ngt ngoi INT, ngt thay i trng
thi cc chn cao PORTB, ngt trn Timer 0, ngt trn Timer 1. Cc ngt ngoi vi khc s c
nhc n khi nghin cu cc modun ngoi vi ny.
trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
#INT_EXT
- Xa c ngt: CLEAR_INTERRUPT(INT_EXT)
- Cm ngt ton cc, phng lc ang x l ngt, li c ngt xy ra:
DISABLE_INTERRUPTS(GLOBAL)
- X l ngt : ty thuc vo ca ngi lp trnh
- Cho php ngt ton cc: ENABLE_INTERRUPTS(GLOBAL)
- C ngt: bit c ngt ngoi l bit RBIF (bit 0 ca thanh ghi INTCON) c t ng set
ln 1 khi c s kin ngt ngoi xy ra. C ny phi c xa bng chng trnh (c th l
trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
#INT_RB
- Xa c ngt: CLEAR_INTERRUPT(INT_RB)
- Cm ngt ton cc, phng lc ang x l ngt, li c ngt xy ra:
DISABLE_INTERRUPTS(GLOBAL)
- oc cng B loi b trng thi mismatch
- X l ngt : ty thuc vo ca ngi lp trnh, ch n s ln ngt
- Cho php ngt ton cc: ENABLE_INTERRUPTS(GLOBAL)
- Ngun ngt: l trng thi trn ca thanh ghi b m timer 0, TMR0 vi iu khin PIC
- S kin ngt: s kin ngt xy ra khi c s trn ca TMR0, tc l khi TMR0=255 ri b
xa
- Bit cho php ngt: cho php ngt ny, bit cho php ngt TMR0IE (bit 5 ca thanh ghi
INTCON) phi c set ln 1. Ngoi ra, bit cho php ngt ton cc GIE (bit 7 ca thanh
ghi INTCON) cng phi c set ln 1.
- C ngt: bit c ngt ngoi l bit TMR0IF (bit 2 ca thanh ghi INTCON) c t ng set
ln 1 khi c s kin ngt ngoi xy ra. C ny phi c xa bng chng trnh (c th l
trong chng trnh con phc v ngt) vi iu khin qun l chnh xc cc ln ngt k
tip.
- Gn gi tr ban u cho thanh ghi TMR0, ty thuc vo thi gian m ngi lp trnh
mun (xem li bi 3): SET_TIMER0(gi tr)
- Cho php ngt timer 0: ENABLE_INTERRUPTS(INT_TIMER0)
- Cho php ngt ton cc: ENABLE_INTERRUPTS(GLOBAL)
#INT_TIMER0
- Xa c ngt: CLEAR_INTERRUPT(INT_TIMER0)
- Cm ngt ton cc, phng lc ang x l ngt, li c ngt xy ra:
DISABLE_INTERRUPTS(GLOBAL)
- X l ngt : ty thuc vo ca ngi lp trnh, ch n s ln ngt
- Gn li gi tr ban u cho thanh ghi TMR0 (ty thuc vo ca ngi lp trnh):
SET_TIMER0(gi tr)
BI TP:
R11
10K
U1
13 33 R1
OSC1/CLKIN RB0/INT
14 34
OSC2/CLKOUT RB1
35
RB2 268
2 36
RA0/AN0 RB3/PGM
3 37
RA1/AN1 RB4
4 38 R2
RA2/AN2/VREF-/CVREF RB5
5 39
RA3/AN3/VREF+ RB6/PGC
6 40 220
RA4/T0CKI/C1OUT RB7/PGD
7
RA5/AN4/SS/C2OUT
15
RC0/T1OSO/T1CKI
8 16 R3
RE0/AN5/RD RC1/T1OSI/CCP2
9 17
RE1/AN6/W R RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL 222
23
RC4/SDI/SDA
1 24
MCLR/Vpp/THV RC5/SDO
25 R4
RC6/TX/CK
26
RC7/RX/DT
220
19
RD0/PSP0
20
RD1/PSP1
21 R5
RD2/PSP2
22
RD3/PSP3
27 220
RD4/PSP4
28
RD5/PSP5
29 R6
RD6/PSP6
30
RD7/PSP7
220
PIC16F877A
R7
220
R8 Q1
PNP
4K
R10 Q2
PNP
10k
C1 R11 R12
10K 10K
30pF
X1
CRYSTAL
C2
30pF
U1
13 33 D1
14
OSC1/CLKIN RB0/INT
34
R1
OSC2/CLKOUT RB1
35
RB2 268
2 36 LED-RED
RA0/AN0 RB3/PGM
3 37
4
RA1/AN1 RB4
38
D2
5
RA2/AN2/VREF-/CVREF RB5
39
R2
RA3/AN3/VREF+ RB6/PGC
6 40
RA4/T0CKI/C1OUT RB7/PGD 220
7 LED-RED
RA5/AN4/SS/C2OUT
15
8
RC0/T1OSO/T1CKI
16
D3
9
RE0/AN5/RD RC1/T1OSI/CCP2
17
R3
RE1/AN6/WR RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL 222
23 LED-RED
RC4/SDI/SDA
R9 1
MCLR/Vpp/THV RC5/SDO
24
D4
4K 25 R4
RC6/TX/CK
26
RC7/RX/DT
220
19 LED-RED
RD0/PSP0
20
RD1/PSP1
21
D5
RD2/PSP2 R5
22
RD3/PSP3
27 220
RD4/PSP4
28 LED-RED
RD5/PSP5
29
D6
RD6/PSP6 R6
30
RD7/PSP7
220
PIC16F877A LED-RED
D7
R7
220
LED-RED
BI 5: IU CH RNG XUNG-PWM
Chu k xung chnh l khong thi gian t lc TMR2=0 cho n khi TMR2=PR2. Suy ra,
tng PR2 n v, hay chnh l chu k xung s bng:
N l t l chia tn s.
T=(255+1)*4*(1/4Mhz)*4=1024s
rng xung l gi tr 10 bit : trong 8 bit cao c ghi vo thanh ghi CCPR1L, v 2
bit thp ghi vo 2 bit 5 v 4 ca thanh ghi CCP1CON :
Gm cc bc:
C1
30pF
X1 UDK
C2 CRYSTAL
13 OSC1/CLKIN RB0/INT 33
14 34
OSC2/CLKOUT RB1
35
RB2
30pF 2 36
RA0/AN0 RB3/PGM
3 37
RA1/AN1 RB4
4 RA2/AN2/VREF-/CVREF RB5 38
5 39 LCD1
RA3/AN3/VREF+ RB 6/PGC LM016L
6 40
RA4/T0CKI/C1OUT RB 7/PGD
7
RA5/AN4/SS/C2OUT
15
RC0/T1OSO/T1CKI
+5V 8 RE0/AN5/RD RC1/T1OSI/CCP2 16
9 17
RE1/AN6/WR RC2/CCP1
10 18
RE2/AN7/CS RC3/SCK/SCL
23
RC4/SDI/SDA
VDD
VSS
VEE
RW
1 24
RS
D0
D1
D2
D3
D4
D5
D6
D7
MCLR/Vpp/THV RC5/SDO
E
25
RC6/TX/CK
26
RC7/RX/DT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
R9 RD0/PSP0
19
4K 20
RV1 RD1/PSP1
21
RD2/PSP2
22
RD3/PSP3
RD4/PSP4 27
28
RD5/PSP5
29
RD6/PSP6
30
RD7/PSP7
10K PIC16F877A
+12V
R6
2K2 U2
1 6
5
2
R5 Q5
4 NPN
1K
OPTOCOUPLER-NPN
Q2
NPN
R7
10k
+12V
R1 D32
2K2 U1 DIODE
1 6
R11
10k 5 +12V
2 R2 Q?
MPSA05
4 1K
OPTOCOUPLER-NPN
R3
10K RL?
OMI-SH-205D
D1
DIODE
+88.8
BI TP:
#include <16F877A.h>
#fuses HS,NOWDT,NOPROTECT,NOLVP
#use delay(clock=4000000)
#include <lcd_lib_4bit.c>
//#INCLUDE <KBD.C>
// Keypad layout:
{'4','5','6','7'},
{'8','9','A','B'},
{'C','D','E','F'}
};
if (input (row0) & input (row1) & input (row2) & input (row3))
return (0);
else
return (1);
char kbd_getc( ) {
byte kchar;
byte row;
kchar='\0';
if(++kbd_call_count>KBD_DEBOUNCE_FACTOR) {
switch (col) {
case 0 :
output_low(col0);
output_high(col1);
output_high(col2);
output_high(col3);
//DELAY_MS(1000);
break;
case 1 : output_high(col0);
output_low(col1);
output_high(col2);
output_high(col3);
break;
case 2 : output_high(col0);
output_high(col1);
output_low(col2);
output_high(col3);
break;
case 3 : output_high(col0);
output_high(col1);
output_high(col2);
output_low(col3);
break;
kbd_down=false;
kchar=last_key;
last_key='\0';
if(!input (row0))
row=0;
row=1;
row=2;
row=3;
last_key =KEYS[row][col];
kbd_down = true;
else // NEU KHONG CO PHIM NAO BAM, CHUYEN SANG QUET COT TIEP THEO
++col;
if(col>=4)
col=0;
return(kchar);
void main()
INT C;
INT16 value;
SET_TRIS_D(0X00);
SET_TRIS_B(0X0F);
lcd_putcmd(0x80);
lcd_init();
delay_ms(200);
OUTPUT_B(0XF0);
while( TRUE )
C=KBD_GETC();
IF (C!='\0')
LCD_PUTCMD(0X01);
PRINTF(LCD_PUTCHAR,"%C",C);
void main()
INT C;
INT16 DAT_THU;
INT16 value;
SET_TRIS_D(0X00);
SET_TRIS_B(0X0F);
lcd_putcmd(0x80);
lcd_init();
delay_ms(200);
WHILE( TRUE )
DAT_THU=0;
DO
C=KBD_GETC();
DAT_THU =DAT_THU*10;
DAT_THU=DAT_THU+C-0X30;
LCD_PUTCHAR(C);
}WHILE(C!='E');
LCD_PUTCMD(0X01);
LCD_PUTCMD(0XC2);
PRINTF(LCD_PUTCHAR,"%6LU",DAT_THU);