EE241 - Spring 2007

Advanced Digital Integrated

Circuits

Lecture 23: Latches and Flip-Flops

Announcements

Final exam on May 8 in class

Project presentations on May 3, 1-5pm

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 Class Material
Last lecture
SRAM
Todays lecture
Latches and flip-flops

Latches: Reading
Rabaey et al, Chapters 7 and 10
Chapter 10 in Chandrakasan et al, by Partovi
Stojanovic, Oklobdzija, JSSC 4/99

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 Latch vs. Flip-Flop
z Latch Flip-Flop (register)
stores data when stores data when
clock rises
clock is low

D Q D Q

Clk Clk

Clk Clk

D D

Q Q

Latch vs. Flip-Flop

Courtesy of IEEE Press, New York. 2000 6

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 Latch Pair vs. Flip-Flop
Performance metrics
Delay metrics
Delay penalty
Clock skew penalty
Inclusion of logic
Inherent race immunity
Power/Energy Metrics
Power/energy
PDP, EDP
Design robustness
7

Latches

Negative latch Positive latch

(transparent when CLK= 0) (transparent when CLK= 1)

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 Latches

Transmission-Gate Latch C2MOS Latch

Clk
Clk

D Q
D Q

Clk
Clk

Latches

10
Courtesy of IEEE Press, New York. 2000

5
 TSPC - True Single Phase Clock Logic

VDD VDD VDD VDD

M1 M1 M1 M1
Out Out

In M2 M2
In M2 M2
Out Out
In In

M3 M3 M3 M3

Precharged N Precharged P Non-precharged N Non-precharged P

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TSPC - True Single Phase Clock Logic

VD D VDD VDD VDD

PUN

In
Static

Logic Out

PDN

Including logic into Inserting logic between

the latch latches

12

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 Doubled TSPC Latches

VDD VDD VDD VDD

Out
In
Out

Doubled n-TSPC latch Doubled p-TSPC latch

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DEC Alpha 21064

Dobberpuhl, JSSC 11/92

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 DEC Alpha 21064

L1: L2:

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DEC Alpha 21064

Integrating logic into latches

Reducing effective overhead

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8
DEC Alpha 21164

L1 Latch L2 Latch

L1 Latch with logic

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Latch Pair as a Flip-Flop

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 Requirements for the Flip-Flop Design
High speed of operation:
Small Clk-Output delay
Small setup time
Small hold timeInherent race immunity
Low power
Small clock load
High driving capability
Integration of logic into flip-flop
Multiplexed or clock scan
Robustness
Crosstalk insensitivity
- dynamic/high impedance nodes are affected

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Sources of Noise

Courtesy of IEEE Press, New York. 2000 20

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 Gate Isolation

Courtesy of IEEE Press, New York. 2000 21

Flip-Flop Robustness
Robustness of the storage node
Input isolation
Data stored statically, max resistance limit
Min capacitance limit
Preventing storage node exposure

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 Types of Flip-Flops

Latch Pair
(Master-Slave)
Pulse-Triggered Latch

L1 L2 L
Data Data
D Q D Q D Q

Clk Clk Clk Clk

Clk

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Flip-Flop Delay
z Sum of setup time and Clk-output delay is the true
measure of the performance with respect to the
system speed
z T = TClk-Q + TLogic + Tsetup+ Tskew

D Q Logic D Q
N
Clk Clk

TClk-Q TLogic TSetup

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 Delay vs. Setup/Hold Times
350

300
Minimum Data-Output
250
Clk-Output [ps]

200

150
Setup Hold

100

50

0
-200 -150 -100 -50 0 50 100 150 200
Data-Clk [ps]
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Master-Slave Latch Pairs

z Positive setup times

z Two clock phases:
distributed globally
generated locally
z Small penalty in delay for incorporating
MUX
z Some circuit tricks needed to reduce the
overall delay
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 Master-Slave Latch Pairs

Case 1: PowerPC 603 (Gerosa, JSSC 12/94)

Vdd Vdd

Clk Clkb
Q
D

Clkb Clk

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T-G Master-Slave Latch

Feedback added for static operation

Unbuffered input
input capacitance depends on the phase of the clock
over-shoot and under-shoot with long routes
wirelength must be restricted at the input
Clock load is high
Low power
Small clk-output delay, but positive setup

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 Master-Slave Latches
Vdd Vdd

Case 2: C2MOS
Ck Ckb
D Q
Ckb Ck

Vdd Vdd Vdd Vdd

Clk Ck
Vdd Vdd
Ckb Ck

Feedback added for static operation

Ck Ckb

Locally generated clock

Poor driving capability

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Master-Slave TSPC Flip-flops

VDD VDD VDD VDD VDD VD D

Y
D D
D X

D

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

VDD VDD VDD

D D

(c) Positive edge-triggered D flip-flop

using split-output latches

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 Pulse-Triggered Latches

First stage is a pulse generator

generates a pulse (glitch) on a rising edge of the clock
Second stage is a latch
captures the pulse generated in the first stage
Pulse generation results in a negative setup time
Frequently exhibit a soft edge property

Note: power is always consumed in the pulse generator

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Pulsed Latch

Simple pulsed latch

Kozu, ISSCC96
32

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 Intel/HP Itanium 2

Naffziger, ISSCC02
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Pulse-Triggered Latches

Hybrid Latch Flip-Flop, AMD K-6

Partovi, ISSCC96

Vdd

Clk

34

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 HLFF Operation

1-0 and 0-1 transitions at the input with 0ps setup time

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Hybrid Latch Flip-Flop

Skew absorption

Partovi et al, ISSCC96 36

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 Pulse-Triggered Latches

AMD K-7

Courtesy of IEEE Press, New York. 2000 37

Pulse-Triggered Latches
Semi-Dynamic Flip-Flop (SDFF),
Sun UltraSparc III, Klass, VLSI Circuits98
Vdd Vdd

Q
Q

Clk

Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft
edge on rising transition
Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists
Small penalty for adding logic 38

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 Pulse-Triggered Latches

7474, from early 1960s

S
Q

Clk
Q
R

D
39

Pulse-Triggered Latches
Case 4: Sense-amplifier-based flip-flop, Matsui 1992.
DEC Alpha 21264, StrongARM 110
First stage is a sense amplifier,
precharged to high, when Clk = 0
After rising edge of the clock sense
amplifier generates the pulse on
S or R
The pulse is captured in
S-R latch
Cross-coupled NAND has different
propagation delays of rising and
falling edges

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 Sense Amplifier-Based Flip-Flop

Courtesy of IEEE Press, New York. 2000 41

Flip-Flop Performance Comparison

Test bench Data

D Q
200fF
Total power consumed
internal power Clock
Clk Q
200fF
data power
clock power 50fF
Measured for four cases
no activity (0000 and 1111)
maximum activity (0101010..) Delay is (minimum D-Q)
average activity (random sequence) Clk-Q + setup time

Stojanovic, Oklobdzija JSSC 4/99

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 Flip-Flop Performance Comparison

70

60
Total power [uW]

50
TG M-S
HLFF Original SAFF
40

30
mSAFF 2
20 C MOS
SDFF
10

0
100 150 200 250 300 350 400 450 500
Delay [ps]

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Sampling Window Comparison

Naffziger, JSSC 11/02

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 Local Clock Gating
2

Q
CKI
1.2
0.85 0.85
DI 0.5
D
0.85
0.5 0.5

CKIB CKIB 0.5

0.5

0.85 0.5 0.85 0.5

Data-Transition
Look-Ahead

Pulse XNOR
Generator

CKIB Clock on demand

0.85 Flip-flop
CKI
CP
0.5

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Next Lecture
Timing

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