UVM

Methodology

May 2015

Any use of this material without specific permission of Arrow Devices is strictly prohibited
 Topics covered
Introduc0on
SV Test-bench Architecture
UVM Test-bench Architecture
UVM Congura0on
UVM Messaging
UVM Sequences
UVM Test
UVM Phasing
UVM Overriding
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Introduc0on

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 UVM Core Capabilities

l Universal Verification Methodology or UVM

A methodology and a class library for building advanced
reusable verification component

l Relies on strong, proven industry foundations

The core of its success is adherence to a standard (i.e.
architecture, stimulus creation, automation, factory usage
standards etc.)

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Origin of UVM

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 The Goal: Automation

Following can be automated using UVM

l Coverage Driven Verification
(CDV) environments
l Automated Stimulus
Generation
l Independent Checking
l Coverage Collection

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SV Test-bench Architecture

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SV Testbench Architecture

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Example: SV FIFO Testbench

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UVM Test-bench Architecture

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UVM Test-bench Architecture

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Example: UVM FIFO Testbench (1/3)

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Example: UVM FIFO Testbench (2/3)

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Example: UVM FIFO Testbench (3/3)
Descrip0on of Pop Agent

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UVM Class Hierarchy

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 UVM Agent
l Agents provide all the verification
logic for a device in the system
l Instantiation and connection logic
is done by the developer in a
standard manner
l A Standard agent has:
Sequencer for generating
traffic
Driver to drive the DUT
Monitor
l Agent has standard configuration
parameters
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UVM Agent: Standard Configuration
l A standard agent is configured using an enumeration field:
is_active
UVM_ACTIVE:
Actively drive an interface or device
Driver, Sequencer and Monitor are allocated
UVM_PASSIVE:
Only the Monitor is allocated
l Still able to do checking and collect coverage
l Other user-defined configuration parameters can also be added
Example: address configuration for slave devices

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Driver-Sequencer Model

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UVM Congurable Bus Environment

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UVM Congura0on

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 UVM Configuration Mechanism
l The configuration mechanism allows a powerful way for attribute
configuration
l Configuration mechanism advantages:
Mechanism semantic allows an upper component to override
contained components values
- No file changes are required
Can configure attributes at various hierarchy locations
Wild cards and regular expressions allow configuration of multiple
attributes with a single command
Debug capabilities
Support for user defined types (e.g. SV virtual interfaces)
Run-time configuration support
Type safe solution
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 UVM Database
UVM supports the following database

l uvm_config_db
l uvm_resource_db

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Example: UVM Congura0on Database

l The full signature of set method is

uvm_config_db #( type T = int )::set( uvm_component cntxt ,

string inst_name , string field_name , T value );
interface ahb_if data_port_if( clk , reset );
interface ahb_if control_port_if( clk , reset );
...
uvm_config_db #( virtual ahb_if )::set( null , "uvm_test_top" ,
"data_port" , data_port_if );
uvm_config_db #( virtual ahb_if )::set( null , "uvm_test_top" ,
"control_port" , control_port_if );

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 UVM Messaging Facility
l Messages print trace information with advantages over
$display:
Aware of its hierarchy/scope in testbench
Allows filtering based on hierarchy, verbosity, and time
l Simple Messaging:
`uvm_*(string id, string message, <verbosity>);Where
*(severity) is one of fatal, error, warning, info
<verbosity> is only valid for uvm_info

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UVM Sequences

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 Transaction : uvm_seq_item
l UVM provides all the necessary operations using factory
registration
Randomization
Printing
Cloning
Comparing
Copying
Packing
Transaction Recording

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Fifo Sequence Item

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 UVM Sequences
l A sequencer controls the generation of random stimulus by
executing sequences
l A sequence captures meaningful streams of transactions
A simple sequence is a random transaction generator
A more complex sequence can contain timing, additional
constraints, parameters
l Sequences:
Allow reactive generation react to DUT
Have many built-in capabilities like interrupt support,
arbitration schemes, automatic factory support, etc
Can be nested inside other sequences
Are reusable at higher levels
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 UVM Sequences

l A sequence is started by two ways

Setting as the default sequence
Using a call to its start() method
l Start Method and example

Virtual task start (uvm_sequencer_base sequencer, // Pointer to sequencer
uvm_sequence_base parent_sequencer = null, // Relevant if called within a sequence
integer this_priority = 100, // Priority on the sequencer
bit call_pre_post = 1); // pre_body and post_body methods called
// For instance - called from an uvm_component - usually the test:
apb_write_seq.start(env.m_apb_agent.m_sequencer);
// Or called from within a sequence:
apb_compare_seq.start(m_sequencer, this);

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Example: FIFO Sequence

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Virtual Sequence

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UVM Test

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 UVM Test
l Placing all components in the test requires lot of duplication
l Separate the env configuration and the test
TB class instantiates and configures reusable components
l Tests instantiate a testbench
Specify the nature of generated traffic
Can modify configuration parameters as needed
l Benefits
Tests are shorter, and descriptive
Less knowledge to create a test
Easier to maintain - changes are done in a central location
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UVM Phasing

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 UVM Simulation Phases
l The Standard UVM phases
Build phases, Run-time phases and Clean up phases
l Unique tasks are performed in each simulation phase
Set-up activities are performed during testbench
creationwhile expected results may be addressed in check
Phases run in order next phase does not begin until
previous phase is complete
l UVM provides set of standard phases enabling VIP plug&play
Allows orchestrating the activity of components that were
created by different resources

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UVM Simulation Phases

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Example: FIFO Environment Phases

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UVM Overriding

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 Overriding SV components and
Data Objects
l UVM Provides a mechanism for overriding the default data
items and objects in a testbench
l Polymorphism made easy for test writers
l Replace ALL instances:
object::type_id::set_type_override(derived_obj::get
_type())
l Replace Specific instances
object::type_id::set_inst_override(derived_obj::get_
type(), hierarchical path);

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 Extensions Using Callbacks

l Like the factory, callbacks are a way to affect an existing

component from outside
l The SystemVeriloglanguage includes built-in callbacks
e.g. post_randomize(), pre_body()
l Callbacks requires the developer to predict the extension
location and create a proper hook
l Callbacks advantages:
They do not require inheritance
Multiple callbacks can be combined

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 UVM Advantages (1/2)
Standard communica0on between components
End of test is well dened
All the tasks in the component are pre-dened standard
names by using Phasing
Standard Sequencer to Driver Communica0on
Separa0ng testbench into structural and behavioral
Congura0on database ie either easy to use or to change

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 UVM Advantages (2/2)
Using Factory registra0on
You can override the type or instance of trasac0ons,
components etc.,
Congura0on can be changed easily
Overridden components can be used with less eorts
Provides user more exbility in wri0ng tests
Reusability
Debugging

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Thank you

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