STEPS TO FOLLOW AT STARTING

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1.First Download the ISCAS' 89 Benchmark Circuit from ISCAS website.
2.Open the verilog codes and try to analyze the code by checking number of input
s and outputs.
3.Another important aspect to check wheteher the verilog code is pure combinatio
nal and sequential circuit.

STEPS TO CONVERT THE VERILOG CODE INTO THE NETLIST

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Important aspect:LIBRARY USED FARADAY
1.Open the code and redefine the behaviroal of D flip flop as per the Library we
re used.
2.Make Seperate Directoty for each BENCHMARK CIRCUIT eg: s5837
3.Copy the code to that Directory in synopsis server.
4.Invoke the design Compiler tool to convert the verilog code into the Netlist.
5.Carefully change the logic and constraint script to get your netlist. (SCRIPT
S RELATED TO RUN DC COMPILER ,CONSTRAINTS AND LOGIC ATTACHED IN FOLDER(USBDRIVE=
>) )
6.Repeat above steps for all ISCAS benchmark Circuits.

STEPS TO CONVERT THE NETLIST TO SCAN INSERTED NETLIST AND OBTAIN FAULT COVERAGE
, WSA
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1.Copy the netlist code into MENTOR SERVER and make seperate Directory similar a
s done in synopsis server.
2.There will be four file 1.faraday library 2.netlist generated for specific ver
ilog code 3.do files for scan insertion and atpg run.
3.Copy the file from FOLDER USB to run the tessent tool.
4.Invoke the tessent tool to convert the netlist into scan inserted netlist by <
circuitname>_atpg.do eg:s5378_atpg.do
5.Analyze the files created by the tool to runn the atpg.
6.Run one more time the tessent tool to get FAULT COVERAGE and WEIGHTED SWITCHIN
G ACITIVITY by another do file :-atpg_setup_<circuitname>.do eg:atpg_setup_s5378
7.Analayze the Fault coveage and WSA carefully for each BENCHMARK CIRCUIT.