a simple robot control system that will allow you to fully control your

robot's movements.=> rover 5, using two motors, using H bridges,papilio duo

and xilinx tool(registers,MUX,etc..)

Using a soft-core processor (general purpose processor built using your

FPGA), create a simple system that allows you to control your robot's position
on a flat, level surface. Your system should be able to perform the movement
outlined below:

Given a direction (front or reverse) with a distance, a turn (right or left) and
another direction with another distance, your robot should be able to travel the
first distance in a straight line in the direction given, perform the given turn (left
or right) and travel the second distance in a straight line in the direction given
for that distance.

An example sequence could be: Forward 10 inches, Turn left and reverse 17
inches.

In addition to the maneuvers mentioned above, you will need to meet the
following requirements

1]The robot shall be controlled using general purpose processor created using
schematic capture in Xilinx ise.

2]The robot controller shall be a programmable processor including at least an

instruction memory and a register file.

3]You will have to create your own instruction set that has the following:

4]An opcode field that selects the movement

5]A branch and/or jump instruction

6]Parameters that further define the specifics of the movement required

7]The controller shall fetch, decode and execute operations for each
instruction

There are no restrictions on what technologies you may use; as long as you
are creating an original solution to the problem above and are using a soft-
core solution created using xilinx. This means that you could use schematic
capture, VHDL

Q 1:Describe a high-level plan for creating your position-

control system.
This plan should include ideas for the algorithm(s) you'll design.
Q 2:Describe each of the components involved in your
design-- such as your motors, quadrature encoders,
processor controller, memory, register file and so on

You should be able to describe the data formats you'll use to control these
devices, and the format in which you'll expect data from them.
Q 3:Describe an instruction format:

You should have an instruction format define, both in assembly and machine
code. It does not have to be your final format. You should have a diagram that
shows the fields of the machine code instruction.
In this homework, you will create a 16-bit complex counter. The counter should
have the following features:

1. The counter can be asynchronously set by a clear

signal.

2. Up count and down count based on a control pin

(updown)

3. When it reaches zero during down count, it should

reset it self to 1111111111111111 on the next clock edge.

4. When it reaches 111111111111111 during up count,

it should reset itself to zero on the next clock edge.

5. There is a special function such that when activated,

the up count or down count step size will be a 4-bit
increment/decrement if the control pin stepcontrol is true. In case
the increment or decrement causes over flow or under flow, you
should wrap the count at one count before such condition occurs.
For example, if your down count from 9 by step size 4, the
sequence should be 9, 5, 1, 216 .

6. Of course, you should be able to synchronously load

the counter with a 16-bit data. The load control pin is load.

Please use the following module port names:

clk: clock port.

clr: asynchronous clear port.

 data: 16-bit data for synchronous load.

load: load control port, load data if it is true.

step : 4-bit data for up or down count step. (if step = 0011, the up
count sequence from 0 would be (0, 3, 6, 9 )

stepcontrol: step size control port. If true, use step size specified
by the 4-bit step. Otherwise use step size of 1.

q: a 16-bit output port for the counter.

What to hand in:

1. Your Verilog HDL source code

2. Your test fixture with sufficient number of test vectors to

exercise all the different options.

The simulation output.