Microprocessing

and
Microprogramming
ELSEVIER Microprocessing and Microprogramming 41 ( 19%) 69 l-702

A neural network-based replacement strategy

for high performance computer architectures
Humayun Khalid *
Depurtment of Electrical Engineering, Convent Avenue at 140th Street, City University of New York, The City College, New York,
NY 10031, USA

Received 5 May 1995; revised 8 August 1995; accepted 23 October 1995

Abstract

We propose a new scheme for the replacement of cache lines in high performance computer systems. Preliminary
research, to date, indicates that neural networks (NNs) have great potential in the area of statistical predictions [l]. This
attribute of neural networks is used in our work to develop a neural network-based replacement policy which can effectively
eliminate dead lines from the cache memory by predicting the sequence of memory addresses referenced by the central
processing unit (CPU) of a computer system. The proposed strategy may, therefore, provide better cache performance as
compared to the conventional schemes, such as: LRU (Least Recently Used), FIFO (First In First Out), and MRU (Most
Recently Used) algorithms. In fact, we observed from the simulation experiments that a carefully designed neural
network-based replacement scheme does provide excellent performance as compared to the LRU scheme. The new approach
can be applied to the page replacement and prefetching algorithms in virtual memory systems.

Keywor& Performance evaluation; Trace-driven simulation; Cache memory; Neural networks; Predictor

1. Introduction extremely vital for high speed computers [2-71. It is

In high performance computer systems, band-
width of the memory is often a bottleneck because it
plays a critical role in affecting the peak throughout.
Cache is the simplest cost-effective way to achieve
high speed memory hierarchy and, its performance is
l Email: khali@ee-mail.engr.ccny.cuny.edu
for this reason, that caches have been extensively
studied since their introduction by IBM in the system
360 Model 85 [8]. Caches provide, with high proba-
bility, instructions and data needed by the CPU at a
rate that is closer to the CPU’s demand rate. They
work because the programs exhibit a property called
locality of reference. Three basic cache organizations
were identified by Conti [9]: direct mapped, fully
associative, and set associative. The choice of cache

0165~6074/%/$15.00 0 1996 Elsevier Science B.V. All rights reserved

XSDI 0165-6074(95)00030-5
692 H. Khalid/Microprocessing
organization can have a significant impact on cache
performance and costs [lo- 121. In general, set asso-
ciative cache organization offers a good balance
between hit ratios and the implementation cost. Also,
the selection of a line/block replacement algorithm,
in set associative caches, can have. a significant
impact on the overall system performance. The com-
mon replacement algorithms used with such caches
are: FIFO, MRU, and the LRU. These algorithms try
to anticipate future references by looking at the past
behavior of the programs (exploiting the locality of
reference proper@ of the programs). The relative
performance of these algorithms depends mainly on
the length of the history consulted. An LRU algo-
rithm consults a longer history of past address pat-
terns than FIFO, and therefore, it has a better relative
performance.
Many different approaches have been suggested
by researchers to improve the performance of re-
placement algorithms [13-151. One such proposal
was given by Pomerene et al. [13]. Pomerene sug-
gested the use of a shadow directory in order to look
at a relatively longer history when making decisions
with LRU. The problem with this approach is that
the size of the shadow directory limits the length of
the history consulted. Chen et al. [14] studied the
improvement in cache performance due to instruc-
tion reordering for a variety of benchmark programs.
The instruction reordering increases the spatial and
sequential locality of instruction caches, and thereby,
results in a better performance of the replacement
and mapping algorithms. Our research work attempts
to improve the performance of cache memory by
developing a replacement strategy that looks at a
very long history of addresses, without proportional
increase in the space/time requirements. The task is
accomplished through neural networks (NNs). Some
rudimentary work in this area was done by Sen [ 161.
His results were not very encouraging. Moreover, no
justification or explanation was given for the design.
In the next section of this paper we will describe
various neural network paradigms that have been
and Microprogramming 41 (1996) 691-702
considered in our work. Section 3 provides a theoret-
ical framework for the replacement policy. Next,
algorithms are developed to realize the replacement
scheme for different categories of neural networks.
Section 5 is on the hardware implementation of the
algorithms. Simulation results and discussion are
given in Section 6. Finally, the last section contain
recommendations for future work and conclusions.
2. Neural network paradigms for the cache con-
troller
Neural networks are human attempts to simulate
and understand the nervous system with the hope of
capturing some of the power of these biological
systems such as the ability for generalization, grace-
ful degradation, adaptivity and learning, and paral-
lelism. There are many different types/models/
paradigms of neural networks (NNs), reflecting the
emphasis and goals of different research groups.
Each network type, generally, has several variations
which address some weakness or enhance some fea-
ture of the basic networks. In this large array of
network types, there are two characteristics that di-
vide NNs into a few basic categories.
(1) Direction of signal flow: feed-forwa,rd/feed-
back/lateral,
(2) Mode of learning: supervised/unsupervised/re-
inforcement.
NNs are experts at many pattern recognition tasks.
They generate their own rules by learning from
examples shown to them. Due to their learning abil-
ity, NNs have been applied in several areas such as:
financial prediction, signal analysis and processing,
process control, robotics, classification, pattern
recognition, filtering, speech synthesis, and medical
diagnosis. Several good references are available on
the theory and applications of NNs [17-191.
We have chosen six of the most popular NNs, that
encompass almost all of the basic categories. In
addition, we have looked at variants from among
 H. Khalid/Microprocessing
these basic categories. A very brief description of the
paradigms used in our work is given hereunder.
(1) Backpropagation Neural Network (BPNN). A
typical BPNN has an input layer, an output layer,
and at least one hidden layer. There is no theoretical
limit on the number of hidden layers. However, in
our work we have tried to limit the number of cases
under study by considering at most two hidden lay-
ers. There are several variants of BPNNs, a few of
which are considered in the present work.
(2) Radial Basis Function Network (RBFN). In gen-
eral, a RBPN is any neural network which makes use
of a radially symmetric and radially bounded transfer
function in its hidden layer. Probabilistic neural net-
works (PNNs) and general regression neural net-
works (GRNNs) could both be considered RBFNs.
The Moody/Darken type of RBFN (MD-RBFN),
that we have used in the research, consists of 3
layers: an input layer, a prototype layer, and an
output layer.
(3) Probabilistic Neural Network (PNNJ. The PNNs
actually implements Bayes decision rule and uses
Parzen windows to estimate the probability density
functions (pdf) related to each class. The main ad-
vantage of PNN is that it can be effectively used
with sparse data.
(4) Modular Neural Network (MNN). MNNs con-
sists of a group of BPNNs competing to learn differ-
ent aspects of a problem, and therefore, it can be
regarded as a generalization of BPNN. There is a
gating network associated with MNN that controls
the competition and learns to assign different parts of
the data space to different networks.
(5) Learning Vector Quantization Nehvork (LVQ).
LVQ is a classification network. It contains an input
layer, a Kohonen layer which learns and performs
the classification, and an output layer. The basic
and Microprogramming 41 (1996) 691-702 693
LVQ has various drawbacks and therefore, variants
have been developed to overcome these shortcom-
ings.
(6) General Regression Neural Network (GRNN).
GRNNs are general purpose NNs. A simple GRNN
consists of an input layer, a pattern layer, summation
and division layer, and an output layer, GRNNs
provide good results in situations where the statistics
of the data changes over time. They can be regarded
as the generalization of probabilistic neural net-
works. GRNNs use the same parzen estimator as the
PNNs.
3. Theoretical basis for the cache replacement
policy
The proposed scheme uses neural networks to
identify which line/block should be replaced on a
cache miss in real-time. The job of our neural net-
works is to learn a function that may approximate
the unknown complex relationship between the past
and future values of addresses.
f: past + future;
tl (past, future) E Domain( addresses)
The function of f can also be learned using the tag
field of the addresses. Recall, that a set-associative
cache partitions the addresses into tag, set, and the
word fields. The word field is used to select a word
within a cache block/line and the set field is used
for indexing. The tag field preserves the mapping
between the cache and the main memory. This means
that the development of f using the tag field is only
possibly if we use the set field for indexing a group
of neurons in NNs. Fig. 1 shows how a NN is
partitioned into groups/sets and indexed through a
set selector. Here, the function f actually represents
a predictor. The parameters of such predictors are
developed through the use of some statistical proper-
ties of variables/functions such as mean, variance,
694 H. Khalid/Microprocessing
Fig. 1. Partial block diagram of the cache controller with any
neural network paradigm except PNN/GRNN.
probability density functions (pdf), cumulative distri-
bution functions (cdf), power spectral density etc.
This means that our NNs would behave as predictors
if they are informed about the statistical properties of
the tags. The problem with this approach is that tags,
like other similar data sets, do not have well-defined
statistical properties.
To accomplish the task in, we have attempted to
teach NNs the histogram of references (an estimated
pdf is called a histogram). Initially, the performance
of the predictor would be low, however, the perfor-
mance improves as the histogram develops. A well-
developed histogram may contain sufficient locality
information about the programs and can be used for
guiding the replacement decisions. In order to ac-
complish this with NNs, we need at least two tags,
T(i) and T(i + l), for the training/learning. This
implies that the network learning should be delayed
until a new tag arrives. A tag T(i) is a vector that is
made up of O’s and - l’s (Bipolar values). The size
of each vector T(i) depends on the computer archi-
tecture. For example for a Q-bit address machine
that incorporates a cache with N sets and P words
per block, the size of the vector T(i) would be equal
to Y = (Q - (log, N + log, P)) bits. So, a Y-di-
mensional vector T(i) should be applied to the input
and Microprogramming 41 (1996) 691-702
layer of NNs (predictor) and the output f(i + 1)
(estimate of T(i + 1)) is compared with T( i + 1) in
order to get error values for the feedback purpose.
The repetition of the procedure will eventually lead
to the development of predictor parameters contain-
ing histogram information of the addresses. There
are some NNs, like PNNs and GRNNs, which re-
quire only the present value of tags T(i) to estimate
the categorical pdf/cdf, internally, using parzen win-
dows. Such NNs are good for classification type of
problems, since they are adept at developing categor-
ical histograms (related to a category/class).
The above discussion gives some insight into the
algorithm that would make NNs behave as predictors
for our problem. The question that remains is that
how can the predictor information be used for
block/line replacements in a cache in real time?
This question is answered in two different ways for
two different categories of NNs based on whether
the histogram is estimated internally by NNs or not.
Our first category consist of BPNN, MNN, LVQ,
and RBFN. The second category contains PNN, and
GRNN. The basic approach, however, is the same
for both cases. What we want to do is to make both
types of NNs learn the histogram of addresses/tags.
At the same time, we would also like to extract the
history information for a particular tag instead of the
estimate of the future values of the tag. So, the
important parameter that is used for guiding the
replacement decision is not f(i + l), rather, it is the
response of a particular layer of neurons containing
categorical history. The number of categories re-
ferred to in such layers, that is the number of neu-
rons in the layers, should obviously be equal to the
associativity A of the cache in order to be able to
identify the cache line to be replaced within the set.
The task, therefore, is to select a NN architecture and
train it to learn the histogram in such a way so that at
least a layer of neurons in NNs would provide the
desired information. The responses of these neurons
to an incoming tag T(i) will therefore determine the
extent to which a tag vector T(i) is seen in the past.
 H. Kholid/ Microprocessing and Microprogrumming 41 (1996) 691-702
This can be accomplished by correlating the history
of references, corresponding to each cache line in a
set, with the present tag vector T(i).
Consider the finite correlation of two sequences x,
and Y,,,
m
‘n= c Xkyk-n
k=O
=X()y-n+X,y,_n+ ... +x,y,_.
The neurons in NNs can be made to compute the
sum as follows for an input vector X and the weight
vector W:
xrw = xowo + X,W] + . . . +xmwm
Equating the right hand side of Eqs. (1) and (2), we
get the following values:
W~=y_nrW1=Y~-nt . . . . ..,wm=ym_n
This means that for certain weight values, the inner
product results from a layer of neurons can provide,
to a certain extent, the correlation information. With
this information, we can determine which line is the
most suitable candidate to be replaced in a cache set.
Another way of looking at the same thing is from
the point of view of the difference in the two vectors.
For an associativity A, we are looking towards an
A-class problem for which we require
i= ,7ax, A 11X - Wi 11
9. 7
Expanding IIX - Wi II we get,
IIx-wiII=[(x-wi)‘(x-wi)]“2
= (xTx- 2XTWi -t- w;rwi)1’2
From (3) it is obvious that for max IIX - Wi II,
i= 1, 2,..., A, we require min (XTWi>. Therefore,
the most suitable line to be replaced is the one that
corresponds to the neuron, in a layer, with the small-
est output response. Thus, the identification of such a
layer for the two categories of NNs, under study,
becomes imperative for our job. For the PNNs/
GRNNs, parzen estimators are responsible for devel-
695
T(i)
(1)
i ForSet N-1 1
i T
Li
(2) Fig. 2. Partial block diagram of the cache controller with
PNN/GRNN paradigm.
oping the histogram. In such a case, we don’t need
T(i) and T(i + 1) for the determination of feedback
error. Therefore, the output layer of such NNs could
be used for the identification of replaceable cache
lines (see Fig. 2). The things become a little more
complicated for the other category of NNs
(BPNN, MNN, LVQ, RBFN). This is because, we
need to train such NNs to develop the histogram by
externally providing T(i + 1). In this paper, we sug-
gest a heuristic solution to the problem of identifying
the layer of neurons that would provide the replace-
ment information. Our trace-driven simulation exper-
iments indicate that by inserting a low-dimensional
layer of neurons between two identical NNs, learning
the histogram together, could help us identify the
(3) appropriate cache line to be replaced (see Fig. 1).
4. The algorithms
The discussion above, leads us to the following
algorithms for the replacement of cache lines from a
set.
696 H. Khalid/ Microprocessing and Microprogramming 41 (I 996) 691-702
Algorithm-l
(For replacements with BPNN, MNN, RBFN, and
LVQ)
Step 1: (Partitioning Of NNs)
Partition the NNs into groups. Each group/NN mod-
ule deals with a specific set. This means that for N
sets of a cache the algorithmic space/time complex-
ity would be O(aN), where (Yis a factor that relates
to the complexity of NNs within a module.
Step 2: (Partitioning of Modules)
Each module of NN is partitioned into two sub-mod-
ules. The first sub-module should have an input layer
and one or more hidden layers. The second sub-mod-
ule should have one or more similar hidden layers
and an output layer. The two sub-modules are to be
connected by a lower dimensional layer of NNs,
interface layer, containing ‘A’ neurons (A =
associativity of a cache) that provide the desired
response for replacements.
Step 3: (Initialization)
Initialize all the weights in the NNs to small random
values very close to zero.
Step 4: (Module Selection)
Partition each incoming address into tag, word, and
set fields. The set field is to be used for selecting one
of the NN modules.
Step 5: (Replacement Line Identification)
Apply the input Y-dimensional tag vector 7’(i) to the
selected module n and look at the response from the
interface layer. The lowest response from neuron i,
i= 1,2,..., A, indicates that the ith cache line
within the set n should be replaced on a miss. On a
hit situation or when a cache line is empty (illegal
tag), the response from NNs should be disregarded.
Step 6: (Learning)
The output response from the second sub-module is
compared with the next incoming tag T( i + 1) and
the resulting error (T(i + 1) - l?‘(i+ 1)) is used for
the weight adjustment.
Algorithm-2 (For replacements with PNNs and
GRNNs)
Step I: Same as above.
Step 2: Same as step3 above
Step 3: Same as step4 above.
Step 4: (Replacement Line Identification)
Apply the input Y-dimensional tag vector 7’(i) to the
selected module n and send the output response of
the PNN/GRNN to a transformation module. This
module transforms values as follows:
g: Lowest value + Highest possible output value for neurons
All other values + Lowest possible output value for neurons.
The highest output index of the transformation mod-
ule indicates the corresponding cache line to be
replaced from the set n.
Step 5: (Learning)
The output values from the transformation unit is
compared with its input values for the error. This
means that
ERROR = { g (input) - input) (4)
However, for the hit situation or for the case when a
cache line is empty, the error is evaluated by com-
paring the input values of the transformation module
with a vector. This vector should have a value of
+ 1.0 (highest possible unscaled output value for a
neuron) at the coordinates corresponding to the hit-
position/tag-insertion position (empty line case). All
other values should be - 1.0 (lowest possible un-
scaled output value for a neuron>.
5. Proposed implementation of the replacement
scheme
Based on the given theory and the algorithm for
different categories of NNs, we have developed two
different architectures presented via Figs. 1 and 2.
Fig. 1 shows how the set field of an incoming
address is extracted by the set selector to identify a
neural network module that contains the information
related to a particular cache set. The input and the
output lines for only one neural network module is
shown for brevity. All the other neural network
modules are identical copies of the one shown. The
tag field of an address is fed in the NN module as an
 H. Khalid/Microprocessing
input through a register. The sub-modules are repre-
sented by rectangular boxes. These boxes contain
input, output, and the hidden layer(s) for BPNN,
MNN, RBFN, or LVQ. The number of neurons in
the input and output layers are identical and equal to
the dimensionality Y of the tag vector T(i). The
sub-modules are connected by a neural network layer
called the interface layer. Each neuron in the inter-
face layer corresponds to a cache block/line within
a cache set. The error values are generated by com-
paring the estimated tag f(i + 1) with a new incom-
ing tag T(i + 1). Therefore, the error calculations are
delayed by approximately the amount of time it takes
for a new address/tag to arrive. The error is com-
puted through an adder/subtracter accompanied with
a buffer as shown by a circle in Fig. 1. This error is
fed back to the neural networks, for the set in
consideration, in order to develop the histogram of
addresses. The minimum selector (MIN SEL) identi-
fies the neuron, in the interface layer, that provides
the lowest response value and accordingly sends the
line replacement information to the control unit (CU).
The initial performance of this architecture would
obviously be low, because of the initial random
weight selection. However, performance improves as
NNs learn the histogram. The hardware implementa-
tion for the PNNs/GRNNs based replacement algo-
(4
Fig. 3. Miss ratio v.s. cache size for different variants of BPNN with BLDATA as the trace tile: (a) Associativity
(c) Associativity = 8.
and Microprogramming 41 (1996) 691-702 697
rithm is shown in Fig. 2. Here, only the present
value of tag T(i) is presented directly to the NNs
module as an input. The output layer for
PNNs/GRNNs is shown external to the rectangular
box in Fig. 2. The transformation module transforms
the output values from PNNs/GRNNs for two pur-
poses:
(11 To identify the corresponding cache line to be
replaced.
(2) To determine the error.
Again, the module transforms values as follows:
g : Lowest value + Highest possible output value
for neurons
All other values + Lowest possible output value
for neurons
For example, a 4-dimensional output vector
[O.l 0.9 0.8 0.31T is transformed as given below.
[O.l 0.9 0.8 0.31T L [l.O - 1.0 - 1.0 - 1.01r
A multiplexer (MUX) is used to select the vector
values from either the CU or the output of the
transformation unit. The information as to which of
the inputs should be selected by the MUX comes
from the CU. The lower input lines to the MUX are
selected by the CU on a hit situation or when a cache
(c)
= 2; (b) Associativity = 4,
698 H. Khalid/ Microprocessing and Microprogramming 41 (1996) 691-702

(4
Fig. 4. Miss ratio vs. cache size for different variants of BPNN with TPC.DAT as the trace file: (a) Associativity = 2; (b) Associativity = 4;
(c) Associativity = 8.

line in empty. However, on a cache miss, the upper
lines (representing the desired output vector) are
selected for the purpose of error computation.
6. Simulation results and discussion
In this research work, we have used trace-driven
simulations to accurately obtain information on the
relative performance of various neural network
paradigms and the conventional LRU algorithm. The
two trace files used were named TPC.data and
BI.data. TPC.data is the trace file that was generated
on an IBM PC running Borland’s Turbo Pascal
Compiler, The other trace file, BI.data, was gener-
ated using Microsoft’s Basica Interpreter. Each of
these original trace files contains approximately l/2
million addresses. For more information on these
trace files see [20].
The caches considered in our simulation have set
sizes that vary from N = 32 to N = 2048. The line
size is fixed at 8 words per block. We have also
varied the associativity A and looked at three differ-
ent cases, that is A = 2, A = 4, and A = 8. Each
figure is partitioned into three parts namely (a), (b),
and (cl, corresponding to the three values of associa-
tively under consideration. Figs. 3 and 4 provide the
miss ratio information for different variants of BPNN
paradigm with BI.data and TPC.data as the trace
files, respectively. T’s assigned to the legends denote
the type of the BPNN. Complete description of T’s
is given in Table 1. Notice from the Figs. 3 and 4
that BPNN of type T6 has a relatively better perfor-
mance than the other types. This means that the

Table 1
Legend information for Figures 3 and 4
Tl:Hidden layer1 = 11, Learning rule = Quick-prop, Learning rate = 0.5, Transfer function = TanH, Momentum = 0.5
‘I2 Hidden layer1 = 11,Learning rule = Max-prop, Learning rate = 0.5, Transfer function = TanH, Momentum = 0.5
T3: Hidden layer1 = 19, Learning rule = Norm-cum, Learning rate = 0.5, Transfer function = TanH, Momentum = 0.5
T4: Hidden layer1 = 11,Learning rule = Ext-delta-bar-delta, Learning rate = 0.5, Transfer function = Sigmoid, Momentum = 0.5
T5: Hidden layer1 = 1I, Hidden layer2 = 19, Learning rule = Max-prop, Learning rate = 0.9, Learning rule = TanH, Momentum = 0.9
T6: Hidden layer1 = 19, Learning rule = Norm-cum, Learning rate = 0.9, Transfer function = TanH, Momentum = 0.9
T7: Hidden layer1 = 19, Learning rule = Norm-cum, Learning rate = 0.05, Transfer function = TanH, Momentum = 0.05
 H. Khalid/ Microprocessing and Microprogramming 41 (1996) 691-702
Norm-Cum learning rule along with the TanH trans-
fer function is suitable for our neural network-based
replacement algorithm. The number of neurons in the
hidden layer are reasonably varied, in our experi-
ments, in the range 10 to 20. For T5, even with two
hidden layers, Max-Prop learning rule could not
outperform the Norm-Cum based results. However,
T3’s performance is on the same league as T6 (best
case) which demonstrates the fact that for our data,
there is a very little change in learning with the
increased momentum and learning rate values.
The performance of T7 with respect to T6 indi-
cates that very high values of momentum and leam-
ing rates do not produce very drastic results as
compared to moderate values, but, very low values
are indeed detrimental to the performance. The
(a)
Fig. 6. Miss ratio V.S. cache size for different NN paradigms
(c) Associativity = 8.
699
decrement in the miss ratio with increasing cache
size is uniform across different types of BPNNs.
Notice that the relative performance of T7 in Fig. 4
is worse as compared to Fig. 3; This is due to the
fact that the learning of neural networks is dependent
on the sequence of the data file. However, based on
the general profile of the results, for a variety of
address traces, we can draw some conclusions on the
relative performance of different types of neural
networks. Our experiments with using dynamic
learning rates (based on miss ratios) failed because
of the low values of miss ratios, the related curves
are, therefore, not included in the given figures. In
Figs. 5 and 6, a comparative performance of BPNN,
PNN, GRNN, LVQ, RBFN, and MNN is given.
Here, we have considered the best results from among
(b)
with TPC.DATA as the trace file: (a) Associativity = 2; (b) Associativity = 4;
700 H. Khlid/ Microprocessing and Microprogramming 41 (1996) 691-702

ib) CC)

Fig. 7. Miss ratio V.S. cache size for LRU, LVQ, and BPNN with BI.DATA as the trace tile: (a) Associativity = 2; (b) Associativity = 4; (c)
Associativity = 8.

the paradigms for a reasonable number of neurons
(IO to 20 neurons). Our comparative study reveals
that BPNN outperforms the other paradigms. The
closest rival appears to be the LVQ. PNNs and
GRNNs appear to be next in line, respectively. How-
ever, PNNs in some cases performs as well as LVQ.
The difference in the relative performance of various
neural network paradigms is quite appreciable for
large caches.
The last pair of Figs. 7 and 8, provide us with a
relative performance of LRU, LVQ, and BPNN. For
the peak category, BPNN gives a significant perfor-
mance improvement of 16.4711% in the miss ratio
values over the LRU algorithm. The average is not
significant because of the large variance in BPNN’s
performance as shown in Figs. 3 and 4. LVQ also
performs well and, in most of the cache organiza-
tions considered in the simulation studies, its perfor-
mance is better than the LRU. This proves that we
can get excellent results from NNs provided we
choose our parameters carefully. We expect that,
longer trace files for a variety of applications and
systems software can provide us with even better
results. The results are trace dependent, however, the

(a) (b) fc)

Fig. 8. Miss ratio V.S. cache size for LRU, LVQ, and BPNN with TPC.DATA as the trace file: (a) Associativity = 2; (b) Associativity = 4;
(c) Associativity = 8.
 H. Khalid/ Microprocessing and Microprogramming 41 (1996) 691-702
theory presented here dictates that our cache replace-
ment strategy can be expected to yield reasonably
good results for any workload.
7. Conclusion and recommendations for future
work
In this paper, we have presented neural network-
based cache replacement algorithms and have pro-
posed corresponding hardware implementations.
Several neural network paradigms, such as: BPNN,
MNN, RBPN, LVQ, PNN, and GRNN, were investi-
gated in our work and their relative performance was
studied, and analyzed. Our trace-driven simulation
results indicate that with a suitable BPNN paradigm,
we can get an excellent improvement of 16.47 11% in
the miss ratio over the conventional LRU algorithm.
Excellent performance of neural network-based re-
placement strategy means that this new approach has
potential for providing promising results when ap-
plied to the page replacement and prefetching algo-
rithms in virtual memory systems.
Acknowledgements
This research is supported in part by psc-cuny
grants #‘s 6-64455 and 6-666353.
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702 H. Khalid/Microprocessing and Microprogramming
Humayun Khalid was born at Karachi,
Pakistan. He received his B.S.E.E.
(Magna Cum Laude) and M.S.E.E.
(Graduate Citation) degrees from the
City College of New York. Currently,
he is a Ph.D. candidate in the depart-
ment of Electrical Engineering at the
City University Of New York. His re-
search interests include parallel com-
puter architecture, high performance
computing/computers, computer net-
works, performance evaluation, and ap
plied artificial neural networks. Mr.
41 (1996) 691-702
Khalid is a reviewer for IEEE international Phoenix Conference
on Computers and Communications (IPCCC), IEEE International
Conference on Electronics, Circuits, and Systems (ICECS’95),
Journal of Computer and Electrical Engineering, Information Sci-
ences Journal, and Computer Simulation Journal. He is an Assis-
tant Chair for the IEEE International Conference on Electronics,
Circuits, and Systems (ICECS’95). He is a lecturer at the City
University of New York (CUNY), and a lead researcher at the
Computer Engineering Research Lab. (CERL). He has published
several refereed technical articles in national and international
journals and conference proceedings.