Acer Aspire One AOP531H - D520 Compal LA-5141P PDF

A B C D E
ZZZ
DAZ@
DAZ08400100
1 1
KAV60 LA-5141P LS-5141P/5142P/5143P
ZZZ
DA2@
DA60000BO10
LA-5141P REV1 M/B
ZZZ
Compal Confidential
DA2@
DA20000FM10
LS-5141P REV1 PWR/B
ZZZ
DA2@
DA60000BU10
2 2
LS-5142P REV1 SDIO/B
ZZZ
DA2@
DA60000BT10
KAV60 Schematics Document
LS-5143P REV1 CARDREADER/B
www.manuals.clan.su
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
3
2009-03-06 3
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5141
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401690
Date: Tuesday, March 10, 2009 Sheet 1 of 40
A B C D E
A B C D E
Compal Confidential Diamondville SC

FCBGA8
Model Name : KAV60 437Pins
File Name : LA-5141P 22x22mm
page 4,5
1
P/N : DA60000BO00 1
FSB Clock Generator

CRT Conn H_A#(3..31) 400/533MHz H_D#(0..63) CK505 page 12
page 14
RGB
Calistoga GSE Memory BUS(DDRII) DDRII-SO-DIMM
page 11
FCBGA998
1.8V DDRII 400/533
LCD Conn. LVDS
Thermal Sensor page 13 27x27mm
EMC1402 page 6,7,8,9,10
page 4
DMI USB Port X1
page 28
X2 mode
USB I/O Board X2
2
PCI-Express ICH7M HDA page 22 2
BGA652 to I/O board

CONN
31x31mm RTS5159E
page 22
page 15,16,17,18
SATA
www.manuals.clan.su
SDIO CONN MINI Card x2 10/100 Ethernet BlueToothX1
AR8114A to I/OBoard CONN page19
page 27 page 22
JP7
page 19 page 24
Aralia Codec CMOS CAM
page13
LPC BUS ALC272
page 20
Transfermer WLANX1
page19
3
page 24 3
WWANX1
page19
Power ON/OFF RJ45

DC/DC Interface
page 29 page 24 HeadPhone & INT DMIC CONN
& LED CONN AMP & INT
MIC Jack
page 26 Speaker
page 21 page 21 page 13
3VALW/5VALW
page 33
ENE KBC SPI
DC IN
page 31
KB926page 25
1.5VS/0.9VS/ I/O board
BATT IN 2.5VS SATA CONN
page 32 page 36
Int.KBD SPI ROM USB Port X2
page 27 page 25
CHARGER 1.8V/VCCP Touch Pad
page 34
page 35 page 27
4 USB Card Reader 4
x1 RTS5159E
CPU_CORE
page 37
SCHEMATIC,MB A5141
B B
401690
A B C D E
A B C D E
1 1
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 100X b
EEPROM(24C16/02) 1010 000X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
www.manuals.clan.su
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3 ICH7M SM Bus address 3
BOARD ID Table(Page 25) Device Address
ID BRD ID Ra Rb Vab Clock Generator 1101 001Xb

(SLG8SP556VTR)
0 R01 (EVT) NC 0 0V DDR DIMMA 1010 000Xb
1 R02 (DVT) 100K 8.2K 0.25V
2 R03 (PVT) 100K 18K 0.50V
3 R10A (MP) 100K NC 3.3V
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E
5 4 3 2 1
(6) H_A#[3..16]
(6) H_D#[0..15] H_D#[32..47] (6)
U5A N270@ U5B
H_A#3 P21 V19 H_ADS# +VCCP +VCCP H_D#0 Y11 R3 H_D#32
A[3]# ADS# H_ADS# (6) D[0]# D[32]#
H_A#4 H20 Y19 H_BNR# H_BNR# (6) H_D#1 W10 R2 H_D#33
H_A#5 A[4]# BNR# H_BPRI# H_D#2 D[1]# D[33]# H_D#34
N20 A[5]# BPRI# U21 H_BPRI# (6) Y12 D[2]# D[34]# P1
1
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#
0
GROUP
ADDR
DATA GRP 0
H_A#7 J19 T21 H_DEFER# R201 R27 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# (6) D[4]# D[36]#
H_A#8 N19 T19 H_DRDY# H_DRDY# (6) 56_0402_5% 330_0402_5% H_D#5 W12 P2 H_D#37
H_A#9 A[8]# DRDY# H_DBSY# H_D#6 D[5]# D[37]# H_D#38
G20 A[9]# DBSY# Y18 H_DBSY# (6) AA16 D[6]# D[38]# J3
H_A#10 M19 H_D#7 Y10 N3 H_D#39
DATA GRP 2
2
2
H_A#11 A[10]# H_BR0# H_D#8 D[7]# D[39]# H_D#40
H21 A[11]# BR0# T20 H_BR0# (6) Y9 D[8]# D[40]# G3
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]#
CONTROL
H_A#13 H_IERR# H_D#10 D[9]# D[41]# H_D#42
M20 A[13]# IERR# F16 W15 D[10]# D[42]# N2
H_A#14 K19 V16 H_INIT#_R R33 1 2 1K_0402_5% H_D#11 AA13 L2 H_D#43
D A[14]# INIT# H_INIT# (16) D[11]# D[43]# D
H_A#15 J20 H_D#12 Y16 M3 H_D#44
H_A#16 A[15]# H_LOCK# H_D#13 D[12]# D[44]# H_D#45
L21 A[16]# LOCK# W20 H_LOCK# (6) Close to CPU W13 D[13]# D[45]# J2
H_ADSTB#0 K20 H_D#14 AA9 H1 H_D#46
(6) H_ADSTB#0 ADSTB[0]# D[14]# D[46]#
T5 H_AP0 D17 D15 H_RESET# H_RS#[0..2] (6) H_D#15 W9 J1 H_D#47
(6) H_REQ#[0..4] AP0 RESET# H_RESET# (6) D[15]# D[47]#
PAD H_REQ#0 N21 W18 H_RS#0 (6) H_DSTBN#0 H_DSTBN#0 Y14 K2 H_DSTBN#2 H_DSTBN#2 (6)
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2
J21 REQ[1]# RS[1]# Y17 (6) H_DSTBP#0 Y15 DSTBP[0]# DSTBP[2]# K3 H_DSTBP#2 (6)
H_REQ#2 G19 U20 H_RS#2 (6) H_DINV#0 H_DINV#0 W16 L1 H_DINV#2
REQ[2]# RS[2]# DINV[0]# DINV[2]# H_DINV#2 (6)
H_REQ#3 P20 W19 H_TRDY# H_TRDY# (6) H_DP#0 V9 M4 H_DP#2
H_REQ#4 REQ[3]# TRDY# T10 PAD DP#0 DP#2 PAD T15
R19 REQ[4]# (6) H_D#[16..31] H_D#[48..63] (6)
(6) H_A#[17..31] AA17 H_HIT# H_HIT# (6) U5 H_D#16 AA5 C2 H_D#48
H_A#17 HIT# H_HITM# H_D#17 D[16]# D[48]# H_D#49
C19 A[17]# HITM# V20 H_HITM# (6) Y8 D[17]# D[49]# G2
H_A#18 F19 H_D#18 W3 F1 H_D#50
H_A#19 A[18]# H_D#19 D[18]# D[50]# H_D#51
E21 A[19]# BPM[0]# K17 U1 D[19]# D[51]# D3
H_A#20 A16 J18 H_D#20 W7 B4 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 D19 H15 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# H_D#22 D[21]# D[53]# H_D#54
C14 A[22]# BPM[3]# J15 CPU N280 Y7 D[22]# D[54]# A5
ADDR GROUP 1
H_A#23 C18 K18 H_D#23 AA6 C3 H_D#55
H_A#24 A[23]# PRDY# PREQ# H_D#24 D[23]# D[55]#
DATA GRP 3
C20 J16 N280@ Y3 A6 H_D#56
A[24]# PREQ# D[24]# D[56]#
XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#25 W2 F2 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
D20 A[26]# TDI N16 V3 D[26]# D[58]# C6
H_A#27 B18 M16 ITP_TDO H_D#27 U2 B6 H_D#59
H_A#28 A[27]# TDO ITP_TMS H_D#28 D[27]# D[59]# H_D#60
C15 A[28]# TMS L17 T3 D[28]# D[60]# B3
H_A#29 B16 K16 ITP_TRST# H_D#29 AA8 C4 H_D#61
H_A#30 A[29]# TRST# H_D#30 D[29]# D[61]# H_D#62
B17 A[30]# BR1# V15 V2 D[30]# D[62]# C7
H_A#31 C16 H_D#31 W4 D2 H_D#63
H_A#32 A[31]# H_PROCHOT#_R H_DSTBN#1 D[31]# D[63]# H_DSTBN#3
A17 A[32]# PROCHOT# G17 1 2 H_PROCHOT# (37) (6) H_DSTBN#1 Y4 DSTBN[1]# DSTBN[3]# E2 H_DSTBN#3 (6)
H_A#33 B14 E4 H_THERMDA R202 22_0402_5% H_DSTBP#1 Y5 F3 H_DSTBP#3
THERM
A[33]# THRMDA (6) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (6)

H_A#34 B15 E5 H_THERMDC Close to CPU H_DINV#1 Y6 C5 H_DINV#3
A[34]# THRMDC (6) H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 (6)
H_A#35 A14 H_DP#1 R4 D4 H_DP#3
H_ADSTB#1 A[35]# H_THERMTRIP# T13 PAD DP#1 DP#3 PAD T12
(6) H_ADSTB#1 B19 ADSTB[1]# THERMTRIP# H17 H_THERMTRIP# (6,16)
H_AP1 M18 +CPU_GTLREF A7 T1 COMP0 1 R57 2 27.4_0402_1%
T7 PAD AP1 R240 1 @ GTLREF COMP[0]
2 1K_0402_5% ACLKPH U5 ACLKPH COMP[1] T2 COMP1 1 R58 2 54.9_0402_1%
C H_A20M# R239 1 @ DCLKPH COMP2 C
(16) H_A20M# U18 A20M# 2 1K_0402_5% V5 DCLKPH COMP[2] F20 2 R208 1 27.4_0402_1%
H_FERR# T16 V11 CLK_CPU_BCLK CLK_CPU_BCLK (12) T17 F21 COMP3 2 R209 1 54.9_0402_1%
(16) H_FERR# FERR# BCLK[0] BINIT# COMP[3]
H_IGNNE# J4 V12 CLK_CPU_BCLK# R6 MISC
(16) H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# (12) EDM
H_STPCLK# R16 +CPU_EXTBGREF M6 R18 H_DPRSTP# H_DPRSTP# (16,37)
(16) H_STPCLK# H_INTR STPCLK# EXTBGREF DPRSTP# H_DPSLP#
(16) H_INTR T15 LINT0 N15 R17 H_DPSLP# (16)
H CLK
H_NMI FORCEPR# DPSLP# H_DPWR#

(16) H_NMI R15 LINT1 N6 HFPLL DPWR# U4 H_DPWR# (6)
H_SMI# U17 P17 V17 H_PWRGOOD H_PWRGOOD (16)
(16) H_SMI# SMI# MCERR# PWRGOOD H_CPUSLP#
T6 RSP# SLP# N18 H_CPUSLP# (6)
D6 C21 CPU_BSEL0 J6 A13
NC1 RSVD3 (12) CPU_BSEL0 BSEL[0] CORE_DET
G6 C1 CPU_BSEL1 H5 B7 +CPU_CMREF
(12) CPU_BSEL1
NC
NC2 RSVD2 CPU_BSEL2 BSEL[1] CMREF[1]

H6 NC3 RSVD1 A3 (12) CPU_BSEL2 G5 BSEL[2]
K4 NC4
K5 AU80586GE025512_FCBGA437
NC5
www.manuals.clan.su
M15 NC6
L16 NC7 N270@
Layout note:
AU80586GE025512_FCBGA437 COMP0,2 connect with Zo=27.4ohm +/-15%, make
. trace length shorter than 0.5"
+VCCP +VCCP +VCCP +VCCP
COMP1,3 connect with Zo=55ohm +/-15%, make
trace length shorter than0.5"
1
1
R34 1 2 1K_0402_5% H_A#32
R30 1 2 1K_0402_5% H_A#33
R31 1 2 1K_0402_5% H_A#34 R47 R234 R51
R29 1 2 1K_0402_5% H_A#35 +CPU_GTLREF 1K_0402_1% +CPU_EXTBGREF 1K_0402_1% +CPU_CMREF 1K_0402_1%
2
2
+VCCP
@
1
1
R28 1 2 1K_0402_5% H_A20M# 1 1 1
R32 1 2 1K_0402_5% H_IGNNE#
B @ C62 R48 C342 R238 C65 R49 B
0.1U_0402_16V4Z 2K_0402_1% 1U_0402_6.3V4Z 2K_0402_1% 0.1U_0402_16V4Z 2K_0402_1%
2 2 2
change BOM structure 11/14
2
2
+VCCP
This shall place near CPU
R200 1 2 56_0402_5% ITP_TMS
Close to CPU pin
Close to CPU pin Close to CPU pin
R198 1 2 56_0402_5% ITP_TDI
PREQ#
within 500mils.
R206 1 2@ 56_0402_5% within 500mils. within 500mils. H_THERMDA, H_THERMDC routing together.
R199 1 2 56_0402_5% ITP_TDO Zo=55ohm Trace width / Spacing = 10 / 10 mil
R205 1 2 68_0402_5% H_PROCHOT# Zo=55ohm Zo=55ohm
Modify schematic by 10/21
R213 1 2 56_0402_5% ITP_TCK +3VS
R218 1 2 56_0402_5% ITP_TRST# CPU THERMAL SENSOR
0.1U_0402_16V4Z
1
C352
U17
2
1 8 EC_SMB_CK2 EC_SMB_CK2 (25)

VDD SMCLK
H_THERMDA 2 7 EC_SMB_DA2
DP SMDATA EC_SMB_DA2 (25)
C351
1 2 H_THERMDC 3 6 2 R304 1 +3VS
2200P_0402_50V7K DN ALERT# 10K_0402_5%
4 THERM# GND 5
A A
EMC1402-1-ACZL-TR_MSOP8
Address:100_1100

SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
5 4 3 2 1
U5D U5C +VCCP

A2 VSS1 VSS162 N5
A4 N7 C9 0.1U_0402_16V7K 1U_0402_6.3V6K
VSS2 VSS161 VTT1
A8 VSS4 VSS160 N9 VTT2 D9 1
A15 N13 +VCCP E9
VSS5 VSS159 VTT3 1 1 1 1
A18 N17 F8 C295 C307 C337 C341 C57 +
VSS6 VSS158 VTT4
A19 VSS7 VSS157 P3 VTT5 F9
A20 VSS8 VSS156 P4 VTT6 G8
2 2 2 2 2
B1 VSS9 VSS155 P5 V10 VCCF VTT7 G14
B2 VSS10 VSS154 P6 VTT8 H8
D B5 P7 A9 H14 0.1U_0402_16V7K 1U_0402_6.3V6K 220U_B2_2.5VM_R35 D
VSS11 VSS153 VCCQ1 VTT9
B8 VSS12 VSS152 P9 B9 VCCQ2 VTT10 J8 PLACE IN CAVITY
B13 VSS13 VSS151 P13 VTT11 J14
B20 VSS14 VSS149 P15 VTT12 K8
B21 VSS15 VSS148 P16 VTT13 K14
C8 VSS16 VSS147 P18 VTT14 L8
C17 VSS17 VSS146 P19 VTT15 L14
D1 VSS18 VSS145 R1 VTT16 M8
D5 R5 +CPU_CORE M14
VSS19 VSS144 VTT17
D8 VSS20 VSS143 R7 VTT18 N8
D14 VSS21 VSS142 R9 VTT19 N14
D18 VSS22 VSS141 R13 VTT20 P8
D21 VSS23 VSS140 R21 A10 VCCP1 VTT21 P14
E3 VSS24 VSS139 T4 A11 VCCP2 VTT22 R8
E6 VSS25 VSS138 T5 A12 VCCP3 VTT23 R14
E7 VSS26 VSS137 T7 B10 VCCP4 VTT24 T8
E8 VSS27 VSS136 T9 B11 VCCP5 VTT25 T14
E15 VSS28 VSS135 T10 B12 VCCP6 VTT26 U8
E16 VSS29 VSS134 T11 C10 VCCP7 VTT27 U9
E19 VSS30 VSS133 T12 C11 VCCP8 VTT28 U10
F4 VSS31 VSS132 T13 C12 VCCP9 VTT29 U11
F5 VSS32 VSS131 T18 D10 VCCP10 VTT30 U12
F6 VSS33 VSS130 U3 D11 VCCP11 VTT31 U13
F7 VSS34 VSS129 U6 D12 VCCP12 VTT32 U14
F17 VSS35 VSS128 U7 E10 VCCP13
F18 VSS36 VSS127 U15 E11 VCCP14
G1 VSS37 VSS126 U16 E12 VCCP15
G4 VSS38 VSS125 U19 F10 VCCP16 VCCPC64 F14
G7 VSS39 VSS124 V1 F11 VCCP17 VCCPC63 F13
C G9 V4 F12 E14 C
VSS41 VSS123 VCCP18 VCCPC62
G13 VSS42 VSS122 V6 G10 VCCP19 VCCPC61 E13
G21 VSS45 VSS121 V7 G11 VCCP20
H3 VSS46 VSS120 V8 G12 VCCP21
H4 VSS48 VSS119 V13 H10 VCCP22
H13 VSS52 VSS116 V21 J10 VCCP25
H16 VSS53 VSS115 W1 J11 VCCP26
H18 VSS54 VSS114 W5 J12 VCCP27
H19 W8 K10 +1.5VS
VSS55 VSS113 VCCP28
J5 VSS56 VSS112 W11 K11 VCCP29
www.manuals.clan.su
J7 VSS57 VSS111 W14 K12 VCCP30 130mA
J9 W17 L10 D7 +1.5VS
VSS58 VSS110 VCCP31 VCCA
J13 VSS59 VSS109 W21 L11 VCCP32 1
J17 Y1 L12 C338
VSS60 VSS108 VCCP33 CPU_VID0 0.1U_0402_16V7K
K1 VSS61 VSS107 Y2 M10 VCCP34 VID[0] F15 CPU_VID0 (37)
K6 Y20 M11 D16 CPU_VID1
VSS62 VSS106 VCCP35 VID[1] CPU_VID1 (37) 2
K7 Y21 M12 E18 CPU_VID2 CPU_VID2 (37) +CPU_CORE
VSS63 VSS105 VCCP36 VID[2] CPU_VID3
K9 VSS64 VSS104 AA2 N10 VCCP37 VID[3] G15 CPU_VID3 (37)
1
K13 AA3 N11 G16 CPU_VID4 CPU_VID4 (37)
VSS65 VSS103 VCCP38 VID[4] CPU_VID5 R221
K15 VSS66 VSS102 AA4 N12 VCCP39 VID[5] E17 CPU_VID5 (37)
K21 AA7 P10 G18 CPU_VID6 CPU_VID6 (37)
VSS67 VSS101 VCCP40 VID[6] 100_0402_1%
L3 VSS68 VSS100 AA10 P11 VCCP41
L4 AA12 P12
2
VSS69 VSS99 VCCP42 VCCSENSE
L5
L6
VSS70 VSS98 AA15
AA18
R10
R11
VCCP43 VCCSENSE C13 VCCSENSE (37) Length match within 25 mils
VSS71 VSS97 VCCP44
L7 VSS72 VSS96 AA19 R12 VCCP45 VSSSENSE
The trace space 7 mils,
L9 VSS73 VSS95 AA20 VSSSENSE D13 VSSSENSE (37)
B
L13 VSS74
Zo=27.4ohm B
1
L15 AU80586GE025512_FCBGA437
VSS75 R220
L18 VSS76
L19 VSS77 N270@
M1 100_0402_1%
VSS78
M5
2
VSS79
M7 VSS80
M9 VSS81
M13 +CPU_CORE +CPU_CORE
VSS82
M21 VSS83 PLACE IN CAVITY 2 x 330uF(9mohm/2)
N4 VSS84 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1 1
+ C51 + C331
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
C308 C309 C310 C311 C312 C313 C314 C320 C321 C322 C323 C324 C326 C327 C325 C315
AU80586GE025512_FCBGA437 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M
2 2 @
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
N270@
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
1 1 1 1 1 1 1 1 1 1 1 1
C298 C299 C300 C301 C302 C46 C304 C303 C335 C47 C328 C334
2 2 2 2 2 2 2 2 2 2 2 2
A A
10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z
PLACE IN CORRIDOR AND CLOSE TO CPU

SCHEMATIC,MB A5141
B B
401690
5 4 3 2 1
5 4 3 2 1
(4) H_D#[0..63] H_A#[3..31] (4)

U1A U1B
H_D#0 C4 F8 H_A#3
H_D#1 H_D#_0 H_A#_3 H_A#4 DMI_TXN0 MCH_CLKSEL0
F6 H_D#_1 H_A#_4 D12 (17) DMI_TXN0 Y29 DMI_RXN_0 CFG_0 C18 MCH_CLKSEL0 (12)
H_D#2 H9 C13 H_A#5 DMI_TXN1 Y32 E18 MCH_CLKSEL1
H_D#_2 H_A#_5 (17) DMI_TXN1 DMI_RXN_1 CFG_1 MCH_CLKSEL1 (12)
H_D#3 H6 A8 H_A#6 DMI_TXP0 Y28 G20 MCH_CLKSEL2
H_D#_3 H_A#_6 (17) DMI_TXP0 DMI_RXP_0 CFG_2 MCH_CLKSEL2 (12)
H_D#4 F7 E13 H_A#7 DMI_TXP1 Y31 G18 CFG3
H_D#_4 H_A#_7 (17) DMI_TXP1 DMI_RXP_1 CFG_3 @ PAD T32
H_D#5 E3 E12 H_A#8 J20 CFG5 1 2
D H_D#6 H_D#_5 H_A#_8 H_A#9 DMI_RXN0 CFG_5 CFG6 R181 2.2K_0402_5% D
C2 H_D#_6 H_A#_9 J12 (17) DMI_RXN0 V28 DMI_TXN_0 CFG_6 J18 @ PAD T33
H_D#7 C3 B13 H_A#10 DMI_RXN1 V31
H_D#_7 H_A#_10 (17) DMI_RXN1 DMI_TXN_1
H_D#8 K9 A13 H_A#11 DMI_RXP0 V29
H_D#_8 H_A#_11 (17) DMI_RXP0 DMI_TXP_0
H_D#9 F5 G13 H_A#12 DMI_RXP1 V32
H_D#_9 H_A#_12 (17) DMI_RXP1 DMI_TXP_1
H_D#10 H_A#13
DMI
J7 H_D#_10 H_A#_13 A12
H_D#11 K7 D14 H_A#14
H_D#12 H_D#_11 H_A#_14 H_A#15
H8 H_D#_12 H_A#_15 F14
H_D#13 E5 J13 H_A#16 M_CLK_DDR0 AF33 K32
H_D#_13 H_A#_16 (11) M_CLK_DDR0 SM_CK_0 RESERVED1
H_D#14 K8 E17 H_A#17 M_CLK_DDR1 AG1 K31
H_D#_14 H_A#_17 (11) M_CLK_DDR1 SM_CK_1 RESERVED2
H_D#15 J8 H15 H_A#18 C17
H_D#16 H_D#_15 H_A#_18 H_A#19 RESERVED7
J2 H_D#_16 H_A#_19 G15 AJ1 SM_CK_2 RESERVED8 F18
H_D#17 J3 G14 H_A#20 AM30 A3
H_D#_17 H_A#_20 SM_CK_3 RESERVED9
CFG/RSVD
H_D#18 N1 A15 H_A#21
H_D#19 H_D#_18 H_A#_21 H_A#22 M_CLK_DDR#0
M5 H_D#_19 H_A#_22 B18 (11) M_CLK_DDR#0 AG33 SM_CK#_0
H_D#20 K5 B15 H_A#23 M_CLK_DDR#1 AF1
H_D#_20 H_A#_23 (11) M_CLK_DDR#1 SM_CK#_1
H_D#21 J5 E14 H_A#24
H_D#22 H_D#_21 H_A#_24 H_A#25
H3 H_D#_22 H_A#_25 H13 AK1 SM_CK#_2
H_D#23 J4 C14 H_A#26 AN30
H_D#24 H_D#_23 H_A#_26 H_A#27 SM_CK#_3
N3 A17
DDR2 MUXING
H_D#25 H_D#_24 H_A#_27 H_A#28 DDR_CKE0
M4 H_D#_25 H_A#_28 E15 (11) DDR_CKE0 AN21 SM_CKE_0
H_D#26 M3 H17 H_A#29 DDR_CKE1 AN22
H_D#_26 H_A#_29 (11) DDR_CKE1 SM_CKE_1
H_D#27 N8 D17 H_A#30 AF26
H_D#28 H_D#_27 H_A#_30 H_A#31 SM_CKE_2
N6 H_D#_28 H_A#_31 G17 AF25 SM_CKE_3
H_D#29 K3
H_D#30 H_D#_29 DDR_CS0#
N9 H_D#_30 (11) DDR_CS0# AG14 SM_CS#_0
H_D#31 M1 F10 H_ADS# DDR_CS1# AF12
H_D#_31 H_ADS# H_ADS# (4) (11) DDR_CS1# SM_CS#_1
H_D#32 V8 C12 H_ADSTB#0 AK14
H_D#_32 H_ADSTB#_0 H_ADSTB#0 (4) SM_CS#_2
H_D#33 V9 H16 H_ADSTB#1 AH12
H_D#_33 H_ADSTB#_1 H_ADSTB#1 (4) SM_CS#_3
H_D#34 R6 E2 +H_VREF
H_D#35 H_D#_34 H_VREF0 H_BNR#
T8 H_D#_35 H_BNR# B9 H_BNR# (4) AJ21 SM_OCDCOMP_0
H_D#36 R2 C7 H_BPRI# AF11 E31
HOST
H_D#_36 H_BPRI# H_BPRI# (4) SM_OCDCOMP_1 PM_ICHSYNC# MCH_ICH_SYNC# (15)

H_D#37 N5 G8 H_BR0# G21
H_D#_37 H_BREQ0# H_BR0# (4) PM_BMBUSY# PM_BMBUSY# (17)
PM
C H_D#38 H_RESET# M_ODT0 PM_EXTTS#0 C
N2 H_D#_38 H_CPURST# B10 H_RESET# (4) (11) M_ODT0 AE12 SM_ODT_0 PM_EXTTS#_0 F26 PM_EXTTS#0 (11)
H_D#39 +H_VREF +1.8V M_ODT1 PM_EXTTS#12
R5 H_D#_39 H_VREF1 E1 (11) M_ODT1 AF14 SM_ODT_1 PM_EXTTS#_1 H26 1 PM_DPRSLPVR (17,37)
H_D#40 U7 AJ14 J15 R203 0_0402_5%
H_D#41 H_D#_40 CLK_MCH_BCLK# SM_ODT_2 THRMTRIP# H_THERMTRIP#
R8 H_D#_41 HCLKN AA6 CLK_MCH_BCLK# (12) AJ12 SM_ODT_3 PWROK AB29 H_THERMTRIP# (4,16)
H_D#42 T4 AA5 CLK_MCH_BCLK W27 ICH_POK
H_D#_42 HCLKP CLK_MCH_BCLK (12) RSTIN# ICH_POK (17,25)
H_D#43 T7 C10 H_DBSY# R232 1 2 80.6_0402_1% SMRCOMPN AN12 PLTRST_R# 1 2
H_D#_43 H_DBSY# H_DBSY# (4) SM_RCOMPN PLTRST# (15,17,19,24,25,27)
H_D#44 R3 C6 H_DEFER# 1 2 SMRCOMPP AN14 R211 100_0402_5%
H_D#_44 H_DEFER# H_DEFER# (4) SM_RCOMPP
H_D#45 T5 H5 H_DINV#0 R228 80.6_0402_1% AA33
H_D#_45 H_DINV#_0 H_DINV#0 (4) SM_VREF_0
CLK
H_D#46 V6 J6 H_DINV#1 +DIMM_VREF AE1 A27
H_D#_46 H_DINV#_1 H_DINV#1 (4) SM_VREF_1 D_REFCLKN CLK_MCH_DREFCLK# (12)
H_D#47 V3 T9 H_DINV#2 10uA A26
H_D#_47 H_DINV#_2 H_DINV#2 (4) D_REFCLKP CLK_MCH_DREFCLK (12)
0.1U_0402_16V4Z
H_D#48 W2 U6 H_DINV#3 1 J33
H_D#_48 H_DINV#_3 H_DINV#3 (4) D_REFSSCLKN MCH_SSCDREFCLK# (12)
H_D#49 W1 G7 H_DPWR# Layout Note: H33
H_D#_49 H_DPWR# H_DPWR# (4) D_REFSSCLKP MCH_SSCDREFCLK (12)
C53
H_D#50 V2 E6 H_DRDY# J22
H_D#_50 H_DRDY# H_DRDY# (4) +DIMM_VREF trace CLKREQ# MCH_CLKREQ# (12)
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H_D#51 W4 F3 H_DSTBN#0
H_D#52 H_D#_51 H_DSTBN#_0 H_DSTBN#1 2 width and spacing
W7 H_D#_52 H_DSTBN#_1 M8
H_D#53 W5 T1 H_DSTBN#2 is 20/20. Calistoga-GSE_FCBGA998
H_D#54 H_D#_53 H_DSTBN#_2 H_DSTBN#3
V5 H_D#_54 H_DSTBN#_3 AA3
+VCCP H_D#55 AB4 F4 H_DSTBP#0
H_D#_55 H_DSTBP#_0 H_DSTBN#[0..3] (4)
H_D#56 AB8 M7 H_DSTBP#1
H_D#57 H_D#_56 H_DSTBP#_1 H_DSTBP#2
W8 H_D#_57 H_DSTBP#_2 T2
H_D#58 AA9 AB3 H_DSTBP#3
H_D#59 H_D#_58 H_DSTBP#_3
AA8 H_D#_59 H_DSTBP#[0..3] (4)
54.9_0402_1%
54.9_0402_1%
H_D#60 AB1 H_D#_60 Strap Pin Table

1
H_D#61 AB7 H_D#_61

R175
R6
H_D#62 AA2 C8 H_HIT#

H_D#_62 H_HIT# H_HIT# (4)
H_D#63 AB5 B4 H_HITM# Low = DMI x 2
H_D#_63 H_HITM#
C5 H_LOCK#
H_HITM# (4)
CFG5
*
H_LOCK# H_LOCK# (4)
G9 H_REQ#0 High = DMI x 4
2
H_REQ#_0 H_REQ#1
H_REQ#_1 E9
H_XRCOMP A10 G12 H_REQ#2
H_XSCOMP H_XRCOMP H_REQ#_2 H_REQ#3
A6 H_XSCOMP H_REQ#_3 B8
+H_SWNG0 C15 F12 H_REQ#4
B H_YRCOMP H_XSWING H_REQ#_4 H_RS#0 B
J1 H_YRCOMP H_RS#_0 A5 H_REQ#[0..4] (4)
H_YSCOMP K1 B6 H_RS#1
+H_SWNG1 H_YSCOMP H_RS#_1 H_RS#2
H1 H_YSWING H_RS#_2 G10
E8 H_CPUSLP#
H_SLPCPU# H_RS#[0..2] (4)
E10 H_TRDY#
H_TRDY#
H_CPUSLP# (4)
24.9_0402_1%
24.9_0402_1%
H_TRDY# (4)
1
Calistoga-GSE_FCBGA998
R182
R7
+3VS
Layout Note:
PM_EXTTS#0 1 2
H_XRCOMP / H_YRCOMP / H_VREF / H_SWNG0 / R187 10K_0402_5%
H_SWNG1 trace width and spacing is 10/20. PM_EXTTS#1 1 @ 2
R188 10K_0402_5%
+VCCP +VCCP
+VCCP
221_0402_1%
221_0402_1%
1
1
100_0402_1%
1
R167
R180
R176
A A
2
+H_SWNG0 +H_SWNG1
2
+H_VREF
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
1
100_0402_1%
100_0402_1%
0.1U_0402_16V4Z
1 1
1
200_0402_1%
R166
R178
1
R174
C243
C240
C251
C50 be placed <100mils

from GMCH pin 2 2 Security Classification Compal Secret Data Compal Electronics, Inc.
2
2
2
SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
5 4 3 2 1
D U1C DDR_A_D[0..63] (11)

D
DDR_A_BS0 AK12 AC31 DDR_A_D0
(11) DDR_A_BS0 SA_BS_0 SA_DQ_0
DDR_A_BS1 AH11 AB28 DDR_A_D1
DDR_A_BS2 AG17 AE33 DDR_A_D2
AF32 DDR_A_D3
(11) DDR_A_DM[0..7] SA_DQ_3
DDR_A_DM0 AB30 AC33 DDR_A_D4
DDR_A_DM1 SA_DM_0 SA_DQ_4 DDR_A_D5
AL31 SA_DM_1 SA_DQ_5 AB32
DDR_A_DM2 AF30 AB31 DDR_A_D6
AK26 SA_DM_3 SA_DQ_7 AE31
DDR_A_DM4 AL9 AH31 DDR_A_D8
AG7 SA_DM_5 SA_DQ_9 AK31
DDR_A_DM6 AK5 AL28 DDR_A_D10
AH3 SA_DM_7 SA_DQ_11 AK27
(11) DDR_A_DQS[0..7] AH30 DDR_A_D12
DDR_A_DQS0 AC28 SA_DQ_12 DDR_A_D13
SA_DQS_0 SA_DQ_13 AL32
DDR_A_DQS1 AJ30 AJ28 DDR_A_D14
DDR_A_DQS2 AK33 SA_DQS_1 SA_DQ_14 DDR_A_D15
SA_DQS_2 SA_DQ_15 AJ27
DDR_A_DQS3 AL25 AH32 DDR_A_D16
DDR_A_DQS4 SA_DQS_3 SA_DQ_16 DDR_A_D17
AN9 SA_DQS_4 SA_DQ_17 AF31
DDR_A_DQS5 AH8 AH27 DDR_A_D18
DDR_A_DQS6 AM2 SA_DQS_5 SA_DQ_18 DDR_A_D19
SA_DQS_6 SA_DQ_19 AF28
DDR_A_DQS7 AE3 AJ32 DDR_A_D20
SA_DQS_7 SA_DQ_20 DDR_A_D21
(11) DDR_A_DQS#[0..7] SA_DQ_21 AG31
DDR_A_DQS#0 AC29 AG28 DDR_A_D22
DDR_A_DQS#1 AK30 SA_DQS#_0 SA_DQ_22 DDR_A_D23
SA_DQS#_1 SA_DQ_23 AG27
DDR_A_DQS#2 AJ33 AN27 DDR_A_D24
DDR_A_DQS#3 AM25 SA_DQS#_2 SA_DQ_24 DDR_A_D25
AM26
DDR2 SYSTEM MEMORY

DDR_A_DQS#4 AN8 SA_DQS#_3 SA_DQ_25 DDR_A_D26
SA_DQS#_4 SA_DQ_26 AJ26
DDR_A_DQS#5 AJ8 AJ25 DDR_A_D27
DDR_A_DQS#6 AM3 SA_DQS#_5 SA_DQ_27 DDR_A_D28
SA_DQS#_6 SA_DQ_28 AL27
C DDR_A_DQS#7 AE2 AN26 DDR_A_D29 C
SA_DQS#_7 SA_DQ_29 DDR_A_D30
(11) DDR_A_MA[0..13] SA_DQ_30 AH25
DDR_A_MA0 AJ15 AG26 DDR_A_D31
DDR_A_MA1 SA_MA_0 SA_DQ_31 DDR_A_D32
AM17 SA_MA_1 SA_DQ_32 AM12
DDR_A_MA2 AM15 AL11 DDR_A_D33
AH15 SA_MA_3 SA_DQ_34 AH9
DDR_A_MA4 AK15 AK9 DDR_A_D35
AN15 SA_MA_5 SA_DQ_36 AM11
DDR_A_MA6 AJ18 AK11 DDR_A_D37
AF19 SA_MA_7 SA_DQ_38 AM8
DDR_A_MA8 AN17 AK8 DDR_A_D39
AL17 SA_MA_9 SA_DQ_40 AG9
DDR_A_MA10 AG16 AF9 DDR_A_D41
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DDR_A_MA11 AL18 SA_MA_10 SA_DQ_41 DDR_A_D42
SA_MA_11 SA_DQ_42 AF8
DDR_A_MA12 AG18 AK6 DDR_A_D43
DDR_A_MA13 AL14 SA_MA_12 SA_DQ_43 DDR_A_D44
SA_MA_13 SA_DQ_44 AF7
AG11 DDR_A_D45
DDR_A_CAS# SA_DQ_45 DDR_A_D46
(11) DDR_A_CAS# AJ17 SA_CAS# SA_DQ_46 AJ6
DDR_A_RAS# AK18 AH6 DDR_A_D47
(11) DDR_A_RAS# SA_RAS# SA_DQ_47
SA_RCVENIN# AN28 AN6 DDR_A_D48
T9 PAD SA_RCVENOUT# SA_RCVENIN# SA_DQ_48 DDR_A_D49
AM28 SA_RCVENOUT# SA_DQ_49 AM6
T8 PAD DDR_A_WE# AH17 AK3 DDR_A_D50
(11) DDR_A_WE# SA_WE# SA_DQ_50
AL2 DDR_A_D51
SA_DQ_51 DDR_A_D52
AH21 SB_BS_0 SA_DQ_52 AM5
AJ20 AL5 DDR_A_D53
SB_BS_1 SA_DQ_53 DDR_A_D54
AE27 SB_BS_2 SA_DQ_54 AJ3
AJ2 DDR_A_D55
SA_DQ_55 DDR_A_D56
AN20 SB_MA_0 SA_DQ_56 AG2
AL21 AF3 DDR_A_D57
SB_MA_1 SA_DQ_57 DDR_A_D58
AK21 SB_MA_2 SA_DQ_58 AE7
AK22 AF6 DDR_A_D59
B SB_MA_3 SA_DQ_59 B
AL22 AH5 DDR_A_D60
AH22 SB_MA_5 SA_DQ_61 AG3
AG22 AG5 DDR_A_D62
AF21 SB_MA_7 SA_DQ_63 AF5
AM21 SB_MA_8
AE21 SB_MA_9
AL20 SB_MA_10 SB_CAS# AG19
AE22 SB_MA_11 SB_RAS# AG21
AE26 SB_MA_12 SB_WE# AG20
AE20 SB_MA_13
A A

SCHEMATIC,MB A5141
Size Document Number
Rev
Custom B
401690
5 4 3 2 1
5 4 3 2 1
D D
U1F R190 +1.5VS_PCIE

24.9_0402_1%
H27 R28 PEGCOMP 1 2
SDVO_CTRLDATA EXP_A_COMPI
J27 SDVO_CTRLCLK EXP_A_ICOMPO M28
(12) CLK_MCH_3GPLL# Y26 G_CLKN
2 1 GMCH_CRT_R AA26 N30
(12) CLK_MCH_3GPLL G_CLKP SDVO_TVCLKIN#
MISC
R10 150_0402_1% R30
GMCH_CRT_G SDVO_INT#
2 1 SDVO_FLDSTALL# T29
R8 150_0402_1%
2 1 GMCH_CRT_B
R9 150_0402_1% H20 M30
(14) GMCH_CRT_CLK CRT_DDC_CLK SDVO_TVCLKIN
(14) GMCH_CRT_DATA H22 CRT_DDC_DATA SDVO_INT P30
GMCH_CRT_B A24 T30
(14) GMCH_CRT_B CRT_BLUE SDVO_FLDSTALL
A23 CRT_BLUE#
GMCH_CRT_G E25
(14) GMCH_CRT_G CRT_GREEN
F25 CRT_GREEN#
SDVO
GMCH_CRT_R C25
(14) GMCH_CRT_R CRT_RED
VGA
Close to U4.H25 D25 CRT_RED#
GMCH_CRT_VSYNC_R F27
GMCH_CRT_HSYNC_R CRT_VSYNC
D27 CRT_HSYNC
2 1 CRT_IREF H25 P28
R183 255_0402_1% CRT_IREF SDVO_RED#
SDVO_GREEN# N32
R171 2 1 100K_0402_5% H30 P32
L_BKLTCTL SDVO_BLUE#
(25) GMCH_ENBKL G29 L_BKLTEN SDVO_CLKN T32
C LCTLA_CLK F28 C
LCTLB_DATA L_CLKCTLA
E28 L_CTLBDATA
(13) LVDS_SCL LVDS_SCL G28 N28
LVDS_SDA L_DDC_CLK SDVO_RED
(13) LVDS_SDA H28 L_DDC_DATA SDVO_GREEN M32
(13) GMCH_ENVDD K30 L_VDDEN SDVO_BLUE P33
2 1 L_IBG K27 R32
R184 1.5K_0402_1% L_IBG SDVO_CLKP
J29 L_VBG +1.5VS
J30 L_VREFH
K29 L_VREFL
39_0402_5% LVDS_ACLK# D30 A21
(13) LVDS_ACLK# LA_CLKN TV_DACA
R282 1 2 GMCH_CRT_VSYNC_R LVDS_ACLK C30 C20
(14) GMCH_CRT_VSYNC (13) LVDS_ACLK LA_CLKP TV_DACB
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A30 LB_CLKN TV_DACC E20
LVDS
R296 1 2 GMCH_CRT_HSYNC_R A29 G23
(14) GMCH_CRT_HSYNC LB_CLKP TV_IREF
TV
39_0402_5%
LVDS_A0# G31
TV_IRTNA B21
C21
Disable TV
(13) LVDS_A0# LA_DATAN_0 TV_IRTNB
(13) LVDS_A1# LVDS_A1# F32 D21
LVDS_A2# LA_DATAN_1 TV_IRTNC
Place R282,R296 close to F27,D27 11/18 (13) LVDS_A2# D31 LA_DATAN_2
(13) LVDS_A0 LVDS_A0 H31
LVDS_A1 LA_DATAP_0
(13) LVDS_A1 G32 LA_DATAP_1 TV_DCONSEL0 G26
(13) LVDS_A2 LVDS_A2 C31 J26
LA_DATAP_2 TV_DCONSEL1
F33 LB_DATAN_0
D33 LB_DATAN_1
F30 LB_DATAN_2
E33 LB_DATAP_0
D32 LB_DATAP_1
B +3VS F29
B
LB_DATAP_2
1 2 LCTLA_CLK Calistoga-GSE_FCBGA998
R192 10K_0402_5%
1 2 LCTLB_DATA
R191 10K_0402_5%
A A

SCHEMATIC,MB A5141
B B
401690
5 4 3 2 1
5 4 3 2 1
+VCCP +1.5VS
U1E U1G
U1H AH33 VSS_1
T25 VCC_NCTF1 VCCAUX_NCTF1 AD25 Y33 VSS_2 VSS_111 J16 W33 NC1 NC61 W30
R25 VCC_NCTF2 VCCAUX_NCTF2 AC25 V33 VSS_3 VSS_112 AL15 AM33 NC2 NC62 Y6
P25 VCC_NCTF3 VCCAUX_NCTF3 AB25 R33 VSS_4 VSS_113 AG15 AL33 NC3 NC63 AL1
N25 VCC_NCTF4 VCCAUX_NCTF4 AD24 G33 VSS_5 VSS_114 W15 C33 NC4 NC64 Y5
M25 VCC_NCTF5 VCCAUX_NCTF5 AC24 AK32 VSS_6 VSS_115 R15 B33 NC5 NC65 Y10
P24 VCC_NCTF6 VCCAUX_NCTF6 AD22 AG32 VSS_7 VSS_116 F15 AN32 NC6 NC66 W10
N24 VCC_NCTF7 VCCAUX_NCTF7 AD21 AE32 VSS_8 VSS_117 D15 A32 NC7 NC67 W25
M24 VCC_NCTF8 VCCAUX_NCTF8 AD20 AC32 VSS_9 VSS_118 AM14 AN31 NC8 NC68 V24
Y22 VCC_NCTF9 VCCAUX_NCTF9 AD19 AA32 VSS_10 VSS_119 AH14 W28 NC9 NC69 U24
W22 VCC_NCTF10 VCCAUX_NCTF10 AD18 U32 VSS_11 VSS_120 AE14 V27 NC10 NC70 V10
V22 VCC_NCTF11 VCCAUX_NCTF11 AD17 H32 VSS_12 VSS_121 H14 W29 NC11 NC71 U10
D D
U22 VCC_NCTF12 VCCAUX_NCTF12 AD16 E32 VSS_13 VSS_122 B14 J24 NC12 NC72 K18
T22 VCC_NCTF13 VCCAUX_NCTF13 AD15 C32 VSS_14 VSS_123 F13 H24 NC13
R22 VCC_NCTF14 VCCAUX_NCTF14 AD14 AM31 VSS_15 VSS_124 D13 W32 NC14
P22 VCC_NCTF15 VCCAUX_NCTF15 K14 AJ31 VSS_16 VSS_125 AL12 G24 NC15
N22 VCC_NCTF16 VCCAUX_NCTF16 AD13 AA31 VSS_17 VSS_126 AG12 F24 NC16
M22 VCC_NCTF17 VCCAUX_NCTF17 Y13 U31 VSS_18 VSS_127 H12 E24 NC17
Y21 VCC_NCTF18 VCCAUX_NCTF18 W13 T31 VSS_19 VSS_128 B12 D24 NC18
W21 VCC_NCTF19 VCCAUX_NCTF19 V13 R31 VSS_20 VSS_129 AN11 K33 NC19
V21 VCC_NCTF20 VCCAUX_NCTF20 U13 P31 VSS_21 VSS_130 AJ11 A31 NC20
U21 VCC_NCTF21 VCCAUX_NCTF21 T13 N31 VSS_22 VSS_131 AE11 E21 NC21
T21 VCC_NCTF22 VCCAUX_NCTF22 R13 M31 VSS_23 VSS_132 AM9 C23 NC22
R21 VCC_NCTF23 VCCAUX_NCTF23 P13 J31 VSS_24 VSS_133 AJ9 AN19 NC23
P21 VCC_NCTF24 VCCAUX_NCTF24 N13 F31 VSS_25 VSS_134 AB9 AM19 NC24
N21 VCC_NCTF25 VCCAUX_NCTF25 M13 AL30 VSS_26 VSS_135 W9 AL19 NC25
M21 VCC_NCTF26 VCCAUX_NCTF26 AD12 AG30 VSS_27 VSS_136 R9 AK19 NC26
Y20 VCC_NCTF27 VCCAUX_NCTF27 Y12 AE30 VSS_28 VSS_137 M9 AJ19 NC27
W20 VCC_NCTF28 VCCAUX_NCTF28 W12 AC30 VSS_29 VSS_138 J9 AH19 NC28
V20 VCC_NCTF29 VCCAUX_NCTF29 V12 AA30 VSS_30 VSS_139 F9 AN3 NC29
NC
U20 VCC_NCTF30 VCCAUX_NCTF30 U12 Y30 VSS_31 VSS_140 C9 Y9 NC30
T20 VCC_NCTF31 VCCAUX_NCTF31 T12 V30 VSS_32 VSS_141 A9 J19 NC31
R20 VCC_NCTF32 VCCAUX_NCTF32 R12 U30 VSS_33 VSS_142 AL8 H19 NC32
P20 VCC_NCTF33 VCCAUX_NCTF33 P12 G30 VSS_34 VSS_143 AG8 G19 NC33
N20 VCC_NCTF34 VCCAUX_NCTF34 N12 E30 VSS_35 VSS_144 AE8 F19 NC34
M20 VCC_NCTF35 VCCAUX_NCTF35 M12 B30 VSS_36 VSS_145 U8 E19 NC35
Y19 VCC_NCTF36 VCCAUX_NCTF36 AD11 AA29 VSS_37 VSS_146 AA7 D19 NC36
P19 VCC_NCTF37 VCCAUX_NCTF37 AD10 U29 VSS_38 VSS_147 V7 C19 NC37
N19 VCC_NCTF38 VCCAUX_NCTF38 K10 R29 VSS_39 VSS_148 R7 B19 NC38
M19 VCC_NCTF39 VSS_NCTF1 AN33 P29 VSS_40 VSS_149 N7 A19 NC39 RESERVED26 Y25
Y18 VCC_NCTF40 VSS_NCTF2 AA25 N29 VSS_41 VSS_150 H7 Y8 NC40 RESERVED27 Y24
P18 V25 M29 E7 G16 AB22
C
N18
M18
Y17
VCC_NCTF41
VCC_NCTF42
VCC_NCTF43
NCTF VSS_NCTF3
VSS_NCTF4
VSS_NCTF5
U25
AA22
AA21
H29
E29
B29
VSS_42
VSS_43
VSS_44
VSS_151
VSS_152
VSS_153
B7
AL6
AG6
F16
E16
D16
NC41
NC42
NC43
RESERVED28
RESERVED29
RESERVED30
AB21
AB19
AB16 C
VCC_NCTF44 VSS_NCTF6 VSS_45 VSS_154 NC44 RESERVED31
P17 VCC_NCTF45 VSS_NCTF7 AA20 AK28 VSS_46 VSS_155 AE6 C16 NC45 RESERVED32 AB14
N17 VCC_NCTF46 VSS_NCTF8 AA19 AH28 VSS_47 VSS_156 AB6 B16 NC46 RESERVED33 AA12
M17 VCC_NCTF47 VSS_NCTF9 AA18 AE28 VSS_48 VSS_157 W6 AN2 NC47 RESERVED34 W24
Y16 VCC_NCTF48 VSS_NCTF10 AA17 AA28 VSS_49 VSS_158 T6 A16 NC48 RESERVED35 AA24
P16 VCC_NCTF49 VSS_NCTF11 AA16 U28 VSS_50 VSS_159 M6 Y7 NC49 RESERVED36 AB24
N16 VCC_NCTF50 VSS_NCTF12 AA15 T28 VSS_51 VSS_160 K6 AM4 NC50 RESERVED37 AB20
VSS
M16 VCC_NCTF51 VSS_NCTF13 AA14 J28 VSS_52 VSS_161 AN5 AF4 NC51 RESERVED38 AB18
Y15 VCC_NCTF52 VSS_NCTF14 AA13 D28 VSS_53 VSS_162 AJ5 AD4 NC52 RESERVED39 AB15
P15 VCC_NCTF53 VSS_NCTF15 A4 AM27 VSS_54 VSS_163 B5 AL4 NC53 RESERVED40 AB13
N15 VCC_NCTF54 VSS_NCTF16 A33 AF27 VSS_55 VSS_164 AA4 AK4 NC54 RESERVED41 AB12
M15 VCC_NCTF55 VSS_NCTF17 B2 AB27 VSS_56 VSS_165 V4 W31 NC55 RESERVED42 AB17
Y14 VCC_NCTF56 VSS_NCTF18 AN1 AA27 VSS_57 VSS_166 R4 AJ4 NC56
www.manuals.clan.su
W14 VCC_NCTF57 VSS_NCTF19 C1 Y27 VSS_58 VSS_167 N4 AH4 NC57
V14 VCC_NCTF58 U27 VSS_59 VSS_168 K4 AG4 NC58
U14 VCC_NCTF59 CFG_19 K28 T27 VSS_60 VSS_169 H4 AE4 NC59
T14 VCC_NCTF60 R27 VSS_61 VSS_170 E4 AM1 NC60
R14 VCC_NCTF61 RESERVED10 K25 P27 VSS_62 VSS_171 AL3
P14 VCC_NCTF62 RESERVED11 K26 N27 VSS_63 VSS_172 AD3
N14 VCC_NCTF63 RESERVED12 R24 M27 VSS_64 VSS_173 W3
+VCCP M14 T24 G27 T3 Calistoga-GSE_FCBGA998
VCC_NCTF64 RESERVED13 VSS_65 VSS_174
RESERVED14 K21 E27 VSS_66 VSS_175 B3
T10 VTT_NCTF1 RESERVED15 K19 C27 VSS_67 VSS_176 AK2
R10 VTT_NCTF2 RESERVED16 K20 B27 VSS_68 VSS_177 AH2
P10 VTT_NCTF3 RESERVED17 K24 AL26 VSS_69 VSS_178 AF2
N10 VTT_NCTF4 RESERVED18 K22 AH26 VSS_70 VSS_179 AB2
L10 VTT_NCTF5 RESERVED19 J17 W26 VSS_71 VSS_180 M2
D1 VTT_NCTF6 RESERVED20 K23 U26 VSS_72 VSS_181 K2
RESERVED21 K17 AN25 VSS_73 VSS_182 H2
M10 RSVD_3 RESERVED22 K12 AK25 VSS_74 VSS_183 F2
A18 RSVD_4 RESERVED23 K13 AG25 VSS_75 VSS_184 V1
AB10 RSVD_5 RESERVED24 K16 AE25 VSS_76 VSS_185 R1
B B
AA10 RSVD_6 RESERVED25 K15 J25 VSS_77
G25 VSS_78
Calistoga-GSE_FCBGA998 A25 VSS_79
H23 VSS_80
F23 VSS_81
B23 VSS_82
AM22 VSS_83
AJ22 VSS_84
AF22 VSS_85
G22 VSS_86
E22 VSS_87
J21 VSS_88
H21 VSS_89
F21 VSS_90
AM20 VSS_91
AK20 VSS_92
AH20 VSS_93
AF20 VSS_94
D20 VSS_95
W19 VSS_96
R19 VSS_97
AM18 VSS_98
AH18 VSS_99
AF18 VSS_100
U18 VSS_101
H18 VSS_102
D18 VSS_103
AK17 VSS_104
V17 VSS_105
T17 VSS_106
F17 VSS_107
B17 VSS_108
A A
AH16 VSS_109
U16 VSS_110

SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
5 4 3 2 1
+VCCP +1.5VS
2940mA
U1D 144mA
T26 B20
R26
P26
VCC0
VCC1
VCCATVDACA0
VCCATVDACA1 A20
B22
PCI-E/MEM/PSB PLL decoupling
VCC2 VCCATVDACB0
220U_B2_2.5VM_R35
N26 VCC3 VCCATVDACB1 A22 Disable TV
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
M26 VCC4 VCCATVDACC0 D22
V19 C22 +1.5VS_3GPLL +1.5VS
1 VCC5 VCCATVDACC1
1 1 1 1 1 U19 D23 R210
VCC6 VCCATVBG
C37
+
C41
C39
C261
C265
C266
T19 E23 +1.5VS_3GPLL 2 1 +1.5VS
VCC7 VSSATVBG
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
W18 VCC8 VCCDTVDAC F20
V18 F22 0_0603_5%
2 2 2 2 2 2 VCC9 VCCDQTVDAC
T18 VCC10 VCCDLVDS0 C28 20mA +1.5VS 1 1 1
R18 VCC11 VCCDLVDS1 B28
C277
C278
C287
D D
W17 VCC12 VCCDLVDS2 A28
10U_0805_10V4Z
0.1U_0402_16V4Z
U17 E26 40mA +3VS @
VCC13 VCCHV0 2 2 2
R17 VCC14 VCCHV1 D26 1 1
10U_0805_10V4Z
0.1U_0402_16V4Z
W16 VCC15 VCCHV2 C26
C24
V16 AB33 U4_AB33 10mil 1 1
VCC16 VCCSM0
C235
T16 AM32 U4_AM32
VCC17 VCCSM1 2 2
C23
+VCCP
R16 VCC18 VCCSM2 AN29 10mil
C239
V15 VCC19 VCCSM3 AM29
2 2
1U_0603_10V6K
1U_0603_10V6K
U15 VCC20 VCCSM4 AL29 1 1
T15 VCC21 VCCSM5 AK29
2
C318
C286
VCCSM6 AJ29
+1.5VS_MPLL
45mA Max. +1.5VS_HPLL 45mA Max.
D15 @ AD33 AH29 R45 R38
VCCAUX1 VCCSM7 2 2 0_0603_5% 0_0603_5%
AD32 VCCAUX2 VCCSM8 AG29
RB751V-40TE17_SOD323-2 AD31 AF29 2 1 +1.5VS 2 1 +1.5VS
VCCAUX3 VCCSM9 +1.8V
AD30 AE29
+VCCP_D 1
VCCAUX4 VCCSM10
10U_0805_10V4Z
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5VS
AD29 VCCAUX5 VCCSM11 AN24 533 MTS=1720mA
AD28 VCCAUX6 VCCSM12 AM24
AD27 VCCAUX7 VCCSM13 AL24 1 1 1 1
1250mA AC27 VCCAUX8 VCCSM14 AK24
1U_0603_10V6K
C48
C52
C43
C44
4.7U_0603_6.3V6M
4.7U_0603_6.3V6M
AD26 VCCAUX9 VCCSM15 AJ24
0.1U_0402_16V4Z
AC26 VCCAUX10 VCCSM16 AH24

2 2 2 2
AB26 VCCAUX11 VCCSM17 AG24 1 1 1
1
1 AE19 VCCAUX12 VCCSM18 AF24

+2.5VS
C250
C288
C330
C293
R168 AE18 AE24
@ VCCAUX13 VCCSM19
AF17 VCCAUX14 VCCSM20 AN18 10mil 2 2 2
10_0402_5% AE17 AN16
2 VCCAUX15 VCCSM21
AF16 AM16
2
VCCAUX16 VCCSM22
AE16 VCCAUX17 VCCSM23 AL16
AF15 VCCAUX18 VCCSM24 AK16 1
AE15 VCCAUX19 VCCSM25 AJ16
J14 AN13 C319
VCCAUX20 VCCSM26 1U_0402_6.3V4Z
J10 VCCAUX21 VCCSM27 AM13
C 2 C
H10 VCCAUX22 VCCSM28 AL13
+1.5VS_DPLLB
40mA Max. +1.5VS_DPLLA
40mA Max.
AE9 AK13
To be confirmed 11/14 +VCCP
AD9
U9
VCCAUX23
VCCAUX24
VCCSM29
VCCSM30 AJ13
AH13 1 2
L20
1 2
L2
VCCAUX25 VCCSM31 +1.5VS +1.5VS
FBM-L10-160808-301-T_0603 FBM-L10-160808-301-T_0603
add net name(+VCCP_D) AD8 VCCAUX26 VCCSM32 AG13
0.1U_0402_16V4Z
0.1U_0402_16V4Z
330U_D2_2.5VY_R9M
780mA AD7 VCCAUX27 VCCSM33 AF13
220U_B2_2.5VM_R35
20mil 12/10 C25 AD6 VCCAUX28 VCCSM34 AE13 1 1
VCCSM35 AN4 10mil 1 1
C257
C236
C13
1 2 10mil U4_A14 A14 AM10 + +
VTT0 VCCSM36
C268
D10 VTT1 VCCSM37 AL10
P9 AK10 <BOM Structure>
VTT2 VCCSM38 2 2 2 2
1U_0603_10V6K
0.47U_0603_16V4Z L9 AH1 10mil 1
VTT3 VCCSM39
D9 VTT4 VCCSM40 AH10
C329
www.manuals.clan.su
P8 VTT5 VCCSM41 AG10
L8 VTT6 VCCSM42 AF10
2
1U_0603_10V6K
D8 VTT7 VCCSM43 AE10 1
P7 VTT8 VCCSM44 AN7 change C249 BOM structure(@) 01/23
C54
C22 L7
D7
VTT9 VCCSM45 AM7
AL7
Co-layout with C249
U4_A7 VTT10 VCCSM46 2
1 210mil A7 VTT11 VCCSM47 AK7 add C268 01/22 Del C249 02/18
P6 VTT12 VCCSM48 AJ7
L6 VTT13 VCCSM49 AH7
0.47U_0603_16V4Z G6 AN10
VTT14 VCCSM50
POWER
D6 VTT15 VCCSM51 AJ10

220U_B2_2.5VM_R35
U5 VTT16 VCCAMPLL AD1 +1.5VS_MPLL 45mA +2.5VS
0.1U_0402_16V4Z
P5 VTT17 VCCAHPLL AD2 +1.5VS_HPLL 45mA
1 L5 VTT18 VCCADPLLA B26 +1.5VS_DPLLA 50mA
G5 VTT19 VCCADPLLB J32 +1.5VS_DPLLB 50mA 1
C40
+ D5 VTT20 VCCDHMPLL1 AE5 +1.5VS 150mA

Y4 AD5 Route +2.5VS from GMCH pinN33 to C267
VTT21 VCCDHMPLL2 +1.5VS_PCIE
2
U4 VTT22 VCCTXLVDS0 D29 +2.5VS 60mA decoupling cap <200mil to the edge. 2
P4 C29 R177
B VTT23 VCCTXLVDS1 B
L4 VTT24 VCC3G0 U33 400mA 2 1 +1.5VS
G4 T33 0_0805_5%
VTT25 VCC3G1
220U_B2_2.5VM_R35
D4 VTT26 VCCA3GPLL V26400mA +1.5VS_3GPLL CRTDAC: Route FB 1
+2.5VS
10U_0805_10V4Z
10U_0805_10V4Z
Y3 VTT27 VCCA3GBG N33 2mA +2.5VS within 3" of Calistoga 1 1
U3 M33 +
VTT28 VSSA3GBG
C254
C253
C259
4.7U_0805_6.3V6K
4.7U_0805_6.3V6K
P3 VTT29 VCCSYNC J23 70mA

1 1 L3 C24 +2.5VS_CRTDAC 70mA 2 R172 1 +2.5VS
VTT30 VCCACRTDAC0 2 2 2
10U_0805_10V4Z
0.1U_0402_16V4Z
G3 B24 10_0603_5%
VTT31 VCCACRTDAC1
C281
C276
0.022U_0402_16V7K
10U_0805_10V4Z
0.1U_0402_16V4Z
D3 B25 1 1 @
VTT32 VSSACRTDAC
Y2 VTT33 VCCALVDS B31 10mA +2.5VS 1 1 1
2 2
C256
C245
U2 B32 +VCCP
VTT34 VSSALVDS
C242
C244
P2 VTT36 2 2
C241
L2 VTT35 VTT41 P1
2 2 2
G2 VTT37 VTT42 L1
D2 VTT38 VTT43 G1
10mil U4_AA1 AA1 U1
U4_F1 VTT39 VTT44
F1 VTT40 VTT45 Y1
10mil
2 2 Calistoga-GSE_FCBGA998
C283 C248 +2.5VS +2.5VS

0.47U_0603_16V4Z 0.47U_0603_16V4Z
1 1 Route VSSACRTDAC gnd from GMCH to
decoupling cap ground lead and then
connect to the gnd plane.
0.01U_0402_25V7K
4.7U_0805_6.3V6K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 1 1 1
C260
C247
C237
C246
2 2 2 2
A A
close pin C29/D29 close pin B31

SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
5 4 3 2 1
+1.8V +1.8V
JDIM1
(7) DDR_A_DQS#[0..7] +DIMM_VREF 1 VREF VSS 2
+1.8V 3 4 DDR_A_D4
DDR_A_D0 VSS DQ4 DDR_A_D5
(7) DDR_A_D[0..63] 5 DQ0 DQ5 6
DDR_A_D1 7 8
DQ1 VSS
1
(7) DDR_A_DM[0..7] 9 10 DDR_A_DM0
R41 DDR_A_DQS#0 VSS DM0
Layout Note: 11 DQS0# VSS 12
(7) DDR_A_DQS[0..7] DDR_A_DQS0 13 14 DDR_A_D6
Place near JDIM1 1K_0402_1% 15
DQS0 DQ6
16 DDR_A_D7
DDR_A_D2 VSS DQ7
(7) DDR_A_MA[0..13] 17 18
2
DDR_A_D3 DQ2 VSS DDR_A_D12
+DIMM_VREF 19 DQ3 DQ12 20
21 22 DDR_A_D13
VSS DQ13
1
D DDR_A_D9 D
23 DQ8 VSS 24
R43 Share +DIMM_VREF for DDR_A_D8 25 26 DDR_A_DM1
DQ9 DM1
27 28
1K_0402_1% 1.DDRII VREF DDR_A_DQS#1 29
VSS VSS
30 M_CLK_DDR0
DQS1# CK0 M_CLK_DDR0 (6)
+1.8V 2.GMCH SM_VREF_0 DDR_A_DQS1 31 32 M_CLK_DDR#0 M_CLK_DDR#0 (6)
2
DQS1 CK0#
33 34
SM_VREF_1 DDR_A_D10 35
VSS VSS
36 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
37 DQ11 DQ15 38
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
39 VSS VSS 40
+DIMM_VREF
2 2 2 2 2
20mils
C91
C90
C89
C70
C71
41 VSS VSS 42
DDR_A_D16 43 44 DDR_A_D20
1 1 1 1 1 DDR_A_D17 DQ16 DQ20 DDR_A_D21
1 1 45 DQ17 DQ21 46
C86 C92 47 48
DDR_A_DQS#2 VSS VSS R54
49 DQS2# NC 50 1 2 PM_EXTTS#0 (6)
0.1U_0402_16V4Z 2.2U_0603_6.3V6K DDR_A_DQS2 51 52 DDR_A_DM2 0_0402_5%
2 2 DQS2 DM2
53 VSS VSS 54
57 DQ19 DQ23 58
220U_B2_2.5VM_R35
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 59 VSS VSS 60
1 1 1 1 DDR_A_D24 61 62 DDR_A_D28
+ DDR_A_D25 DQ24 DQ28 DDR_A_D29
63 DQ25 DQ29 64
C61
C69
C68
C88
C87
@ For EMI DDR issue 65 66

DDR_A_DM3 VSS VSS DDR_A_DQS#3
67 DM3 DQS3# 68
2 2 2 2 2 DDR_A_DQS3
69 NC DQS3 70
71 VSS VSS 72
del C94 C95 01/22 DDR_A_D27 75
DQ26 DQ30
76 DDR_A_D31
DQ27 DQ31
77 VSS VSS 78
(6) DDR_CKE0 DDR_CKE0 79 80 DDR_CKE1 DDR_CKE1 (6)
CKE0 NC/CKE1
81 VDD VDD 82
C C
83 NC NC/A15 84
(7) DDR_A_BS2 DDR_A_BS2 85 86
BA2 NC/A14
87 VDD VDD 88
DDR_A_MA12 89 90 DDR_A_MA11
DDR_A_MA9 A12 A11 DDR_A_MA7
91 A9 A7 92
DDR_A_MA8 93 94 DDR_A_MA6
A8 A6
95 VDD VDD 96
Layout Note: DDR_A_MA5 97 98 DDR_A_MA4
DDR_A_MA3 A5 A4 DDR_A_MA2
99 100
Place one cap close to every 2 pullup DDR_A_MA1 101
A3 A2
102 DDR_A_MA0
A1 A0
resistors terminated to +0.9VS 103 VDD VDD 104
DDR_A_MA10 105 106 DDR_A_BS1 DDR_A_BS1 (7)
DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
(7) DDR_A_BS0 107 BA0 RAS# 108 DDR_A_RAS# (7)
www.manuals.clan.su
(7) DDR_A_WE# DDR_A_WE# 109 110 DDR_CS0# DDR_CS0# (6)
WE# S0#
111 VDD VDD 112
(7) DDR_A_CAS# DDR_A_CAS# 113 114 M_ODT0 M_ODT0 (6)
DDR_CS1# CAS# ODT0 DDR_A_MA13
(6) DDR_CS1# 115 NC/S1# NC/A13 116
117 VDD VDD 118
(6) M_ODT1 M_ODT1 119 120
+0.9VS NC/ODT1 NC
121 VSS VSS 122
DDR_A_D32 123 124 DDR_A_D36
125 DQ33 DQ37 126
127 VSS VSS 128
DDR_A_DQS#4 129 130 DDR_A_DM4
DDR_A_DQS4 DQS4# DM4
131 DQS4 VSS 132
133 134 DDR_A_D38
VSS DQ38
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDR_A_D34 135 136 DDR_A_D39

DDR_A_D35 DQ34 DQ39
1 1 1 1 1 1 1 1 1 1 1 1 1 137 DQ35 VSS 138
139 140 DDR_A_D44
VSS DQ44
C79
C84
C104
C81
C103
C102
C83
C82
C101
C99
C78
C80
C100
DDR_A_D40 141 142 DDR_A_D45

DDR_A_D41 DQ40 DQ45
143 DQ41 VSS 144
2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_DQS#5
B add JDIM1 pin 200 and pin 201 to GND DDR_A_DM5
145
147
VSS DQS5# 146
148 DDR_A_DQS5 B
DM5 DQS5
01/20 DDR_A_D42
149 VSS VSS 150
DDR_A_D46
151 DQ42 DQ46 152
DDR_A_D43 153 154 DDR_A_D47
DQ43 DQ47
155 VSS VSS 156
DDR_A_D48 157 158 DDR_A_D52
159 DQ49 DQ53 160
161 VSS VSS 162
163 164 M_CLK_DDR1 M_CLK_DDR1 (6)
NC,TEST CK1 M_CLK_DDR#1
165 VSS CK1# 166 M_CLK_DDR#1 (6)
DDR_A_DQS#6 167 168
DDR_A_DQS6 DQS6# VSS DDR_A_DM6
return the H5.2 pootprint 11/24 169 DQS6 DM6 170
+0.9VS 171 172
RP1 RP5 DDR_A_D50 VSS VSS DDR_A_D54
173 DQ50 DQ54 174
DDR_A_MA0 1 8 8 1 DDR_A_RAS# DDR_A_D51 175 176 DDR_A_D55
DDR_A_MA13 DDR_A_MA4 DQ51 DQ55
2 7 7 2 177 VSS VSS 178
DDR_CS0# 3 6 6 3 DDR_A_MA2 DDR_A_D56 179 180 DDR_A_D60
M_ODT0 DDR_A_BS1 +3VS DDR_A_D57 DQ56 DQ60 DDR_A_D61
4 5 5 4 181 DQ57 DQ61 182
Layout Note: 183 VSS VSS 184
0.1U_0402_16V4Z
56_0804_8P4R_5% 56_0804_8P4R_5% Place these resistor DDR_A_DM7 185 186 DDR_A_DQS#7

RP2 RP6 DM7 DQS7# DDR_A_DQS7
closely DIMMA,all 1 187 VSS DQS7 188
DDR_A_MA1 1 8 8 1 DDR_CKE1 C361 DDR_A_D58 189 190
DDR_A_MA3 DDR_A_MA7 trace length<750 mil DDR_A_D59 DQ58 VSS DDR_A_D62
2 7 7 2 191 DQ59 DQ62 192
DDR_A_MA5 3 6 6 3 DDR_A_MA6 193 194 DDR_A_D63
DDR_A_CAS# DDR_A_MA11 2 CLK_SMBDATA VSS DQ63
4 5 5 4 (12,19) CLK_SMBDATA 195 SDA VSS 196
(12,19) CLK_SMBCLK CLK_SMBCLK 197 198 R53 1 2 10K_0402_5%
56_0804_8P4R_5% 56_0804_8P4R_5% SCL SAO R52
+3VS 199 VDDSPD SA1 200 1 2 10K_0402_5%
RP3 RP4 201 202
DDR_A_WE# GND GND
1 8 8 1 DDR_A_MA12
DDR_A_BS0 2 7 7 2 DDR_A_MA9 P-TWO_A5652C-A0G16
M_ODT1 3 6 6 3 DDR_A_MA8 CONN@
DDR_CS1# 4 5 5 4 DDR_A_MA10
A A
56_0804_8P4R_5% 56_0804_8P4R_5% DIMMA
change DIMMA from H5.2 to H4 11/17
DDR_A_BS2 1 R159 2
Layout Note:
Place these resistor
56_0402_5%
closely DIMMA,all Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
DDR_CKE0 1 R160 2
56_0402_5% trace length
SCHEMATIC,MB A5141
Max=1.3" AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401690
5 4 3 2 1
5 4 3 2 1
+3VM_CK505
add C164,C165 01/22
FBMA-L11-201209-221LMA30T_0805 0.1U_0402_16V4Z
FSC FSB FSA CPU SRC PCI REF DOT_96 USB 2 1
+3VS change R112,R108,Q10A,Q10B
CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 1 1 1 1 1 1 1 1 1 1 1
C159 C164 C165 L11 C151 C181 C175 C197 C199 C155 C154 BOM structure 11/20
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C834
0 0 0 266 100 33.3 14.318 96.0 48.0 47P_0402_50V8J 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 2 2 2 2 2 2 2 2 2 2
+3VS
Close to L11
R112
2.2K_0402_5%
0 0 1 133 100 33.3 14.318 96.0 48.0 @
+1.05VM_CK505 @ R108
0 1 0 200 100 33.3 14.318 96.0 48.0 0.1U_0402_16V4Z
+VCCP L12 2 1 R150 0_0402_5% 2.2K_0402_5%
FBMA-L11-201209-221LMA30T_0805 1 1 1 1 1 1 1 1 1 2
0 1 1 166 100 33.3 14.318 96.0 48.0 C163 C198 C152 C153 C167 C189 C200
D C851 D
47P_0402_50V8J 10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z (17) ICH_SMBDATA 6 1 CLK_SMBDATA
2 2 2 2 2 2 2 2
1 0 0 333 100 33.3 14.318 96.0 48.0
Close to L12 2N7002DW-T/R7_SOT363-6 @ Q10A
2
1 0 1 100 100 33.3 14.318 96.0 48.0 move C159 from P11 to P12 01/22 +3VS
5
1 1 0 400 100 33.3 14.318 96.0 48.0 2N7002DW-T/R7_SOT363-6 @ Q10B
(17) ICH_SMBCLK 3 4 CLK_SMBCLK
1 1 1 Reserved SA000020K00 (Silego : SLG8SP556VTR ) 1 2

+3VS R149
SA000020H10 (ICS : ICS9LPRS387AKLFT) add R149,R150 11/20 0_0402_5%
1 2 H_STP_PCI#
R645 @ 10K_0402_5%
change R141,R140,R147,R81,R91 +3VM_CK505 U11

R82,R97,R95,R98 BOM structure 12/29 9 CLK_SMBDATA
del R143 and CLK_SD_48M 11/21 SDA CLK_SMBDATA (11,19)
change R141,R140,R147,R81,R91
55 VDD_SRC
SCL 10 CLK_SMBCLK
CLK_SMBCLK (11,19)
SRC PORT LIST
6 VDD_REF
R82,R97,R95,R98 BOM structure 01/17 Change R137 from 12 ohm CLK_CPU_BCLK
12 VDD_PCI CPU_0 71 CLK_CPU_BCLK (4)
+VCCP
to 33 ohm 11/21
72 70 CLK_CPU_BCLK#
PORT DEVICE
VDD_CPU CPU_0# CLK_CPU_BCLK# (4)
2
change R137 BOM structure 12/15 19 VDD_48 CPU_1 68 CLK_MCH_BCLK

CLK_MCH_BCLK (6) SRC0 MCH_DREFCLK
R140 @ CLK_MCH_BCLK#
R138 56_0402_5%
add R143 12/15 27 VDD_PLL3 CPU_1# 67 CLK_MCH_BCLK# (6) SRC2 SATA HDD
2.2K_0402_5%
SRC3 MCH_3GPLL
1
FSA 2 1 1 2 CLK_MCH_DREFCLK
C MCH_CLKSEL0 (6) del R143 12/15 +1.05VM_CK505 66 VDD_CPU_IO SRC_0/DOT_96 24 CLK_MCH_DREFCLK (6) C
(4) CPU_BSEL0 1 2 R142 31 25 CLK_MCH_DREFCLK#

CLK_MCH_DREFCLK# (6)
SRC4 PCIE_CARDREADER
R147 1K_0402_5% VDD_PLL3_IO SRC_0#/DOT_96#
0_0402_5% 62
SRC6 PCIE_WLAN
VDD_SRC_IO
1
<BOM Structure> MCH_SSCDREFCLK

52
LCDCLK/27M 28 MCH_SSCDREFCLK (6) SRC7 PCIE_WWAN
R141 <BOM Structure> VDD_SRC_IO MCH_SSCDREFCLK#
1K_0402_5% 23
LCDCLK#/27M_SS 29 MCH_SSCDREFCLK# (6) SRC8
VDD_IO
change R137 from 33 to SRC9 PCIE_LAN
2
38 32 CLK_PCIE_SATA
39 ohm 02/06 VDD_SRC_IO SRC_2 CLK_PCIE_SATA (16)
change C32 from 10P to SRC10 PCIE_ICH
33 CLK_PCIE_SATA#
+VCCP 15p ohm 02/06 SRC_2# CLK_PCIE_SATA# (16)
1 2 FSA 20
SRC11
www.manuals.clan.su
C32 (17) CLK_ICH_48M USB_0/FS_A
R137 39_0402_5% 35 CLK_MCH_3GPLL
SRC_3 CLK_MCH_3GPLL (8)
2
FSB 2
R81 <BOM Structure> 15P_0402_50V8J FS_B/TEST_MODE CLK_MCH_3GPLL#
SRC_3# 36 CLK_MCH_3GPLL# (8)
33_0402_5% 1 2 R101 FSC 7
1K_0402_5% (17) CLK_ICH_14M <BOM Structure> REF_0/FS_C/TEST_
C33 2 1 10P_0402_50V8J 8 39 CLK_PCIE_CARD
CLK_PCIE_CARD (27)
1
FSB <BOM Structure> REF_1 SRC_4

1 2 MCH_CLKSEL1 (6)
40 CLK_PCIE_CARD#
SRC_4# CLK_PCIE_CARD# (27)
1 2 R86 VGATE 1
(4) CPU_BSEL1 (17,25,37) VGATE CKPWRGD/PD#
R91 1K_0402_5%
0_0402_5% 11 57 CLK_PCIE_WLAN
NC SRC_6 CLK_PCIE_WLAN (19)
1
<BOM Structure>
change C32 C33 C42 C45 56 CLK_PCIE_WLAN#
SRC_6# CLK_PCIE_WLAN# (19)
R82 @
0_0402_5% BOM structre 12/14 H_STP_CPU# 53
(17) H_STP_CPU# CPU_STOP# CLK_PCIE_WWAN
61 CLK_PCIE_WWAN (19)
2
H_STP_PCI# SRC_7
54 PCI_STOP#
(17) H_STP_PCI# 60 CLK_PCIE_WWAN#
SRC_7# CLK_PCIE_WWAN# (19)
CLK_XTAL_IN
B +VCCP add C45 for keypart 12/14 5 XTAL_IN
64 B
CLK_XTAL_OUT SRC_8/CPU_ITP
add C32,C33,C42 4 XTAL_OUT
change C42,C45 from SRC_8#/CPU_ITP# 63
2
for keypart 12/08

R97 <BOM Structure> 22p to 15p 02/06 CLK_PCIE_LAN +3VS
13 PCI_1 SRC_9 44 CLK_PCIE_LAN (24)
R100 1K_0402_5%
C42
10K_0402_5% PCI2_TME 14 45 CLK_PCIE_LAN# MCH_CLKREQ# R139 2 1 10K_0402_5%
CLK_PCIE_LAN# (24)
1
FSC PCI_2 SRC_9# SATA_CLKREQ# R111 10K_0402_5%

2 1 1 2 MCH_CLKSEL2 (6) 2 1
15P_0402_50V8J 15 WLAN_CLKREQ# R84 2 1 10K_0402_5%
R99 PCI_3 CLK_PCIE_ICH WWAN_CLKREQ# R85 10K_0402_5%
(4) CPU_BSEL2 1 2 SRC_10 50 CLK_PCIE_ICH (17) 2 1
R95 1K_0402_5% 1 2 PCI4_SEL 16
0_0402_5%
change R115,R121 from (25) CLK_PCI_LPC
R115 47_0402_5% PCI_4/SEL_LCDCL
51 CLK_PCIE_ICH#
SRC_10# CLK_PCIE_ICH# (17)
1
<BOM Structure> 39 ohm to 47 ohm 02/06 1 2 ITP_EN 17

(15) CLK_PCI_ICH PCIF_5/ITP_EN
R121 47_0402_5%
R98 @
0_0402_5%
change c45 from C45 2 1
SRC_11 48
REQ PORT LIST
15p to 10p 02/24 18 47
2
10P_0402_50V8J VSS_PCI SRC_11#

3 VSS_REF PORT DEVICE
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP# 22 37 MCH_CLKREQ#
VSS_48 CLKREQ_3# MCH_CLKREQ# (6)
1 = Pin24/25 : SRC_0 / SRC_0#
26 41
REQ_3# MCH_3GPLL
Pin28/29 : 27M/27M_SS VSS_IO CLKREQ_4#
For PCI4_SEL, 0 = Pin24/25 : DOT96 / DOT96# 69 58 WLAN_CLKREQ#
WLAN_CLKREQ# (19)
REQ_4#
VSS_CPU CLKREQ_6#
For PCI2_TME:0=Overclocking of CPU and SRC allowed Pin28/29 : LCDCLK / LCDCLK# 30 65 WWAN_CLKREQ#
WWAN_CLKREQ# (19)
REQ_6# PCIE_WLAN
VSS_PLL3 CLKREQ_7#
(ICS only) 1=Overclocking of CPU and SRC NOT allowed 34 43
REQ_7# PCIE_WWAN
VSS_SRC CLKREQ_9#
+3VS 59 49
REQ_9#
VSS_SRC SLKREQ_10#
42 46
REQ_10#
VSS_SRC CLKREQ_11#
2
A
Del R129 12/14 R109 73 21 SATA_CLKREQ#
SATA_CLKREQ# (17)
REQ_11# A
CLK_XTAL_IN VSS USB_1/CLKREQ_A#
C169 27P_0402_50V8J 10K_0402_5% REQ_A# SATA
1
SLG8SP556VTR_QFN72_10X10
1
Y2
14.31818MHZ_16PF_DSX840GA ITP_EN PCI4_SEL PCI2_TME
<BOM Structure>
2
1 2 CLK_XTAL_OUT
2
C162 22P_0402_50V8J
R132 R117 Security Classification Compal Secret Data Compal Electronics, Inc.
Routing the trace at least 10mil Del R110, Issued Date 2007/10/15 Deciphered Date 2007/8/18 Title
10K_0402_5% 10K_0402_5%
R119 01/17 SCHEMATIC,MB A5141
1
change C162 from 27P to 22P 01/23 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
401690
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT

CMOS Camera CONN
+LCDVDD +LCDVDD AO3413_SOT23 +3VS
1/3 Change Q30
W=20mils W=20mils
S
1 3
R563 +3VS
300_0603_5%
J13 change +3VS to
@
D D
<BOM Structure> 1 2 +CAM_VCC +CAM_VCC 11/16
G
+3VS
2
C668 1 1 2
1 1
2
restore R563,Q31 0.1U_0402_16V4Z C669 C670
JUMP_43X39
2
4.7U_0603_6.3V6K
1+LCDVDD_R
BOM structure 11/20 4.7U_0805_10V4Z @
R564 1 2 2 2
C671
100K_0402_5%
0.047U_0402_16V4Z
reserve +3VALW 11/16 1
1
Q31 2
D C3
<BOM Structure> 2 2 1
change BOM structure 0.1U_0402_16V4Z
2N7002W-T/R7_SOT323-3 G 11/14 del +3VALW 11/17 2
S R565 4.7K_0402_5%
3
del JP1 11/26
1 Q68
return D2 pin define 12/08
DTC115EUA_SC70-3
(8) GMCH_ENVDD 2 SWAP D2 pin define 12/05

3
D2
C USB20_P1 C
6 CH3 CH2 3
change to JAQ10 circuit 11/14
change +3VS to 5 2
+CAM_VCC Vp Vn
+CAM_VCC 11/16
4 1 USB20_N1
CH4 CH1
CM1293-04SO_SOT23-6
<BOM Structure>
www.manuals.clan.su
LCD/PANEL BD. Conn.
change JLVDS1 Conn form 20 pin SWAP JLVDS1 12/02
to 30 pin 11/26 (17) USB20_N1
USB20_N1 USB20_N1_1
move R441,R438 form USB20_P1 USB20_P1_1

(17) USB20_P1
P13 to P20 12/02
JLVDS1
LVDS_A1 1 2
(8) LVDS_A1
LVDS_A1# 1 2 USB20_N1_1
+CAM_VCC del L8,R145,R146 02/20
LVDS (8) LVDS_A1# 3
5
3 4 4
6 USB20_P1_1
camera
LVDS_A0 5 6
(8) LVDS_A0 7 7 8 8
(8) LVDS_A0# LVDS_A0# 9 10 DMIC_CLK_R
9 10 DMIC_CLK_R (20)
11 12 DMIC_DATA_R change D2 P/N from SC300000O00
LVDS_A2 13
11 12
14
DMIC_DATA_R (20) DMIC
B
(8) LVDS_A2 13 14 to SC300000B00 and BOM structure 12/22 B
(8) LVDS_A2# LVDS_A2# 15 16 +3VS
15 16
17 17 18 18
LVDS_ACLK 19 20 LVDS_SDA
(8) LVDS_ACLK 19 20
LVDS_ACLK# 21 22 LVDS_SCL
(8) LVDS_ACLK# 21 22
23 23 24 24
BKOFF# 25 26 FBMA-L11-201209-221LMA30T_0805
(25) BKOFF# 25 26
For panel ADJ INVT_PWM 27 28 +LEDVDD L7 2 1 B+ 400mA
(25) INVT_PWM 27 28
280mA +LCDVDD 2 1 +LCDVDD_L 29 30
FBMA-L11-201209-221LMA30T_0805 L6 29 30
(20 MIL) 2 1
31
32
GND1 C368 C362
C362L7 12/05
GND2
2 330P_0402_50V7K 100P_0402_50V8J
C5 ACES_88242-3001 1 2
CONN@
combine the DMIC Conn
1000P_0402_50V7K
1
and Camera Conn 11/26 +3VS
DMIC_CLK_R
DMIC_DATA_R
10K_0402_5%
10K_0402_5%
2
2
R44
R42
3
add C5 for keypart 12/08 2

1
1
D17 C603
47P_0402_50V8J LVDS_SCL LVDS_SCL (8)
PJDLC05_SOT23-3 1
For ESD 10/11 LVDS_SDA LVDS_SDA (8)
A A
1
change C603 from 220P to 100P 01/23

change D17 P/N from SCA00000700

to SCA00000A00 and BOM structure 12/22 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
SCHEMATIC,MB A5141
B B
401690
5 4 3 2 1
A B C D E
change D3,D4 P/N from SCA00000G00

to SCA00000A00 and BOM structure 12/22
Close to CRT CONN for ESD.
change D3,D4 BOM structure(@) 03/01
2
D3 D4
1 PJDLC05_SOT23-3 PJDLC05_SOT23-3 1
1
@ @
Place closed to chipset L1
BK1608LL121-T 0603
1 2 RED
(8) GMCH_CRT_R
L3
BK1608LL121-T 0603
1 2 GREEN
(8) GMCH_CRT_G
L4
BK1608LL121-T 0603
1 2 BLUE
(8) GMCH_CRT_B
150_0402_1%
150_0402_1%
150_0402_1%
1
1
1 1 1
R5 R13 R19 C12 C30 C35 1 1 1
C7 C20 C29
2 2 2 10P_0402_50V8J 10P_0402_50V8J 10P_0402_50V8J
2 +CRT_VCC change to +5VS 11/14
2
10P_0402_50V8J 2 2 2
10P_0402_50V8J 10P_0402_50V8J
+5VS JVGA_HS
1 2
R281 39_0402_5%
1 2
C38 0.1U_0402_16V4Z 1 2 JVGA_VS
R287 39_0402_5%
1
2 U15 2
1 1
OE#
2 4 CRT_HSYNC_1
(8) GMCH_CRT_HSYNC A Y C232 C31
G
10P_0402_50V8J 10P_0402_50V8J
SN74AHCT1G125DCKR_SC70-5 2 2
3
+5VS
Place closed to chipset
1 2
C234 0.1U_0402_16V4Z change L5,L19(BK61608LL121-T0603)
1
U4
to R281,R287(39_0402) 11/14
OE#
www.manuals.clan.su
2 4 CRT_VSYNC_1
(8) GMCH_CRT_VSYNC A Y
G
SN74AHCT1G125DCKR_SC70-5
3
change JCRT1 Conn to SP010811273 12/04

CRT PORT
+CRT_VCC
+5VS
C36
+3VS D6 0.1U_0402_16V4Z
W=40mils
2 1 1 2
+CRT_VCC RB491D_SC59-3 JCRT1
6
1
11
3 R165 2.2K_0402_5% RED 1 3
+3VS 7
2.2K_0402_5% R163 VGA_DDC_DAT 12
1
GREEN 2
2
R16 R164 8 G 16
JVGA_HS 13 17
2.2K_0402_5% 2.2K_0402_5% BLUE G
3
9
2
2
5
JVGA_VS 14
4
4 3 VGA_DDC_DAT 10
(8) GMCH_CRT_DATA VGA_DDC_CLK 15
Q14B 1 5
2
2N7002DW-T/R7_SOT363-6 C400 SUYIN_070546FR015S290ZR

1 6 VGA_DDC_CLK 100P_0402_50V8J CONN@
(8) GMCH_CRT_CLK 2
Q14A CRT_DET# (17)

2N7002DW-T/R7_SOT363-6
2
R293
100K_0402_5%
1
+CRT_VCC
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E
5 4 3 2 1
D D
+3VS
U6B
R260 1 2 8.2K_0402_5% PCI_DEVSEL# E18 D7 PCI_REQ#0
AD0 REQ0#
C18 AD1 GNT0# E7
R263 1 2 8.2K_0402_5% PCI_STOP# PCI_REQ#1
A16
F18
AD2 PCI REQ1# C16
D16
R262 1 AD3 GNT1#
2 8.2K_0402_5% PCI_TRDY# E16 AD4 REQ2# C17 PCI_REQ#2
A18 AD5 GNT2# D17
R264 1 2 8.2K_0402_5% PCI_FRAME# E17 E13 PCI_REQ#3
AD6 REQ3#
A17 AD7 GNT3# F13
R259 1 2 8.2K_0402_5% PCI_PLOCK# A15 A13 PCI_REQ#4
AD8 REQ4# / GPIO22
C14 AD9 GNT4# / GPIO48 A14
R256 1 2 8.2K_0402_5% PCI_IRDY# E14 C8 PCI_REQ#5
AD10 GPIO1 / REQ5#
D14 AD11 GPIO17 / GNT5# D8
R258 1 2 8.2K_0402_5% PCI_SERR# B12 AD12
C13 AD13 C/BE0# B15
R257 1 2 8.2K_0402_5% PCI_PERR# G15
G13
AD14 C/BE1# C12
D12
del R244(100K_0402)
AD15 C/BE2#
E12 AD16 C/BE3# C15 and add T17 11/14
C11 AD17
C +3VS D11 A7 PCI_IRDY# C
AD18 IRDY#
A11 AD19 PAR E10
A10 AD20 PCIRST# B18
R254 1 2 8.2K_0402_5% PCI_PIRQA# F11 A12 PCI_DEVSEL# PAD T17
AD21 DEVSEL# PCI_PERR#
F10 AD22 PERR# C9
R255 1 2 8.2K_0402_5% PCI_PIRQB# E9 E11 PCI_PLOCK#
AD23 PLOCK# PCI_SERR#
D9 AD24 SERR# B10
R271 1 2 8.2K_0402_5% PCI_PIRQC# B9 F15 PCI_STOP#
AD25 STOP# PCI_TRDY#
A8 AD26 TRDY# F14
R270 1 2 8.2K_0402_5% PCI_PIRQD# A6 F16 PCI_FRAME#
AD27 FRAME#
C7 AD28
R276 1 2 8.2K_0402_5% PCI_PIRQE# B6 C26 PLTRST#_R
AD29 PLTRST#
www.manuals.clan.su
E6 A9 CLK_PCI_ICH Place closely pin A9
AD30 PCICLK CLK_PCI_ICH (12)
R272 1 2 8.2K_0402_5% PCI_PIRQF# D6 B19
AD31 PME#
R275 1 2 8.2K_0402_5% PCI_PIRQG# CLK_PCI_ICH
Interrupt I/F
2
R273 1 2 8.2K_0402_5% PCI_PIRQH# PCI_PIRQA# A3 G8 PCI_PIRQE#
PCI_PIRQB# PIRQA# GPIO2 / PIRQE# PCI_PIRQF# @
B4 PIRQB# GPIO3 / PIRQF# F7
R274 1 2 8.2K_0402_5% PCI_REQ#0 PCI_PIRQC# C5 F8 PCI_PIRQG# R246
PCI_PIRQD# PIRQC# GPIO4 / PIRQG# PCI_PIRQH# 10_0402_5%
B5 PIRQD# GPIO5 / PIRQH# G7
R265 1 2 8.2K_0402_5% PCI_REQ#1
1
R266 1 2 8.2K_0402_5% PCI_REQ#2 AE5
MISC AE9
RSVD[1] RSVD[6] 1
AD5 AG8 @
R261 1 RSVD[2] RSVD[7]
2 8.2K_0402_5% PCI_REQ#3 AG4 RSVD[3] RSVD[8] AH8 C359
AH4 F21 8.2P_0402_50V8D
R277 1 RSVD[4] RSVD[9] 2
2 8.2K_0402_5% PCI_REQ#4 AD9 RSVD[5] MCH_SYNC# AH20 MCH_ICH_SYNC# (6)
B R278 1 B
2 8.2K_0402_5% PCI_REQ#5
ICH7_BGA652
+3VS
@
C297
1 2
0.1U_0402_16V4Z
5
U16 @
PLTRST#_R 1
P
B
Y 4 PLTRST# (6,17,19,24,25,27)
2 A
1
TC7SH08FUF_SSOP5
3
R227
100K_0402_5%
1 2
2
R226 0_0402_5%
A A

SCHEMATIC,MB A5141
B
401690
5 4 3 2 1
5 4 3 2 1
change C49 C50 from 18pf to 10pf 01/23

C49
D ICH_RTCX1 D
2 1 10P_0402_50V8J
+RTCVCC
10M_0402_5%
Y1
1
32.768K_1TJS125BJ4A421P
R37
R214 1M_0402_5% 2 NC IN 1
1 2 SM_INTRUDER#
3 NC OUT 4
R216 332K_0402_1% U6A
LPC_AD[0..3] (25)
2
1 2 ICH_INTVRMEN
RTC
C50 AB1 AA6 LPC_AD0
ICH_RTCX2 RTXC1 LAD0 LPC_AD1
2 1 10P_0402_50V8J AB2 RTCX2 LAD1 AB5
AC4 LPC_AD2
R217 1 ICH_RTCRST# LAD2 LPC_AD3
+RTCVCC 2 AA3 RTCRST# LAD3 Y6
LPC
20K_0402_5%
ICH_INTVRMEN W4 AC3
change R204 BOM structure
INTVRMEN LDRQ0#
+RTCVCC
Del J6 and add R219 2/18 SM_INTRUDER# Y5 INTRUDER# LDRQ1# / GPIO23 AA5 11/14
1 R219 2
@ 0_0603_5% AB3 LPC_FRAME#
LFRAME# LPC_FRAME# (25)
W1 EE_CS Move R204 from P16 to P25
2 Y1
C294 C317 Y2
EE_SHCLK
AE22 GATEA20 11/18
EE_DOUT A20GATE GATEA20 (25)
LAN
1U_0603_10V4Z W3 AH28 H_A20M#
EE_DIN A20M# H_A20M# (4)
CPU
0.1U_0402_16V4Z 1 2
1
change J6 jump size form 43 x 118 V3 LAN_CLK CPUSLP# AG27
to shortpads 11/14 U3 LAN_RSTSYNC TP1 / DPRSTP# AF24 H_DPRSTP#

H_DPSLP#
H_DPRSTP# (4,37)
2 TP2 / DPSLP# AH25 H_DPSLP# (4)
C21 U5 2 1 56_0402_5%
22P_0402_50V8J
add C21 for keypart 12/31 V4
LAN_RXD0
AG26 H_FERR# R20
+VCCP
LAN_RXD1 FERR# H_FERR# (4)
1 change C21 from 10p to 22p 01/23 T5 LAN_RXD2
AG24 H_PWRGOOD
GPIO49 / CPUPWRGD H_PWRGOOD (4)
(20) HDA_SYNC_AUDIO 1 2 HDA_SYNC_ICH U7
C R235 39_0402_5% LAN_TXD0 H_IGNNE# C
V6 LAN_TXD1 IGNNE# AG22 H_IGNNE# (4)
(20) HDA_BITCLK_AUDIO 1 2 HDA_BITCLK_ICH V7 AG21
R230 39_0402_5% LAN_TXD2 INIT3_3V# H_INIT#
INIT# AF22 H_INIT# (4)
(20) HDA_RST_AUDIO# 1 2 HDA_RST_ICH# AF25 H_INTR
INTR H_INTR (4)
R236 39_0402_5%
+VCCP
AC-97/AZALIA
(20) HDA_SDOUT_AUDIO 1 2 HDA_SDOUT_ICH HDA_BITCLK_ICH U1
R233 39_0402_5% HDA_SYNC_ICH ACZ_BCLK KB_RST#
R6 ACZ_SYNC RCIN# AG23 KB_RST# (25)
1
HDA_RST_ICH# R5 AF23 H_SMI#
ACZ_RST# SMI# H_SMI# (4)
AH24 H_NMI R194
+3VS NMI H_NMI (4)
(20) HDA_SDIN0 T2 ACZ_SDIN0
T3 AH22 H_STPCLK# 56_0402_5%
ACZ_SDIN1 STPCLK# H_STPCLK# (4)
T1
2
ACZ_SDIN2
1
www.manuals.clan.su
AF26 THRMTRIP_ICH# 1 R196 2
THERMTRIP# H_THERMTRIP# (4,6)
R610 HDA_SDOUT_ICH T4 24.9_0402_1%
ACZ_SDOUT
10K_0402_5%
add C9 for keypart 12/08 AH17 Layout note: R196 needs to placed
SATA_LED# DA0
del C9 12/31 (26) SATA_LED# AF18 AE17 within 2" of ICH7, R194 must be placed
2
SATALED# DA1
AF17
DA2 within 2" of R196 w/o stub.
SATA_LED# (22) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 AF3 AE16
SATA_DTX_C_IRX_P0 SATA0RXN DCS1#
(22) SATA_DTX_C_IRX_P0 AE3 SATA0RXP DCS3# AD16
SATA_ITX_DRX_N0 AG2 SATA0TXN
SATA
SATA_ITX_DRX_P0 AH2 SATA0TXP
DD0 AB15
SATA_DTX_C_IRX_N2 AF7 AE14
SATA_DTX_C_IRX_P2 SATA2RXN DD1
AE7 SATA2RXP DD2 AG13
AG6 SATA2TXN DD3 AF13
AH6 SATA2TXP DD4 AD14
DD5 AC13
CLK_PCIE_SATA# AF1 AD12
(12) CLK_PCIE_SATA# SATA_CLKN DD6
CLK_PCIE_SATA AE1 AC12
B (12) CLK_PCIE_SATA SATA_CLKP DD7 B
DD8 AE12
AH10 SATARBIASN DD9 AF12
R613 1 2 24.9_0402_1% SATARBIAS AG10 AB13
SATARBIASP DD10
10mils DD11 AC14
DD12 AF14
AH13 +RTCBATT
DD13
IDE DD14 AH14
IDE_DIORDY AG16 AC15
IORDY DD15
2
IDE_IRQ AH16 IDEIRQ R432
AF16 DDACK#
SATA_ITX_DRX_N0 1 2 SATA_ITX_C_DRX_N0 AH15 AE15 1K_0402_5%
C824 3900P_0402_50V7K SATA_ITX_C_DRX_N0 (22) DIOW# DDREQ
AF15 DIOR#
1 1
SATA_ITX_DRX_P0 1 2 SATA_ITX_C_DRX_P0
C823 3900P_0402_50V7K SATA_ITX_C_DRX_P0 (22) ICH7_BGA652 D31
close ICH7 +RTCVCC
2
+3VS
BAS40-04_SOT23-3
+CHGRTC
2 1 R23 IDE_DIORDY 1
4.7K_0402_5% C528
1 2 SATA_DTX_C_IRX_N2 2 1 R36 IDE_IRQ 0.1U_0402_16V4Z

R285 1K_0402_5% 8.2K_0402_5% 2
1 2 SATA_DTX_C_IRX_P2
R283 1K_0402_5%
A A
SATA_RXn/p need tie to ground when SATA port no used

SCHEMATIC,MB A5141
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 401690 B
5 4 3 2 1
5 4 3 2 1
+3VS Place closely pin B2 Place closely pin AC1
CLK_ICH_48M CLK_ICH_14M
+3VALW +3VALW
1
10K_0402_5% +3VS
R21 1 2 SERIRQ R245 R212
2
2
2
8.2K_0402_5% R55 R56 R207 @ 10_0402_5% @ 10_0402_5%
R22 1 2 PM_CLKRUN# R251 R252 8.2K_0402_5%
2
2.2K_0402_5% 2.2K_0402_5% U6C
D 10K_0402_5% 10K_0402_5% D
1 1
1
(12) ICH_SMBCLK ICH_SMBCLK C22 AF19 C355 C275
1
ICH_SMBDATA SMBCLK GPIO21 / SATA0GP
(12) ICH_SMBDATA B22 SMBDATA GPIO19 / SATA1GP AH18
SMB
SATA
GPIO
LINKALERT# A26 AH19 @ 4.7P_0402_50V8C @ 4.7P_0402_50V8C
ICH_SMLINK0 LINKALERT# GPIO36 / SATA2GP 2 2
B25 SMLINK0 GPIO37 / SATA3GP AE19
ICH_SMLINK1 A25 SMLINK1
+3VALW +3VALW
R59 AC1 CLK_ICH_14M
CLK14 CLK_ICH_14M (12)
Clocks
10K_0402_5% 1 2 ICH_RI# A28 B2 CLK_ICH_48M
RI# CLK48 CLK_ICH_48M (12)
R269 1 2 LINKALERT# 8.2K_0402_5%
SB_SPKR A19
(20) SB_SPKR SPKR
10K_0402_5% PAD T4 SUS_STAT# A27 C20 ICH_SUSCLK T16 PAD
R267 1 SUS_STAT# SUSCLK
2 ITP_DBRESET# ITP_DBRESET# A22 SYS_RST# change R24 BOM structure 11/17
SYS
B24 PM_SLP_S3#
SLP_S3# PM_SLP_S3# (25)
10K_0402_5% PM_BMBUSY# AB18 D23 PM_SLP_S4# PM_SLP_S4# (25)
R268 1 (6) PM_BMBUSY# GPIO0 / BM_BUSY# SLP_S4#
2 OCP# SLP_S5# F22 PM_SLP_S5# PM_SLP_S5# (25) Move R24 from P17 to P25 11/18
OCP# B23
@ 10K_0402_5% GPIO11 / SMBALERT# ICH_POK
PWROK AA4 ICH_POK (6,25)
R224 1 2 SPI_MISO H_STP_PCI# AC20
POWER MGT
+3VS (12) H_STP_PCI# GPIO18 / STPPCI#
GPIO
H_STP_CPU# AF21 AC22 PM_DPRSLPVR
(12) H_STP_CPU# GPIO20 / STPCPU# GPIO16 / DPRSLPVR PM_DPRSLPVR (6,37)
@ 10K_0402_5%
R223 1 2 SB_SPI_CS# A21 GPIO26 TP0 / BATLOW# C21 ICH_LOW_BAT#
2
R148 B21 C23 PBTN_OUT#
GPIO27 PWRBTN# PBTN_OUT# (25)
10K_0402_5% E23 GPIO28
1K_0402_5% High: CRT Plugged C19 PLTRST#
LAN_RST# PLTRST# (6,15,19,24,25,27)
R241 1 2 ICH_PCIE_WAKE# PM_CLKRUN# AG18
1
CRT_DET GPIO32 / CLKRUN# EC_RSMRST#
RSMRST# Y4 EC_RSMRST# (25)
8.2K_0402_5% R26 10K_0402_5% +3VS
AC19 GPIO33 / AZ_DOCK_EN#
1
D
R250 2 1 ICH_LOW_BAT# U2 GPIO34 / AZ_DOCK_RST# 1 2 R279 R280
2 Q11
C (14) CRT_DET# C
@ 10K_0402_5% G 2N7002W-T/R7_SOT323-3 ICH_PCIE_WAKE# F20 E20 EC_SCI#
(19) ICH_PCIE_WAKE# WAKE# GPIO9 EC_SCI# (25)
R222 1 2 SPI_MOSI S SERIRQ AH21 A20 ACIN
(25) SERIRQ ACIN (25,31)
3
EC_THERM# SERIRQ GPIO10

(25) EC_THERM# AF20 THRM# GPIO12 F19
E19 EC_LID_OUT#
GPIO13 EC_LID_OUT# (25)
2
VGATE AD22 R4 10K_0402_5% 10K_0402_5%
(12,25,37) VGATE VRMPWRGD GPIO14
E22 R279 R280
GPIO15
GPIO24 R3 10K_0402_5% 10K_0402_5% 80@ A0@
CRT_DET
change Q11 from SOT23 AC21
AC18
GPIO6 GPIO GPIO25 D20
AD21 SATA_CLKREQ#
60@ 60@
SATA_CLKREQ# (12)
1
GPIO7 GPIO35 / SATAREQ#
to SOT323-3 11/14 (25) EC_SMI#
EC_SMI# E21 GPIO8 GPIO38 AD20
GPIO39 AE20
ICH7_BGA652
2
www.manuals.clan.su
R294 R295
10K_0402_5% 10K_0402_5%
A0@ 80@
U6D
1
PCIE_PTX_C_IRX_N1 F26 V26 DMI_RXN0
(19) PCIE_PTX_C_IRX_N1 PERn1 DMI0RXN DMI_RXN0 (6)
PCIE_PTX_C_IRX_P1 F25 V25 DMI_RXP0
(19) PCIE_PTX_C_IRX_P1 PERp1 DMI0RXP DMI_RXP0 (6)
WLAN (19) PCIE_ITX_C_PRX_N1 C73 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N1 E28 U28 DMI_TXN0 DMI_TXN0 (6)
PETn1 DMI0TXN
DIRECT MEDIA INTERFACE

(19) PCIE_ITX_C_PRX_P1 C75 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P1 E27 U27 DMI_TXP0 DMI_TXP0 (6)
PETp1 DMI0TXP
PCIE_PTX_C_IRX_N2 H26 Y26 DMI_RXN1
(27) PCIE_PTX_C_IRX_N2 PERn2 DMI1RXN DMI_RXN1 (6)
PCIE_PTX_C_IRX_P2 H25 Y25 DMI_RXP1
(27) PCIE_PTX_C_IRX_P2 PERp2 DMI1RXP DMI_RXP1 (6)
SDIO (27) PCIE_ITX_C_PRX_N2 C66 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N2 G28 W28 DMI_TXN1 DMI_TXN1 (6)
C67 PETn2 DMI1TXN
(27) PCIE_ITX_C_PRX_P2 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P2 G27 PETp2 DMI1TXP W27 DMI_TXP1 DMI_TXP1 (6) add R279,R280,R294,R295 02/04
PCI-EXPRESS
PCIE_PTX_C_IRX_N3 K26 AB26
(24) PCIE_PTX_C_IRX_N3 PERn3 DMI2RXN
LAN PCIE_PTX_C_IRX_P3 K25 AB25 change R279,R280,R294,R295 BOM structure 02/18
(24) PCIE_PTX_C_IRX_P3 PERp3 DMI2RXP
(24) PCIE_ITX_C_PRX_N3 C60 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N3 J28 AA28
C64 PETn3 DMI2TXN
(24) PCIE_ITX_C_PRX_P3 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_P3 J27 PETp3 DMI2TXP AA27
B B
PCIE_PTX_C_IRX_N4 M26 AD25
(19) PCIE_PTX_C_IRX_N4 PERn4 DMI3RXN
3G/WIMAX PCIE_PTX_C_IRX_P4 M25 AD24
(19) PCIE_PTX_C_IRX_P4 PERp4 DMI3RXP
(19) PCIE_ITX_C_PRX_N4 C106 2 1 0.1U_0402_16V7K PCIE_ITX_PRX_N4 L28 AC28
C130 2 PETn4 DMI3TXN
(19) PCIE_ITX_C_PRX_P4 1 0.1U_0402_16V7K PCIE_ITX_PRX_P4 L27 PETp4 DMI3TXP AC27
P26 AE28 CLK_PCIE_ICH#

PERn5 DMI_CLKN CLK_PCIE_ICH# (12)
P25 AE27 CLK_PCIE_ICH
PERp5 DMI_CLKP CLK_PCIE_ICH (12)
N28 PETn5
N27 C25 R243 24.9_0402_1% Within 500 mils
PETp5 DMI_ZCOMP DMI_IRCOMP
DMI_IRCOMP D25 1 2 +1.5VS
T25
change USB OC# circuit 11/14 T24
PERn6
PERp6 USBP0N F1 USB20_N0
USB20_N0 (28)
R28 F2 USB20_P0
R27
PETn6 USBP0P
G4 USB20_N1
USB20_P0 (28) USB1(Left)
PETp6 USBP1N USB20_N1 (13)
USB20_P1
R2
USBP1P G3
H1 USB20_N2
USB20_P1 (13) CMOS Camera
+3VALW SPI_CLK USBP2N USB20_N2 (22)
SB_SPI_CS# USB20_P2
P6 SPI_CS# USBP2P H2 USB20_P2 (22) USB2(Right)
SPI
P1 J4 USB20_N3
SPI_ARB USBP3N USB20_N3 (22)
USB20_P3
SPI_MOSI P5
USBP3P J3
K1 USB20_N4
USB20_P3 (22) USB3(Right)
SPI_MOSI USBP4N USB20_N4 (19)
SPI_MISO P2 K2 USB20_P4
USB_OC# 1 R289 2 SPI_MISO USBP4P
L4 USB20_N5
USB20_P4 (19) WLAN
USBP5N USB20_N5 (19)
10K_0402_5% L5 USB20_P5
D3
USBP5P
M1 USB20_N6
USB20_P5 (19) 3G/WIMAX
(28) USB_OC#0 OC0# USBP6N USB20_N6 (19)
USB20_P6
C4
D5
OC1# USB USBP6P M2
N4 USB20_N7
USB20_P6 (19) BT
(28) USB_OC#2_3 OC2# USBP7N USB20_N7 (22)
USB_OC#2_3 R290 2 USB20_P7
1
10K_0402_5%
D4
E5
OC3# USBP7P N3 USB20_P7 (22) Card reader
OC4# R242 22.6_0402_1%
ADD USB_OC#2_3 C3 OC5# / GPIO29
A2 D2 USBRBIAS 1 2
11/14 USB_OC# B3
OC6# / GPIO30 USBRBIAS#
D1
A USB_OC#0 R288 2 OC7# / GPIO31 USBRBIAS A
1
10K_0402_5%
Within 500 mils
ICH7_BGA652

SCHEMATIC,MB A5141
5 4 3 2 1
5 4 3 2 1
U6F +VCCP U6E

0.94A A4 VSS[0] VSS[98] P28
6mA ICH_V5REF_RUN G10 L11 0.1U_0402_16V4Z A23 R1
V5REF[1] Vcc1_05[1] VSS[1] VSS[99]
Vcc1_05[2] L12 B1 VSS[2] VSS[100] R11
AD17 V5REF[2] Vcc1_05[3] L14 1 B8 VSS[3] VSS[101] R12
+1.5VS L16 B11 R13
Vcc1_05[4] 1 1 VSS[4] VSS[102]
10mA ICH_V5REF_SUS F6 L17 C336 C316 + C252 B14 R14
V5REF_Sus Vcc1_05[5] VSS[5] VSS[103]
0.77A Vcc1_05[6] L18 B17 VSS[6] VSS[104] R15
0.1U_0402_16V4Z AA22 M11 220U_B2_2.5VM_R35 B20 R16
Vcc1_5_B[1] Vcc1_05[7] 2 2 2 VSS[7] VSS[105]
1 AA23 Vcc1_5_B[2] Vcc1_05[8] M18 B26 VSS[8] VSS[106] R17
1 1 1 AB22 Vcc1_5_B[3] Vcc1_05[9] P11 B28 VSS[9] VSS[107] R18
+5VS +3VS C93 + C279 C305 C349 AB23 P18 C2 T6
D 220U_B2_2.5VM_R35 Vcc1_5_B[4] Vcc1_05[10] 1U_0603_10V4Z VSS[10] VSS[108] D
AC23 Vcc1_5_B[5] Vcc1_05[11] T11 C6 VSS[11] VSS[109] T12
AC24 Vcc1_5_B[6] Vcc1_05[12] T18 C27 VSS[12] VSS[110] T13
1
2 2 2 2
AC25 Vcc1_5_B[7] Vcc1_05[13] U11 D10 VSS[13] VSS[111] T14
R237 D21 AC26 U18 D13 T15
0.1U_0402_16V4Z 0.1U_0402_16V4Z Vcc1_5_B[8] Vcc1_05[14] VSS[14] VSS[112]
AD26 Vcc1_5_B[9] Vcc1_05[15] V11 D18 VSS[15] VSS[113] T16
100_0402_5% RB751V-40TE17_SOD323-2 AD27 V12 D21 T17
Vcc1_5_B[10] Vcc1_05[16] VSS[16] VSS[114]
AD28 V14 D24 U4
2
Vcc1_5_B[11] Vcc1_05[17] VSS[17] VSS[115]

ICH_V5REF_RUN
Place closely pin D26 Vcc1_5_B[12] Vcc1_05[18] V16 E1 VSS[18] VSS[116] U12
D27 Vcc1_5_B[13] Vcc1_05[19] V17 E2 VSS[19] VSS[117] U13
1 D28,T28,AD28. D28 V18 E4 U14
C343 Vcc1_5_B[14] Vcc1_05[20] VSS[21] VSS[118]
E24 Vcc1_5_B[15] E8 VSS[22] VSS[119] U15
E25 Vcc1_5_B[16] Vcc3_3 / VccHDA U6 +3VS E15 VSS[23] VSS[120] U16
1U_0603_10V4Z E26 56mA 1 F3 U17
2 Vcc1_5_B[17] C296 VSS[24] VSS[121]
F23 Vcc1_5_B[18] VccSus3_3/VccSusHDA R7 +3VALW F4 VSS[25] VSS[122] U24
F24 10mA +VCCP F5 U25
Vcc1_5_B[19] 0.1U_0402_16V4Z VSS[26] VSS[123]
G22 Vcc1_5_B[20] V_CPU_IO[1] AE23 F12 VSS[27] VSS[124] U26
2
G23 Vcc1_5_B[21] V_CPU_IO[2] AE26 F27 VSS[28] VSS[125] V2
H22 Vcc1_5_B[22] V_CPU_IO[3] AH26 14mA F28 VSS[29] VSS[126] V13
0.1U_0402_16V4Z
0.1U_0402_16V4Z
4.7U_0805_10V4Z
H23 Vcc1_5_B[23] G1 VSS[30] VSS[127] V15
+5VALW +3VALW J22 AA7 G2 V24
Vcc1_5_B[24] Vcc3_3[3] +3VS 1 1 1 VSS[31] VSS[128]
J23 Vcc1_5_B[25] Vcc3_3[4] AB12 0.27A G5 VSS[32] VSS[129] V27
C273
C274
C262
K22 Vcc1_5_B[26] Vcc3_3[5] AB20 1 G6 VSS[33] VSS[130] V28
1
D11 K23 AC16 C285 G9 W6

R64 @ Vcc1_5_B[27] Vcc3_3[6] 2 2 2 VSS[34] VSS[131]
L22 Vcc1_5_B[28] Vcc3_3[7] AD13 G14 VSS[35] VSS[132] W24
L23 AD18 0.1U_0402_16V4Z G18 W25
10_0402_5% RB751V-40TE17_SOD323-2 to be confirmed 11/14 M22
Vcc1_5_B[29]
Vcc1_5_B[30]
Vcc3_3[8]
Vcc3_3[9] AG12
2
G21
VSS[36]
VSS[37]
VSS[133]
VSS[134] W26
M23 AG15 G24 Y3
2
ICH_V5REF_SUS Vcc1_5_B[31] Vcc3_3[10] VSS[38] VSS[135]

N22 Vcc1_5_B[32] Vcc3_3[11] AG19 G25 VSS[39] VSS[136] Y24
N23 Vcc1_5_B[33] G26 VSS[40] VSS[137] Y27
1 P22 Vcc1_5_B[34] Vcc3_3[12] A5 +3VS H3 VSS[41] VSS[138] Y28
C C346 C
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P23 Vcc1_5_B[35] Vcc3_3[13] B13 H4 VSS[42] VSS[139] AA1
R22 Vcc1_5_B[36] Vcc3_3[14] B16 1 1 1 H5 VSS[43] VSS[140] AA24
0.1U_0402_16V4Z R23 B7 H24 AA25
2 Vcc1_5_B[37] Vcc3_3[15] VSS[44] VSS[141]
C353
C345
C354
R24 Vcc1_5_B[38] Vcc3_3[16] C10 H27 VSS[45] VSS[142] AA26
R25 Vcc1_5_B[39] Vcc3_3[17] D15 H28 VSS[46] VSS[143] AB4
2 2 2
R26 Vcc1_5_B[40] Vcc3_3[18] F9 J1 VSS[47] VSS[144] AB6
+3VS T22 G11 J2 AB11
Vcc1_5_B[41] Vcc3_3[19] VSS[48] VSS[145]
T23 Vcc1_5_B[42] Vcc3_3[20] G12 J5 VSS[49] VSS[146] AB14
T26 Vcc1_5_B[43] Vcc3_3[21] G16 J24 VSS[50] VSS[147] AB16
T27 Vcc1_5_B[44] J25 VSS[51] VSS[148] AB19
1 T28 Vcc1_5_B[45] VccRTC W5 +RTCVCC J26 VSS[52] VSS[149] AB21
C356 U22 K24 AB24
Vcc1_5_B[46] VSS[53] VSS[150]
0.1U_0402_16V4Z
0.1U_0402_16V4Z
Del R186(0_0805_5%) U23 P7 K27 AB27
www.manuals.clan.su
0.1U_0402_16V4Z Vcc1_5_B[47] VccSus3_3[1] +3VALW VSS[54] VSS[151]
2
V22 Vcc1_5_B[48] 1 45mA 1 1 1 K28 VSS[55] VSS[152] AB28
C289
C292
and +1.5VS_DMIPLLR 11/14 V23 Vcc1_5_B[49] VccSus3_3[2] A24 C332 C347 L13 VSS[56] VSS[153] AC2
W22 Vcc1_5_B[50] VccSus3_3[3] C24 L15 VSS[57] VSS[154] AC5
W23 D19 0.1U_0402_16V4Z 0.1U_0402_16V4Z L24 AC9
Vcc1_5_B[51] VccSus3_3[4] 2 2 2 2 VSS[58] VSS[155]
Y22 Vcc1_5_B[52] VccSus3_3[5] D22 L25 VSS[59] VSS[156] AC11
Place closely pin AG28 within 100mlis. Y23 Vcc1_5_B[53] VccSus3_3[6] G19 L26 VSS[60] VSS[157] AD1
M3 VSS[61] VSS[158] AD3
+1.5VS +1.5VS_DMIPLL
B27 Vcc3_3[1] VccSus3_3[7] K3 +3VALW M4 VSS[62] VSS[159] AD4
50mA R189 K4 1 1 M5 AD7
VccSus3_3[8] VSS[63] VSS[160]
10U_0805_10V4Z
0.01U_0402_25V7K
1 2 +1.5VS_DMIPLL AG28 K5 C333 C339 M12 AD8

VccDMIPLL VccSus3_3[9] VSS[64] VSS[161]
VccSus3_3[10] K6 M13 VSS[65] VSS[162] AD11
0.5_0805_1% 1 1 AB7 L1 0.1U_0402_16V4Z 0.1U_0402_16V4Z M14 AD15
+1.5VS Vcc1_5_A[1] VccSus3_3[11] 2 2 VSS[66] VSS[163]
C272
0.64A AC6 Vcc1_5_A[2] VccSus3_3[12] L2 M15 VSS[67] VSS[164] AD19

C271
AC7 Vcc1_5_A[3] VccSus3_3[13] L3 M16 VSS[68] VSS[165] AD23

1 AD6 Vcc1_5_A[4] VccSus3_3[14] L6 M17 VSS[69] VSS[166] AE2
2 2 C282 AE6 Vcc1_5_A[5] VccSus3_3[15] L7 M24 VSS[70] VSS[167] AE4
AF5 Vcc1_5_A[6] VccSus3_3[16] M6 M27 VSS[71] VSS[168] AE8
B 0.1U_0402_16V4Z AF6 M7 M28 AE11 B
2 Vcc1_5_A[7] VccSus3_3[17] VSS[72] VSS[169]
AG5 Vcc1_5_A[8] VccSus3_3[18] N7 N1 VSS[73] VSS[170] AE13
AH5 Vcc1_5_A[9] N2 VSS[74] VSS[171] AE18
Connected +1.5VS directly Vcc1_5_A[19] AB17 +1.5VS N5 VSS[75] VSS[172] AE21
when disable SATA. +1.5VS Place closely pin AG5. AD2 VccSATAPLL Vcc1_5_A[20] AC17 N6 VSS[76] VSS[173] AE24
N11 VSS[77] VSS[174] AE25
+3VS AH11 Vcc3_3[2] Vcc1_5_A[21] T7 N12 VSS[78] VSS[175] AF2
0.1U_0402_16V4Z
Vcc1_5_A[22] F17 N13 VSS[79] VSS[176] AF4

1 +1.5VS AB10 Vcc1_5_A[10] Vcc1_5_A[23] G17 N14 VSS[80] VSS[177] AF8
AB9 Vcc1_5_A[11] N15 VSS[81] VSS[178] AF11
C263
1 AC10 Vcc1_5_A[12] Vcc1_5_A[24] AB8 1 2 N16 VSS[82] VSS[179] AF27

C269 AD10 AC8 N17 AF28
2 Vcc1_5_A[13] Vcc1_5_A[25] C284 0.1U_0402_16V4Z VSS[83] VSS[180]
AE10 Vcc1_5_A[14] N18 VSS[84] VSS[181] AG1
1U_0603_10V4Z AF10 K7 ICH_K7 PAD T1117mA N24 AG3
2 Vcc1_5_A[15] VccSus1_05[1] VSS[85] VSS[182]
AF9 Vcc1_5_A[16] N25 VSS[86] VSS[183] AG7
AG9 C28 ICH_C28 PAD T3 N26 AG11
Vcc1_5_A[17] VccSus1_05[2] ICH_G20 VSS[87] VSS[184]
AH9 Vcc1_5_A[18] VccSus1_05[3] G20 PAD T14 P3 VSS[88] VSS[185] AG14
P4 VSS[89] VSS[186] AG17
+3VALW Place closely pin AG9. E3 VccSus3_3[19] Vcc1_5_A[26] A1 +1.5VS P12 VSS[90] VSS[187] AG20
1 Vcc1_5_A[27] H6 P13 VSS[91] VSS[188] AG25
C340 10mA C1 H7 1 P14 AH1
+1.5VS VccUSBPLL Vcc1_5_A[28] VSS[92] VSS[189]
1 J6 C344 P15 AH3
0.1U_0402_16V4Z C350 ICH_AA2 Vcc1_5_A[29] VSS[93] VSS[190]
T2 PAD AA2 VccSus1_05/VccLAN1_05[1] Vcc1_5_A[30] J7 P16 VSS[94] VSS[191] AH7
2 ICH_Y7 0.1U_0402_16V4Z
T6 PAD Y7 VccSus1_05/VccLAN1_05[2] P17 VSS[95] VSS[192] AH12
0.1U_0402_16V4Z 2
P24 VSS[96] VSS[193] AH23
2
V5 VccSus3_3/VccLAN3_3[1] P27 VSS[97] VSS[194] AH27
V1 VccSus3_3/VccLAN3_3[2]
W2 ICH7_BGA652
VccSus3_3/VccLAN3_3[3]
+3VS W7 VccSus3_3/VccLAN3_3[4]
A ICH7_BGA652 A
1
C291
0.1U_0402_16V4Z
2

SCHEMATIC,MB A5141
5 4 3 2 1
A B C D E
Mini-Express Card for WLAN

+3VS_WLAN +1.5VS
0.1U_0402_16V4Z
1 1 1 1 1
C195 C98 C121 C118 C113
4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7U_0805_10V4Z 0.01U_0402_25V7K

CHANGE R62(0_1206) to J9(43x79)11/17
1 2 2 2 2 2 1
J9
change JMIN1 Conn foorprintt 01/13 JUMP_43X79
JMINI1 @
ICH_PCIE_WAKE# 2 1 +3VS_WLAN 1 1
(17) ICH_PCIE_WAKE# 2 1 2 2 +3VS
4 4 3 3
6 6 5 5 +1.5VS
(12) WLAN_CLKREQ# WLAN_CLKREQ# 8 7
8 7
10 10 9 9
(12) CLK_PCIE_WLAN# 12 12 11 11
14 13
(12) CLK_PCIE_WLAN
16
14
16
13
15 15 BT MODULE CONN
18 18 17 17 change +5VS to +3VS 11/14
20 19 WL_OFF#
20 19 WL_OFF# (25)
22 21 PLTRST#
22 21 PLTRST# (6,15,17,24,25,27)
(17) PCIE_PTX_C_IRX_N1 24 24 23 23
(17) PCIE_PTX_C_IRX_P1 26 26 25 25
+3VS
28 28 27 27 Del R83 R348 0_0402
30 29
32
30 29
31 11/14 24 PIN
(17) PCIE_ITX_C_PRX_N1 32 31
(17) PCIE_ITX_C_PRX_P1 34
36
34 33 33
35
ADD PMOS SOFT START 11/14
36 35 USB20_N4 (17)
38 38 37 37 USB20_P4 (17) del R253 11/17
+3VS_WLAN 40 40 39 39
1 2 42 41 1 2 WWAN_LED# 1
42 41 R105 0_0402_5%
44 44 43 43 MINI1_LED# (22)
0.1U_0402_16V4Z C222 46 45 change EC signal name form C357
46 45
48
50
48 47 47
49
(9~16mA) BT_OFF# to BT_ON# 11/14 2
0.1U_0402_16V4Z
2 50 49 BT@ 2
52 52 51 51 JMINI1 pin 55,56 change to R291
55 G3 G1 53
Mobile EC_TX,EC_RX from WLAN to WWAN 56 G4 G2 54 non-GND 01/20 (25) BT_ON# 2 1
and add R96 11/14 BELLW_800XX-1021

CONN@
10K_0402_5%
BT@
R87 0_0402_5%
EC_TX_P80_DATA 2 EC_TX_P80_DATA_R
CHANGE R65,R70(0_1206) to +3VS +3VS_BT
(25,27) EC_TX_P80_DATA 1 change C233 BOM structure 11/26 del Q21 11/14
(25,27) EC_RX_P80_CLK
EC_RX_P80_CLK 1 2 EC_TX_P80_CLK_R J10,J11(43x79) 11/17 Q20
R96 0_0402_5% +3VS_WWAN BT@AO3413_SOT23-3 BT@
C348
+3VS_WWAN +3VALW
D
+3VS 1 3 1 2 1
www.manuals.clan.su
@
NON3G@ @ + C233 0.1U_0402_16V4Z
Mini-Express Card for WWAN 150U_Y_6.3VM
G
1 2 1 2
2
R65 0_1206_5% R66 0_1206_5%
2
+3VS_BT
Close to WWAN CONN
JMINI2
(17) ICH_PCIE_WAKE# ICH_PCIE_WAKE# 1 2
1 2
3 3 4 4 JBT1
5 5 6 6 +1.5VS
(12) WWAN_CLKREQ# WWAN_CLKREQ# 7 8 +UIM_PWR 1
7 8 UIM_DATA 1
9 9 10 10 Del J10,J11 and add R65,R66 02/05 2 2
11 12 UIM_CLK (17) USB20_P6 USB20_P6 3 5
(12) CLK_PCIE_WWAN# 11 12 3 GND
13 14 UIM_RST (17) USB20_N6 USB20_N6 4 6
(12) CLK_PCIE_WWAN 13 14 4 GND
15 16 UIM_VPP
15 16
ACES 88266-04001
CONN@
17 17 18 18 add R90 11/25
19 20 WXMIT_OFF#
3 19 20 WXMIT_OFF# (25) 3
21 22 R90 1 2 0_0402_5% +3VALW
21 22 PLTRST# (6,15,17,24,25,27)
(17) PCIE_PTX_C_IRX_N4 23 24 NON3G@
23 24
(17) PCIE_PTX_C_IRX_P4 25 25 26 26 add R107,R110 02/22 add R292 11/20
27 28 R107 0_0402_5%
27 28
1
29 29 30 30 1 2 NON3G@ CLK_SMBCLK (11,12)
(17) PCIE_ITX_C_PRX_N4 31 31 32 32 1 2 NON3G@ CLK_SMBDATA (11,12)
R292
33 34 R110 0_0402_5% 10K_0402_5%
(17) PCIE_ITX_C_PRX_P4 33 34
change C226 BOM
35
37
35 36 36
38
USB20_N5 (17) add R102 12/18
USB20_P5 (17)
2
10U_0805_10V4Z 37 38 @
structure 02/06 +3VS_WWAN 39 39 40 40
1 2 41 42 WWAN_LED# (22) (25) WWAN_WAKEUP# 1 2 WWAN_WAKEUP_R#
C226 <BOM Structure> 41 42 MINI1_LED# R102 0_0402_5%
43 43 44 44 1 2
D7 WWAN_WAKEUP_R# R106 0_0402_5%
@ CM1293-04SO_SOT23-6
45
47
45 46 46
48
(9~16mA)
UIM_VPP UIM_DATA EC_TX_P80_DATA_R 47 48
1 CH1 Add R105,R106 02/03 ADD WWAN_WAKEUP# ON pin 45 11/17
CH4 4 EC_TX_P80_CLK_R
49 49 50 50
51 51 52 52
Del R93 R407(0_0402) change R66,R102 BOM structure(@) 03/04

G1
G2
G3
G3
2 5 +UIM_PWR
Vn Vp FOX_AS0B226-S99N-7F 11/18 24 PIN
53
54
55
56
CONN@
change +UIM_PWR_1 +3VS_WWAN
UIM_RST 3 6 UIM_CLK
CH2 CH3 to +UIM_PWR 11/14 0.1U_0402_16V4Z
JP5
Del D16(DAN217T146_SC59-3) 1
C149
1 1
C185
1
C186
UIM_VPP
4 GND VCC 1 +UIM_PWR
UIM_RST
Del R94,R408(0_0402) 11/14 0.1U_0402_16V4Z
C105
0.01U_0402_25V7K
5 VPP RST 2
UIM_DATA UIM_CLK 2 2 2 2
6 I/O CLK 3
7 10U_0805_10V4Z
DET
22P_0402_50V8J
1U_0603_10V4Z
0.1U_0402_16V4Z
1
22P_0402_50V8J
22P_0402_50V8J
1 1 1 1
1
10K_0402_5%
C14
C264
4 4
R25
C17
C18
C258
GND 8
@ 2
GND 9
@ @ 2 @ 2 2 2
2
+UIM_PWR
TAITW_PMPAT6-06GLBS7N14N0 CONN@ Security Classification Compal Secret Data Compal Electronics, Inc.
Reserve for SIM card does not meet rise time SCHEMATIC,MB A5141
and pull-up is needed. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
B
401690
A B C D E
A B C D E F G H
+VDDA change to +VDDA

1/22 change U26 BOM structure 01/21
1
R365
J8
10K_0402_5%
2 2 1 1
2
@ JUMP_43X39
1 2
C455 1U_0402_6.3V4Z +5VAMP
U26
1
R366 L21 1 2 0.1U_0402_16V4Z 60mil 1 (output = 300 mA)
+5VS IN
10K_0402_5% FBMA-L11-201209-221LMA30T_0805 5 +VDDA 4.75V
1 OUT 1
2
1
C457
1
C458 GND 40mil C459
2
C456
1 2 MONO_IN
Del L22 11/16 0.1U_0402_16V4Z
3 SHDN BYP 4 1 2
1U_0402_6.3V4Z 2 2 G9191-475T1U_SOT23-5
2.2U_0603_6.3V6K
1
C 1 2
C460 1 R368 Q29 R367
(25) BEEP# 2 1 2 2
1U_0402_6.3V4Z B 2SC2411KT146_SOT23-3 2.4K_0402_1%
560_0402_5% E
change C459 from 0.01uF/0402 to 4.7uF/0603
3
GND change to AGND
01/21
R369 01/21
C461 1
(17) SB_SPKR 1U_0402_6.3V4Z
2 1 2 change C459 from 4.7uF to 2.2uF 01/23
1
560_0402_5%
D25 @
R370 RB751V-40TE17_SOD323-2
change U26,C459 BOM structure 02/18
10K_0402_5% HD Audio Codec
2
change D25 BOM structure 11/20
+AVDD_HDA L23
20mil 0.1U_0402_16V4Z +3VS_DVDD 1 2
change L23,L24 from SM010004010 to SM010032020
L24 +3VS
0.1U_0402_16V4Z 40mil MBK1608121YZF_0603 02/18
+VDDA 1 2 1 1 1
MBK1608121YZF_0603 1 1 1 C463 C464 C465
C466 C467
C462 10U_0805_10V4Z
2 10U_0805_10V4Z 2 2 2 Del JP4 11/26 2
25
38
9
2 2 2 U27
0.1U_0402_16V4Z 0.1U_0402_16V4Z
DVDD
AVDD1
AVDD2
DVDD_IO
14 35 AMP_LEFT
NC LINE_OUT_L AMP_LEFT (21)
15 36 AMP_RIGHT
NC LINE_OUT_R AMP_RIGHT (21)
16 MIC2_L HP_OUT_L 39
17 41
change R441 from 0ohm/0603 to 33ohm/0402 01/21
MIC2_R HP_OUT_R
www.manuals.clan.su
23 LINE1_L NC 45
24 46 DMIC_CLK 1 2 change R441 from 33 ohm to 39 ohm 01/23

LINE1_R DMIC_CLK DMIC_CLK_R (13)
R441 39_0402_5%
18 CD_L NC 43
change R371 from 0 ohm to 22 ohm 12/31
20 CD_R NC 44 1 2 1 2 C470 @
R371 @ 22_0402_5% 22P_0402_50V8J For EMI change R371,C470 BOM structure(@) 01/23
19 CD_GND
BIT_CLK 6 HDA_BITCLK_AUDIO (16)
MIC1_L 1 2 MIC1_C_L 21
(21) MIC1_L MIC1_L
C471 4.7U_0805_6.3V6K
MIC1_R 1 2 MIC1_C_R 22 8 HDA_SDIN0_AUDIO 1 2 HDA_SDIN0 (16)
(21) MIC1_R MIC1_R SDATA_IN
C472 4.7U_0805_6.3V6K R372 33_0402_5%
MONO_IN 12 37
PCBEEP MONO_OUT
LINE1_VREFO 29 For ALC272

11 2.2U_0402_6.3VM
3 (16) HDA_RST_AUDIO# RESET# 3
31 C491 1 2
GPIO1 HP_RIGHT
(16) HDA_SYNC_AUDIO 10 SYNC 10mil 1 HP_RIGHT (21)
change R438 from 0ohm/0603 to 0ohm/0402 01/21 5
MIC1_VREFO_L 28 MIC1_VREFO_L
C490 HP_LEFT
(16) HDA_SDOUT_AUDIO SDATA_OUT HP_LEFT (21)
32 HP_RIGHT 2.2U_0402_6.3VM
DMIC_DATA MIC1_VREFO_R 2
(13) DMIC_DATA_R 1 2 2 GPIO0
R438 0_0402_5% 3 30
R376 2 GPIO3 MIC2_VREFO
(21) MIC_PLUG# 1 20K_0402_1% SENSE_A 13 SENSE A 10mil
R375 2 1 5.11K_0402_1% SENSE_B 34 27 CODEC_VREF
(21) HP_PLUG# SENSE B VREF
1 1
10U_0805_10V4Z
0.1U_0402_16V4Z
(25) EAPD 1 2 47 EAPD JDREF 40
C473
C474
R377 0_0402_5%
0805 CHANGE TO 0603
20K_0402_1%
DMIC_DATA 48 33 HP_LEFT
SPDIFO NC
1
2 2
1 10/5
R378
@ R383 C604 4 26
10K_0402_5% DVSS1 AVSS1
7 DVSS2 AVSS2 42
add R383 01/22 18P_0402_50V8J 2 1
2
@ 2 ALC272-GR_LQFP48_9X9 R380 0_0603_5%
Sense Pin Impedance Codec Signals
2
DEL R383 R382 R384

39.2K PORT-A (PIN 39, 41) DGND AGND 2 1
R379 0_0603_5% GNDA & GND 11/16
20K PORT-B (PIN 21, 22)
SENSE A change C604 Bom structure(@) 01/23 Change to SA00002CI10 ALC272-VA2-GR 2 1
R381 0_0603_5%
10K PORT-C (PIN 23, 24) 20081111
5.1K PORT-D (PIN 35, 36)

GND GNDA
4
Change to SA00002CI10 to SA00002CI20 4
39.2K PORT-E (PIN 14, 15)
S IC ALC272X-GR LQFP 48P CODEC 12/10
20K PORT-F (PIN 16, 17)
SENSE B
10K PORT-G (PIN 43, 44)
5.1K PORT-H (PIN 45, 46) Issued Date 2006/12/25 Deciphered Date 2007/8/18 Title
SCHEMATIC,MB A5141
B B
401690
A B C D E F G H
A B C D E
add J12 12/04 Int. Speaker Conn.

+5VAMP_J change +5VAMP to +5VS 12/02 CONN@
20mil
J12 ACES 88266-04001
2 1 SPKL+ SPK_L+ 4 6
+5VALW 2 1 +5VAMP_J
1 1 SPKL- SPK_L- 3
4 GND
3 GND 5 Left
@ JUMP_43X39 SPKR+ SPK_R+ 2
C384 C385 SPKR- SPK_R- 2
1
10U_0805_10V4Z 0.1U_0402_16V4Z 1 Right
2 2
JP20
change JP20 Conn and pin design 11/26
+5VS change to +5VALW 12/11
1
+5VAMP_J 1
1
16
15
del R388,R387,R386,R385,D10,D13 12/11
6
U13 @ R315 @ R316
100K_0402_5% 100K_0402_5%
VDD
PVDD1
PVDD2
2
change JP20 Conn 01/16
C392 1 2 0.47U_0603_10V7K 7 2 GAIN0
RIN+ GAIN0
3 GAIN1
R94 GAIN1
SWAP JP20 01/20
1
C394 1 2 1 2 AMP_C_RIGHT 17
(20) AMP_RIGHT RIN- SPKR+ R318 R319
ROUT+ 18
0.47U_0603_10V7K 0_0402_5% 100K_0402_5% 100K_0402_5%
14 SPKR-
2
C395 1 ROUT-
2 0.47U_0603_10V7K 9 LIN+
4 SPKL+
R83 LOUT+
C397 1 2 1 2 AMP_C_LEFT 5
(20) AMP_LEFT LIN- SPKL-
LOUT- 8
0.47U_0603_10V7K 0_0402_5%
20081029 Update to 6dB
Add R94,R87 Vender suggesttion
11/16 NC 12
EC_MUTE# BYPASS 10 Keep 10 mil width

(25) EC_MUTE# 19 SHUTDOWN Analog ground change to digital ground
2
08/11/16
GND5
GND1
GND2
GND3
GND4
2 C398 2
0.47U_0603_10V7K
1
21
20
13
11
1 TPA6017A2_TSSOP20
C485
2 2
C486 LINE Out/Headphone Out
330P_0402_50V7K 330P_0402_50V7K
1 1
20mil JHP1
1
(20) HP_LEFT HP_LEFT 1 2 HPOUT_L_1 1 2 HPOUT_L_2 2
R374 56.2_0402_1% L26 FBM-11-160808-700T_0603 6
www.manuals.clan.su
(20) HP_RIGHT HP_RIGHT 1 2 HPOUT_R_1 1 2 HPOUT_R_2 3
R373 56.2_0402_1% L25 FBM-11-160808-700T_0603
4
Chenge to 56.2 ohm for DA-HP FSOV
HP_PLUG# 5
20081104 (20) HP_PLUG#
7 SHLD1
8 SHLD2
FOX_JAS7331-K30H9-7F
11/16 CONN@
MIC1_VREFO_L MIC1_VREFO_L
3 3
2
D26 D27
RB751V-40TE17_SOD323-2
RB751V-40TE17_SOD323-2
1 1
1 1
R403
4.7K_0402_5%
R402
4.7K_0402_5%
MIC JACK
2
JMIC1
1
1 2 1 2 FBM-11-160808-700T_0603 MIC2_L_1 2
(20) MIC1_L
R405 1K_0603_1% L28 6
1 2 1 2 FBM-11-160808-700T_0603 MIC2_R_1 3
(20) MIC1_R
R404 1K_0603_1% L27
4
1 1 MIC_PLUG# 5
(20) MIC_PLUG#
C488 C489
220P_0402_50V8J 220P_0402_50V8J 7 SHLD1
2 2
8 SHLD2
FOX_JAS7331-K30H9-7F
CONN@
(HDA Jack)
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E
A B C D E F G H
1 1
To cardreader/B Conn.
Move SATA HDD Conn to small board 11/21 KSO1
KSI1 WL_BTN#
KSI5 3G_BTN#
+3VS_READER change to +3VALW 12/15

SWAP JP7 pin define 12/03
add net name BATT_AMB_LED#
BATT_GRN_LED# 12/15
2
SATA&CARDREADER&USB Conn 2
JP7
1 1 2 2 +3VS
(16) SATA_ITX_C_DRX_N0 SATA_ITX_C_DRX_N0 3 4 +3VALW
3 4
swap(cable ) (16) SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_P0 5
7
5 6 6
8
7 8 +5VS
(16) SATA_DTX_C_IRX_N0 SATA_DTX_C_IRX_N0 9 10
9 10 BATT_AMB_LED_1# (25)
(16) SATA_DTX_C_IRX_P0 SATA_DTX_C_IRX_P0 11 12 +USB_VCCC
11 12
13
15
13 14 14
16
add J15 J16 12/08
(17) USB20_N2 15 16 BATT_GRN_LED_1# (25)
17 18
www.manuals.clan.su
(17) USB20_P2 17 18
19 20 KSI5
19 20 KSI5 (25,27)
(17) USB20_N3 21 22 KSI1
21 22 KSI1 (25,27)
KSO1
(17) USB20_P3 23
25
23 24 24
26 WWAN_LED#
KSO1 (25,26,27) del J15,J16,C21 12/15
25 26 WWAN_LED# (19)
(17) USB20_N7 27 27 28 28 MINI1_LED# (19)
cardreader (17) USB20_P7 29 29 30 30 5IN1_LED# (26)
31 GND1
3 32 GND2 3
ACES_88242-3001
add C11,C21,C26,C27 for keypart 12/08
CONN@
add C28 for keypart 01/14

del C11,C28,C26 01/21
del C26 02/03
ADD SATA&CARDREADER&USB Conn(JP7) 11/26
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E F G H
5 4 3 2 1
D D
Move Card Reader to small board 11/21

C C
B
www.manuals.clan.su B
A A

SCHEMATIC,MB A5141
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B 401690 B
5 4 3 2 1
A B C D E
change R644 from 0603 to 0805 12/31 @ R651 1 2 0_0402_5% +3V_LAN +3V_LAN
AR8114A: remove L1,C881,C885,R643. C841=1uF
change R643 from 0603 to 0402 12/31 +1.8_VDD/LX
AR8132:remove R644,R645. C841=0.1uF
0.1U_0402_16V4Z
1
change C841 from 0603 to 0402 12/31 1 2 1
L10 8132@ 4.7UH_1008HC-472EJFS-A_5%_1008
C837
add R651 O_0402 02/03 R627
4.7K_0402_1%
1
2
change C841 from 0402 1U to 0603 1U
2
R643 8132@ R628
02/03 0_0402_5% U12 4.7K_0402_1%
+AVDD_CEN 1 2 +2.5V_VDDH/VDD17 1 2 +2.5V_VDDH 1 8
R646 8114@ 0_0603_5% A0 VCC
1 1 2 7
2
A1 WP TWSI_SCL
4 C855 C881
3
4
A2 SCL 6
5 TWSI_SDA
Place Close to Chip 4
10U_0805_10V4Z 0.1U_0402_16V4Z U14 GND SDA LAN_MDI0+ R629 49.9_0402_1%
1 2
8132@ 2 2 8132@ 8132@ AT24C02BN-SH-T_SO8 LAN_MDI0- R630 49.9_0402_1%
AR8132M-AL1E QFN 48P E-LAN CTRL 1 2 1
@ LAN_MDI1+ R631 1 2 49.9_0402_1%
change 8132 P/N to SA000033N00 12/19 LAN_MDI1- R632 1 2 49.9_0402_1% 1 C838
0.1U_0402_16V4Z
U14 8114@ C839 2
Chang C855 form 4.7U to 10U 2
0.1U_0402_16V4Z
2 1 +1.8_VDD/LX 1 29 TWSI_SCL
11/16 vendor suggest C840 8114@ 1U_0603_10V4Z VDD18O TWSI_CLK TWSI_SDA
TWSI_DATA 30
+3V_LAN 2 VDD33
47 LAN_ACTIVITY#
C841 2 +2.5V_VDDH/VDD17 LED_ACTn LAN_SK_LAN_LINK#
1 1U_0603_10V4Z 6 VDDHO LED_10_100n 48
CTR12
del C843,C844 12/02 5 CTR12 LED_DUPLEXn 27
3 13 LAN_MDI0+ ADD C160 01/13 Layout Notice : Place as close

(6,15,17,19,25,27) PLTRST# PERSTn TRXP0 J7
4 14 LAN_MDI0-
(25) LAN_WAKE# WAKEn TRXN0 LAN_MDI1+
chip as possible.
TRXP1 17 +3VALW 2 2 1 1 +3V_LAN
+3V_LAN 1 2 2 1 VBG1P18V 7 18 LAN_MDI1-
VBG1P18V TRXN1
2.2U_0402_6.3VM
R633 4.7K_0402_5% 8114@C842
8114@ C842 1000P_0402_50V7K @ JUMP_43X39
41 11 AVDDVCO1 1 1
change C847 from 0.1u to 1u 12/02
(12) CLK_PCIE_LAN REFCLKP AVDDL_REG
42 AVDDVCO2 Chang C846 form 4.7U to 10U C160
AVDDL/AVDDL_REG C846
(12) CLK_PCIE_LAN# 40 REFCLKN 11/16 vendor suggest
A
t
h
e
r
o
s
10U_0805_10V4Z +3V_LAN
2 2 close to pin2
0.1U_0402_16V4Z
(17) PCIE_ITX_C_PRX_P3 43 RX_P
28 +1.2_DVDDL Chang C160 from 0603 to 0402
DVDDL0
(17) PCIE_ITX_C_PRX_N3 44 RX_N DVDDL1 32 01/20
DVDDL2 45 1 1 1
(17) PCIE_PTX_C_IRX_P3 2 1 PCIE_PTX_IRX_P3 38 AR8114A 10/100 LAN 46 C847
TX_P DVDDL3
C849
C845 0.1U_0402_16V7K close to pin2 C848
(17) PCIE_PTX_C_IRX_N3 2 1 PCIE_PTX_IRX_N3 37 8 +1.2_AVDDL 1U_0402_6.3V4Z 0.1U_0402_16V4Z
3 C850 0.1U_0402_16V7K TX_N AVDDL0 2 2 2 3
AVDDL1 16
+3V_LAN
Place Close to Chip LAN_X1 AVDDL2 22
9 XTLO AVDDL3 36 change BJT form MMJT9435T1G
<BOM Structure> LAN_X2 10 39
XTLI AVDDL4 to MBT35200 11/16
Y5
31 15 +2.5V_VDDH 1
SMCLK AVDDH0
1
LAN_X1 1 2 LAN_X2 33 19 C854
SMDATA AVDDH1 R636 0.1U_0402_16V4Z
AVDDH2 25
10K_0402_1% 8114@
C852 25MHZ_20P C853 8114@ 2
NC_0 20
2 1 12 21 +1.2_AVDDL
2
RBIAS NC_1
15P_0402_50V8J
15P_0402_50V8J
R635 2.37K_0402_1% 34 23 8132@ L29 8114@

TESTMODE NC_2
4
24 +2.5V_VDDH 1 2 1 2 BLM18PG121SN1D_0603 +1.2_DVDDL
NC_3
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26 0_0402_5% R63 Q58
NC_4 MBT35200MT1G_TSOP6
49 GND NC_5 35 change L29,L30 from 0805 to 0603 12/31
CTR12 3 8114@
AR8114-AL1E_QFN48_6X6 1 del R637 R638 12/31

change C852,C853,Y5 BOM structure 12/15
1
2
5
6
C880 AVDDVCO1
add C55 on page 24 12/15 close to pin5 0.1U_0402_16V4Z 1 1
T1 2 8132@ +1.2_AVDDL C856
del C55 12/16 1 1 1000P_0402_50V7K C857
LAN_MDI1+ 1 16 RJ45_MIDI1+ C858 C859 8114@ 1U_0603_10V4Z
LAN_MDI1- RD+ RX+ RJ45_MIDI1- 10U_0805_10V4Z 0.1U_0402_16V4Z 2 8114@ 2
change C852,C853 from 27p to 15p 01/23 2 RD- RX- 15
+AVDD_CEN 3 14 RJ45_CT0 R640 75_0402_5% 8114@ 8114@
CT CT 2 2
1 1 4 NC NC 13 1 2
C861 5 12 1 2 CHECK 01/13
C860 0.1U_0402_16V4Z NC NC RJ45_CT1 R639 75_0402_5%
6 CT CT 11
0.1U_0402_16V4Z LAN_MDI0+ 7 10 RJ45_MIDI0+ 1 L30 8114@
2 2 LAN_MDI0- TD+ TX+ RJ45_MIDI0- C862 L30 C856 AVDDVCO2
8 TD- TX- 9 1 2
1000P_1206_2KV7K 0_0603_5% 0.1U_0402_16V4Z 1
2 BLM18PG121SN1D_0603 2
350uH_NS0013LF 2 8132@ 8132@ C863
0.1U_0402_16V4Z
2
LAN_ACTIVITY# 2 1LAN_ACTIVITY#_R
2
R649 8114@ 511_0402_1% If overclocking, R638, L30 stuffed and R637 removed.
2
R650
Place Close to Pin 28324546 If not overclocking, R637, L30 suffed and R638 removed.
2
@ C868 0_0402_5% C866 C867 AR8132:L30=0ohm,C856=0.1uF. remove C857

100P_0402_50V8J 8114@ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
R648 1 JRJ45 +1.2_DVDDL
1
5.1K_0402_5% LAN_ACTIVITY# 1 2 12 Amber LED- 1 1 1 1

8114@ R647 8132@ 0_0402_5% C865 close to Pin46 change L30,C856,C857 BOM structure 12/22
1
2 1 LAN_ACTIVITY#_R 11 Amber LED+ 16 C882

+3V_LAN
R641 8132@ 511_0402_1% SHLD4 AR8114A: C865=0.1uF 0.1U_0402_16V4Z
8 PR4- 15 AR8132:C865=1uF 2 2 2 2
SHLD3
For EMI.
7 C865
@ PR4+ 0.1U_0402_16V4Z
2 1 RJ45_MIDI1- 6
change C873 from 0.1u to 1u 12/02
C864 470P_0402_50V7K PR2-
5 PR3-
Place Close to Pin816223639
4 PR3+ Place Close to Pin151925
RJ45_MIDI1+ 3 C871 C874 C876
PR2+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
2 RJ45_MIDI0- 2 +2.5V_VDDH +1.2_AVDDL
C869 PR1-
SHLD2 14 1 1 1 1 1 1 1 1
100P_0402_50V8J @ RJ45_MIDI0+ 1 C872 C873 C877
PR1+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z
LAN_SK_LAN_LINK# 1 1U_0402_6.3V4Z
10 Green LED- SHLD1 13
2 2 2 2 2 2 2 2
1 1
+3V_LAN 2 1 R642 9 Green LED+
C870
511_0402_1% 1U_0402_6.3V4Z close to pin8 C875
FOX_JM36113-P2221-7F close to pin5 0.1U_0402_16V4Z
For EMI. CONN@
@
2 1 change JRJ45 Conn 11/26
C878 470P_0402_50V7K
SCHEMATIC,MB A5141
A B C D E
change L13 from SM010004010 to SM010032020 +3VALW
02/18 +EC_AVCC
L13
1 1 1 1 1 1
0.1U_0402_16V4Z
C193
0.1U_0402_16V4Z
C114
0.1U_0402_16V4Z
C110
0.1U_0402_16V4Z
C119
1000P_0402_50V7K
C161
1000P_0402_50V7K
C109
+3VALW 1 2 +EC_AVCC
MBK1608121YZF_0603 2 1
C194
C196 2 2 2 2 2 2
@
111
125
0.1U_0402_16V4Z 1000P_0402_50V7K U8
22
33
96
67
9
1 ECAGND 2
2 1
R382 0_0603_5%
VCC
VCC
VCC
VCC
VCC
VCC
AVCC
change L14 to R382 11/17 del R204 11/21
1 21 INVT_PWM
(16) GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INVT_PWM (13)
2 23 BEEP#
(16) KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 BEEP# (20)
(17) SERIRQ 3 SERIRQ# FANPWM1/GPIO12 26
del R66(0_0402),R67(10K_0402) 4 27 ACOFF
(16) LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF (34)
LPC_AD3 5
11/20 (16) LPC_AD3 LAD3
LPC_AD2 7 PWM Output
(16) LPC_AD2 LAD2
LPC_AD1 8 63 BATT_TEMP
(16) LPC_AD1 LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP (32)
C107 LPC_AD0 BATT_OVP
(16) LPC_AD0 10 LAD0 LPC & MISC BATT_OVP/AD1/GPIO39 64 BATT_OVP (34)
2 1 2 1 ADP_I/AD2/GPIO3A 65 ADP_I (34)
R69 @ 10_0402_5% 12 AD Input 66 BRD_ID
@ 22P_0402_50V8J
(12) CLK_PCI_LPC
13
PCICLK AD3/GPIO3B
75
change R120 and R126 to PVT ID 01/14
(6,15,17,19,24,27) PLTRST# PCIRST#/GPIO05 AD4/GPIO42
1 2 EC_RST# 37 76
+3VALW ECRST# SELIO2#/AD5/GPIO43
R74 47K_0402_5% EC_SCI# 20
2
(17) EC_SCI#
38
SCI#/GPIO0E change R120 and R126 BOM structure 03/04
(22) BATT_GRN_LED_1# CLKRUN#/GPIO1D
C120 68
DAC_BRIG/DA0/GPIO3C EN_DFAN1
ADD BATT_GRN_LED_1# and EN_DFAN1/DA1/GPIO3D 70 EN_DFAN1 (28)
0.1U_0402_16V4Z BATT_AMP_LED_1# 02/03 KSI0 DA Output 71 IREF
1 IREF/DA2/GPIO3E IREF (34)
55 KSI0/GPIO30 DA3/GPIO3F 72 CALIBRATE# (34)
KSI1 56 DEL R90 and WWAN_LED_R# on pin 85 11/17
KSI2 KSI1/GPIO31 +3VALW
Move R204 from P16 to P25 57 KSI2/GPIO32
KSI3 58 83
11/18 KSI3/GPIO33 PSCLK1/GPIO4A EC_MUTE# (21)
KSI4 59 84 USB_ON# Ra
KSI4/GPIO34 PSDAT1/GPIO4B USB_ON# (28)
2
KSI5 60 85 R120
KSI5/GPIO35 PSCLK2/GPIO4C BATT_AMB_LED_1# (22)
KSI6 61 PS2 Interface 86 BT_LED# (26) 100K_0402_5% R120 60@
KSO[0..15] KSI7 KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK
62 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E 87 TP_CLK (27) 100K_0402_5%
(22,26,27) KSO[0..15] KSO0 39 88 TP_DATA 80@
KSI[0..7] KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA (27)
KSO1 40
1
(22,26,27) KSI[0..7] KSO2 KSO1/GPIO21
41 KSO2/GPIO22
KSO3 42 97 change EC signal name form BRD_ID
KSO4 KSO3/GPIO23 SDICS#/GPXOA00 R126
43 98 BT_ON# (19)
KSO4/GPIO24 SDICLK/GPXOA01 BT_OFF# to BT_ON# 11/16
2
KSO5 18K_0402_1% R126
KSO6
44 KSO5/GPIO25 Int. K/B SDIDO/GPXOA02 99
LID_SW# R126
45 KSO6/GPIO26 Matrix SDIDI/GPXID0 109 LID_SW# (26) 0_0402_5%
KSO1 KSI1 KSI5 GPIO15 KSO7 46 SPI Device Interface 2 1 +3VALW 80@ 60@ 18K_0402_1%
KSO8 KSO7/GPIO27 47K_0402_5% R660 A0@
47 KSO8/GPIO28 add R660 pull up +3VALW 01/14
KSO9 48 119 FRD#SPI_SO Rb
1
KSO10 KSO9/GPIO29 SPIDI/RD# FWR#SPI_SI
WLAN_OFF# v v High 49 KSO10/GPIO2A SPIDO/WR# 120 DEL R79 ,R92 and change net name to
KSO11 50 SPI Flash ROM 126 SPI_CLK
KSO12 51
KSO11/GPIO2B SPICLK/GPIO58
128 FSEL#SPICS# WWAN_WAKEUP# 11/17
KSO13 KSO12/GPIO2C SPICS#
WXMIT_OFF# v v High 52
KSO14
KSO15
53
KSO13/GPIO2D
KSO14/GPIO2E
BOARD ID Table
WXMIT_OFF# 54 KSO15/GPIO2F CIR_RX/GPIO40 73 WWAN_WAKEUP# (19)
v v Low 81 KSO16/GPIO48 CIR_RLC_TX/GPIO41 74
ID BRD ID
Swap to WLAN 82 KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 89
BATT_GRN_LED#
FSTCHG (34) Ra Rb Vab
BATT_CHGI_LED#/GPIO52 90 BATT_GRN_LED# (26)
CAPS_LED# 0 R01 (EVT)
EC_SMB_CK1 77 GPIO
CAPS_LED#/GPIO53 91
92 BATT_AMB_LED#
CAPS_LED# (26) NC 0 0V
(32) EC_SMB_CK1 SCL1/GPIO44 BATT_LOW_LED#/GPIO54 BATT_AMB_LED# (26)
EC_SMB_DA1 PWR_LED# 1 R02 (DVT)
(32) EC_SMB_DA1
EC_SMB_CK2
78 SDA1/GPIO45 SUSP_LED#/GPIO55 93
SYSON
PWR_LED# (26) 100K 8.2K 0.25V
KSO1 (4) EC_SMB_CK2 79 SCL2/GPIO46 SM Bus SYSON/GPIO56 95 SYSON (29,35)
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EC_SMB_DA2 2 R03 (PVT)
(4) EC_SMB_DA2 80 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 121 VR_ON (37) 100K 18K 0.50V
KSI1 WL_BTN# AC_IN/GPIO59 127 ACIN (17,31) change R24 from 10k to 47K
R103 from 0 to 2.2K 12/22 3 R10A (MP) 100K NC 3.3V
KSI5 3G_BTN# PM_SLP_S3#
(17) PM_SLP_S3# 6 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 100 EC_RSMRST# (17)
PM_SLP_S5# 14 101 EC_LID_OUT# R24
(17) PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_LID_OUT# (17)
EC_SMI# 15 102 EC_ON RB751V-40TE17_SOD323-2 1 2 47K_0402_5% Move R24 from P17 to P25 11/18
(17) EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXO05 EC_ON (26)
16 103 D12 @
LID_SW#/GPIO0A EC_SWI#/GPXO06 ICH_POK_EC
17 SUSP#/GPIO0B ICH_PWROK/GPXO06 104 1 2 ICH_POK ICH_POK (6,17)
18 PBTN_OUT#/GPIO0C GPO BKOFF#/GPXO08 105 BKOFF# (13)
19 EC_PME#/GPIO0D GPIO WL_OFF#/GPXO09 106 WL_OFF# (19) 1 2 R103 1 2 +3VS change D12,R104 BOM structure 12/22
25 107 2.2K_0402_5% R104 10K_0402_5%
EC_THERM#/GPIO11 GPXO10 WXMIT_OFF# (19)
FAN_SPEED1 28 108 @
(28) FAN_SPEED1 FAN_SPEED1/FANFB1/GPIO14 GPXO11 D19
29 FANFB2/GPIO15
EC_TX_P80_DATA 30 change D12,R103,R104 ICH_POK 2 1
(19,27) EC_TX_P80_DATA EC_TX/GPIO16 VGATE (12,17,37)
EC_RX_P80_CLK 31 110 PM_SLP_S4# (17) BOM
(19,27) EC_RX_P80_CLK EC_RX/GPIO17 PM_SLP_S4#/GPXID1 structure 11/16
32 112 RB751V-40TE17_SOD323-2
(26) ON/OFF# ON_OFF/GPIO18 ENBKL/GPXID2 GMCH_ENBKL (8)
(26) PWR_SUSP_LED# PWR_SUSP_LED# 34 114
PWR_LED#/GPIO19 GPXID3 EAPD (20)
NUM_LED# 36 GPI 115 EC_THERM#
(26) NUM_LED# NUMLED#/GPIO1A GPXID4 EC_THERM# (17)
116 SUSP#
GPXID5 SUSP# (29,34,35,36)
117 PBTN_OUT#
GPXID6 PBTN_OUT# (17) +3VALW
GPXID7 118 LAN_WAKE# (24)
XCLKI 122 U19
XCLK1
<BOM Structure>
XCLKO 123 124 SPI_CS# 1 8
XCLK0 V18R CS# VCC SPI_CLK_R
20mil 1 ENE +3VALW 3 WP# SCLK 6
AGND
+3VALW C116 7 5 SPI_SI

GND
GND
GND
GND
GND
4.7U_0603_6.3V6K suggesttion 4
HOLD# SI
2 SPI_SO
EC_SMB_CK1 GND SO
1 2
2
at C0
R122 2.2K_0402_5% KB926QFD3_LQFP128_14X14 MX25L512AMC-12G_SO8
revision
11
24
35
94
113
69
1 2 EC_SMB_DA1 @
R123 2.2K_0402_5%
ECAGND
1 2 KSO1
R75 47K_0402_5%
1 2 KSO2
change C116 form 1U to 4.7U 12/22 +3VALW
R78 47K_0402_5% change U8 from D2 to D3(SA00001J580) 03/04
8M SPI ROM
22P_0402_50V8J
Follow ENE AP sheet 1 change C117 BOM structure 12/24 1

22P_0402_50V8J
KB926D-AN1-100 1 C123 C122 20mils U10

C150 8 4
VCC VSS
1
0.1U_0402_16V4Z
X1 2 2
3
IN
OUT
2 W
change R122,R123,R124,R125 del R76 12/14
+5VS
from 4.7K to 2.2K 01/23 7 HOLD
TP_CLK FSEL#SPICS# 2 SPI_CS#
NC
NC
1 2 C117 1 1 S
R127 4.7K_0402_5% R77 22_0402_5%
TP_DATA 1 2 2 1 SPI_CLK_R SPI_CLK 2 1 SPI_CLK_R 6
2
R128 4.7K_0402_5% 10P_0402_50V8J R88 22_0402_5% C

32.768K_1TJS125BJ4A421P <BOM Structure> FWR#SPI_SI 2 1 SPI_SI 5 2 SPI_SO 2 1 FRD#SPI_SO
R89 22_0402_5% D Q R80 22_0402_5%
change c150,c123 from 15p to 22p 11/23 R88,C117 close to EC SST25LF080A_SO8-200mil
+3VS
1 2 EC_SMB_CK2 BATT_OVP C182 1 2

change R77 , R89 , R80 form 0 ohm to 22 ohm 02/25
R124 2.2K_0402_5% 100P_0402_50V8J
1 2 EC_SMB_DA2 BATT_TEMP C179 1 2
R125 2.2K_0402_5% 100P_0402_50V8J
ACIN C115 1 2
100P_0402_50V8J Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A5141
ON/OFF switch
change J1,J3(43 x 79) to

change JP2 Conn 12/01
R186,R193(0_0805) 11/16
+3VS
TOP Side
To PWR/B Conn. LED
1
@ +3VALW +3VS
R186 2 1
change JP2 Conn 11/25 R195
0_0805_5% Q45A
2
@ 10K_0402_5% 2N7002DW-T/R7_SOT363-6
2
Compal Footprint
2
@ R347 1 6
(22) 5IN1_LED#
R193 2 1
0_0805_5% 100K_0402_5% +3VALW +5VS +5VALW SATA_LED# MEDIA_LED#
(16) SATA_LED# 4 3 3 4
1
Bottom Side D14

ON/OFF#
JP2
Q45B
1 2
2 ON/OFF# (25) 1
5
ON/OFFBTN# 1 2N7002DW-T/R7_SOT363-6
1 2 2 +3VS
3 51ON# 3
51ON# (31) 3
ON/OFFBTN# 4
DAN202U_SC70 PWR_LED# 4
(25) PWR_LED# 5 5 Q3
(25) PWR_SUSP_LED# PWR_SUSP_LED# 6 6
1
LID_SW# 7 2N7002W-T/R7_SOT323-3
2 (25) LID_SW# 7
C4 D1 @ 8 8
D
9 SDIO_LED# 3 1 MEDIA_LED#
GND (27) SDIO_LED#
1000P_0402_50V7K RLZ20A_LL34 10
1 GND
change Q3 from 2N70002_SOT23 to
2
ACES_85201-08051 SDIO@
G
2
change D1 BOM structure 12/22 CONN@ 2N7002W-T/R7_SOT323-3 11/16
+5VALW change +3VS
to +3VALW 12/17
1
www.manuals.clan.su
EC_ON 2 Q1 LED2 60@
(25) EC_ON R284
G 2N7002W-T/R7_SOT323-3
change JP2 from 6 pin to 8 pin 11/21
2
S +3VALW 1 2 4 3 BATT_AMB_LED# BATT_AMB_LED# (25)

3
R3 300_0402_5%
10K_0402_5% change Q1 form 2N70002_SOT23 to +3VALW R286 1 2 2 YG 1 BATT_GRN_LED# BATT_GRN_LED# (25)

Change PWR_LED and PWR_SUSP_LED 68_0402_5%
1
2N7002W-T/R7_SOT323-3 11/17
Net name 01/13 follow JAWD0 HT-297DQ-GQ_AMB-YG
20080623
LED2
change R284 from 150 ohm to 300 ohm
change R518 from 300 to 422 ohm 02/06 R286 from 120 ohm to 100 ohm 01/23
Bluetooth LED MEDIA_LED NUM_LED CAPS_LED HT-297DQ-GQ_AMB-YG

+5VS +5VS +5VS +5VS 80@
(GREEN) (GREEN) (GREEN)
DEL LID Switch 11/21
change LED2 BOM
follow JAWD0
20080623
structure 02/18
2
2
LED3 LED5 LED6
LED4
HT-191NBQA_BLUE_0603
BT@
change R518 from 422 to 220 03/04 (BLUE) HT-191UYG-DT YEL/GRN_0603 HT-191UYG-DT YEL/GRN_0603 HT-191UYG-DT YEL/GRN_0603
1
1
KSO1 change R1 from 200 to 470 03/04
HARVATEK
MEDIA_LED_R#
CAPS_LED_R#
BT_LED_R#
NUM_LED_R#
change R286 from 100 to 68 03/04
KSI2 BT_BTN# change R2,R4 from 200 to 220 03/04
R518 R1 R2 R4
change R1 from 470 to 390 03/06
1 2 2 1 MEDIA_LED# 2 1 2 1
BT_LED# (25) NUM_LED# (25) CAPS_LED# (25)
BT@ 220_0603_5% 220_0402_5% 220_0402_5%
390_0402_5%
Change SW4 P/N to SN111005800 01/13 KSI2
Bluetooth Button KSO1 R2,R4,R518 close to EC 12/03 R1 close to Q3 12/03

3
SW4
2 1 D33
PJSOT05C_SOT23-3
(22,25,27) KSO1 KSO1 KSI2
KSI2 (25,27)
change R1,R2,R4 from 300 to 200 ohm 02/06
1
4 3
SKRBAAE010_4P change D33 P/N from SCA00000A00
to SCA00000200 02/27 Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
BT@
SCHEMATIC,MB A5141
B B
401690
5 4 3 2 1
SWAP JP12 11/26 To TP/B Conn. SWAP JP11 01/13

CONN@
D
ACES_87151-1207G D
CONN@ 12 14
ACES_85201-24051 LEFT_BTN# 12 G14
11 11 G13 13
KSI[0..7] 10
KSI[0..7] (22,25,26) 10
26 GND2 +5VS 9 9
KSO[0..15] 25 8
KSO[0..15] (22,25,26) GND1 8
TP_DATA 7
(25) TP_DATA 7
6 6
TP_CLK 5
(25) TP_CLK 5
KSI0 24 1 1 4
KSI1 24 C157 RIGHT_BTN# 4
23 23 3 3
KSI0 C144 1 2 100P_0402_50V8J KSO4 C145 1 2 100P_0402_50V8J KSI2 22 C158 2
KSO0 22 100P_0402_50V8J 2
21 21 100P_0402_50V8J 1 1
KSI1 C133 1 100P_0402_50V8J KSO5 C142 1 100P_0402_50V8J KSO1 2 2
2 2 20 20
KSO2 19 JP11
KSI2 C140 1 100P_0402_50V8J KSO6 C148 1 100P_0402_50V8J KSI3 19
2 2 18 18
KSO3 17
KSI3 C141 1 100P_0402_50V8J KSO7 C146 1 100P_0402_50V8J KSO4 17 LEFT_BTN# TP_CLK
2 2 16 16
KSO5 15
KSI4 C137 1 100P_0402_50V8J KSO8 C147 1 100P_0402_50V8J KSO6 15 RIGHT_BTN# TP_DATA
2 2 14 14
KSO7 13 13
3
KSI5 C138 1 2 100P_0402_50V8J KSO9 C136 1 2 100P_0402_50V8J KSO8 12
KSI4 12 D9
11 11
KSI6 C135 1 2 100P_0402_50V8J KSO10 C129 1 2 100P_0402_50V8J KSO9 10 D18 +5VS PJSOT05C_SOT23-3
KSI5 10 PJSOT05C_SOT23-3
9 9
KSI7 C134 1 2 100P_0402_50V8J KSO11 C128 1 2 100P_0402_50V8J KSI6 8
KSO10 8 C156
7
1
KSO0 C139 1 100P_0402_50V8J KSO12 C126 1 100P_0402_50V8J KSO11 7
2 2 6 6
KSI7 5 0.1U_0402_16V4Z
C KSO1 C143 1 100P_0402_50V8J KSO13 C127 1 100P_0402_50V8J KSO12 5 C
2 2 4 4
KSO13 3
KSO2 C131 1 100P_0402_50V8J KSO14 C124 1 100P_0402_50V8J KSO14 3
2 2 2 2
KSO15 1
KSO3 C132 1 100P_0402_50V8J KSO15 C125 1 100P_0402_50V8J 1
2 2
JP12 SW2 SW3
SMT1-05-A_4P SMT1-05-A_4P
LEFT_BTN# 3 1 RIGHT_BTN# 3 1
INT_KBD Conn. 4 2 4 2
5
6
5
6
www.manuals.clan.su To SDIO Conn. change D9,D18 P/N from SCA00000A00
to SCA00000200 02/27
change D18 P/N from SC10T24C010

JP6 to SCA00000A00 and BOM structure 12/22
+3VS 1 1
(26) SDIO_LED# SDIO_LED# 2 change D9 P/N from SC10T24C010
PLTRST# 2
3 3 to SCA00000A00 and BOM structure 12/22
(6,15,17,19,24,25) PLTRST# 4
B PCIE_PTX_C_IRX_P2 4 B
(17) PCIE_PTX_C_IRX_P2 5 5
(17) PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_N2 6 6
7 7
PCIE_ITX_C_PRX_P2 8
(17) PCIE_ITX_C_PRX_P2 8
PCIE_ITX_C_PRX_N2 9
(17) PCIE_ITX_C_PRX_N2 9
10 10
CLK_PCIE_CARD 11
(12) CLK_PCIE_CARD 11
CLK_PCIE_CARD# 12
(12) CLK_PCIE_CARD# 12
13
14
GND1
GND2
EC DEBUG PORT
ACES_87213-1200G JP14
CONN@ 1
+3VALW 1
EC_TX_P80_DATA 2
(19,25) EC_TX_P80_DATA 2
EC_RX_P80_CLK 3
(19,25) EC_RX_P80_CLK 3
swap JP6 pin define 12/08 4 4
ACES_85205-0400
CONN@
swap CLK_PCIE_CARD and CLK_PCIE_CARD# 12/16
A A

SCHEMATIC,MB A5141
B B
401690
5 4 3 2 1
A B C D E
change U2 from SA000039E00 to SA000033H00 02/27 USB CONN. 1

1 1
+USB_VCCA
+5VALW
+USB_VCCA
W=80mils
1
1
+USB_VCCA C231 + C15
U2 150U_B2_6.3VM
C34 1 8 <BOM Structure> 330P_0402_50V7K
0.1U_0402_16V4Z GND VOUT 2 2
2 VIN VOUT 7
2 1 3 6 JUSB1
VIN VOUT
4 EN FLG 5 USB_OC#0 (17) 1 VCC
2
USB20_N0 2
(17) USB20_N0 D-
R130 APL3510BKI-TRG_SO8 USB20_P0 3
(17) USB20_P0 D+
100K_0402_5% 4 GND
1
C16 5
1
USB_ON# @ 1000P_0402_50V7K GND1
(25) USB_ON# 6 GND2
7 GND3
2
8 GND4
SUYIN_020173MR004S10DZL
CONN@
2 2
+5VS
www.manuals.clan.su
FAN1 Conn
+5VS
Change U3 to SA00002XA00 02/25 C10 10U_0805_10V4Z
1 2 3
U7 Change to SA000039E00 02/25
2 D5 @
U3 DAN217_SC59
1 EN GND 8
2 VIN GND 7
+VCC_FAN1 3 VOUT GND 6
1
EN_DFAN1 1 2 VSET 4 VSET 2 C469

(25) EN_DFAN1
R46 330_0402_5% GND 5 1
APL5607KI-TRG_SO8 4.7U_0603_6.3V6K +5VALW +USB_VCCC

1
C427 U7
3 0.01U_0402_25V7K C396 1 3
2 1 GND VOUT 8
2 VIN VOUT 7
2 4.7U_0603_6.3V6K 3 VIN VOUT 6
1 4 EN FLG 5 USB_OC#2_3 (17)
+3VS C399
1000P_0402_50V7K C2 APL3510BKI-TRG_SO8
1 2 0.1U_0402_16V4Z
1
2
1
R305 C19
10K_0402_5% @ 1000P_0402_50V7K
40mil USB_ON#
JP13 2
2
+VCC_FAN1 1 1
(25) FAN_SPEED1 2 2
3 3
1
C393 4
1000P_0402_50V7K GND
5 GND
2
ACES_85204-0300N
CONN@
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E
A B C D E
1 1
+5VALW TO +5VS +3VALW TO +3VS

+5VALW +5VS +3VALW +3VS
SI4800BDY-T1-E3_SO8 Q6 SI4800BDY-T1-E3_SO8 Q12

8 1 8 1
7 2 7 2 +5VALW
2
6 3 1 1 6 3 1 1
1 1 5 C74 C76 R50 1 1 5 C201 C202 R179
2
C97 C96 C215 C214
10U_0805_10V4Z 470_0603_5% 10U_0805_10V4Z 470_0603_5% R302
4
4
10U_0805_10V4Z 2 2
1U_0603_10V4Z 10U_0805_10V4Z 2 2
1U_0603_10V4Z 100K_0402_5%
3 1
2 2
10U_0805_10V4Z 2 2
10U_0805_10V4Z
2 2
1
3
Q17B
+VSB 1 2 5VS_GATE Q8B 2N7002DW-T/R7_SOT363-6 5 SUSP
R68 2N7002DW-T/R7_SOT363-6 5 SUSP +VSB 1 2 SYSON#
22K_0402_5% 1 R185
4
6
C108 33K_0402_5% 1
4
6
C255
Q8A 0.1U_0603_25V7K
6
SUSP 2 Q17A 0.1U_0603_25V7K
2
2N7002DW-T/R7_SOT363-6 SUSP 2
2
2N7002DW-T/R7_SOT363-6 Q28A
1
SYSON 2
(25,35) SYSON
1
www.manuals.clan.su
2N7002DW-T/R7_SOT363-6
1
change R68 from 200K to 22K 12/10
change R185 from 200K to 33K 12/10
+5VALW CHANG TO VL
11/16
RTCVREF VL
2
+2.5VS R298 R297
3 100K_0402_5% 100K_0402_5% 3
@
1
SUSP
(36) SUSP
2
@ R169
3
470_0603_5%
del +1.5VS,+VCCP,+0.9VS,+1.8V Discharge Q28B

1
(25,34,35,36) SUSP# 5
pathR18,R280,R61,R279 Q2,Q24,Q7,Q23 11/17 2N7002DW-T/R7_SOT363-6
1
D Q15
4
2 SUSP
G
@ S 2N7002W-T/R7_SOT323-3
3
change Q2,Q15,Q24,Q7,Q23 form 2N70002_SOT23 to change R18,R169,R280,R61,R279

2N7002W-T/R7_SOT323-3 11/17 Q2,Q15,Q24,Q7,Q7,Q23 BOM structure 11/16
4 4

SCHEMATIC,MB A5141
B B
401690
A B C D E
H29
H
H_3P0 X 4P3N update Screw 12/04
@
1
del H11 H_3P0N 12/10
H18 H10
H H
H_3P1N H_3P3N change H18 from 3P2N to 3P1N 02/22
@ @
1
1
H3 H22 H16 H1 H28 H27 H14 H26 H17
H H H H H H H H H
change H17 from H_2P5 to H_2P5 X 4P4
@ @ @ @ @ @ @ @ @
del H31 01/16 H_2P5 X 4P4
1
1
H30 H19 H15 H20
add H32 12/17
H H H H
@ @ @ @ H_3P3
modify H15,H19,H20,H29,H30 12/17
1
update H15,H19,H20,H30 from 3P8 to 3P6

01/22
www.manuals.clan.su update H15,H19,H20,H30 from 3P6 to 3P3

02/22
FM1 FM2 FM3 FM4
@ @ @ @ FIDUCIAL_C40M80
1

SCHEMATIC,MB A5141
B B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 401690
A B C D
PR1
1M_0402_1%
1 2
VIN VIN
VS
1
1 1
VIN @PR2
@ PR2
10K_0402_5%
PR3
84.5K_0402_1%
PR5
8
PL1 PR4 PR102 22K_0402_5%
2
SMB3025500YA_2P 100K_0402_1% 10K_0402_5% PU1A 3 1 2
P
DC_IN_S1 PACIN +
1 2 1 2 2 1 1 0
(17,25) ACIN
1
- 2
1
G
PC5
SP02000GC00
1
LM358DT_SO8 PR6 1000P_0402_50V7K
4
PJP1 PD3 PC6 20K_0402_1%
2
1
1
6 4 PR7 RLZ4.3B_LL34 0.1U_0603_25V7K
2
GND 4 PC3 PC4 PC2 PC1 10K_0402_5%
5 GND 3 3
2 1000P_0402_50V7K 100P_0402_50V8J 100P_0402_50V8J 1000P_0402_50V7K
2
2
1 1
ACES 88266-04001 PR8

CONN@ 10K_0402_5%
1 2
RTCVREF
(34) PACIN
2 2
Vin Dectector
Min. Typ Max.
- PBJ1 + H-->L 16.976V 17.525V 17.728V
2 1 +RTCBATT L-->H 17.430V 17.901V 18.384V
+RTCBATT
ML1220T13RE
45@
www.manuals.clan.su VIN
+3VALWP 2
PJ2
2 1 1 +3VALW +1.5VSP 2
PJ3
2 1 1 +1.5VS
2
PC123 JUMP_43X118 PC130 JUMP_43X118
2
0.1U_0402_16V7K (4.69A,200mils ,Via NO.= 10) 0.1U_0402_16V7K (3.464A,160mils ,Via NO.=8)

PD4
1
RLS4148_LL34-2
PD5
RLS4148_LL34-2 PJ4 PJ5
1
+5VALWP 2 2 1 1 +5VALW +0.9VSP 2 2 1 1 +0.9VS

BATT+ 2 1
1
2
3 3

PR9 PR10 0.1U_0402_16V7K (5.58A,240mils ,Via NO.= 12) 0.1U_0402_16V7K (1A,40mils ,Via NO.=2)
68_1206_5% 68_1206_5%
1
PR11 PQ1
PJ6
2
200_0603_5% PJ7
CHGRTCP 1 2 N1 3 1 2 1 +1.8VP 2 1 +1.8V
VS +VSBP 2 1 +VSB 2 1
2
1
0.1U_0402_25V6 (120mA,40mils ,Via NO.= 2) 0.1U_0402_16V7K (4.6A,200mils ,Via NO.=10)

1
PR12 PC7
1
100K_0402_1% 0.22U_1206_25V7K PC8
0.1U_0603_25V7K
PJ9
2
PR13 TP0610K-T1-E3_SOT23-3 PJ8

2
22K_0402_1% 2 1 2 1
+1.05VSP 2 1 +VCCP +2.5VSP 2 1 +2.5VS
1 2
(26) 51ON#
2
0.1U_0402_16V7K (7.09A,300mils ,Via NO.=16) 0.1U_0402_16V7K (0.14A,40mils ,Via NO.=2)
1
RTCVREF
1
PR14
200_0603_5%
PR15 PR16 PU2
560_0603_5% 560_0603_5% 3.3V
2
1 2 1 2 3 2 N2
OUT IN
+CHGRTC
1
GND PC10
4
PC9 G920AT24U_SOT89-3 1U_0805_25V4Z 4
10U_0805_10V4Z 1
2

SCHEMATIC,MB A5141
Rev
Custom B
401690
A B C D
A B C D
PH1 under CPU botten side :

CPU thermal protection at 92 degree C
Recovery at 56 degree C
VL
VL
VL
VMB
2
PL2 PR17
PJP2
1
1 1
SMB3025500YA_2P 47K_0402_1%
1 1 BATT_S1 1 2 BATT+ PC11
MAINPWON (33)
2 PH1 0.1U_0603_25V7K PR18
1
2 EC_SMCA 100K_0603_1%_TSM1A104F4361RZ 47K_0402_1%
3 3
1
4 EC_SMDA 1 2
2
4 PC12 PC13 PR19
5 5
8
1000P_0402_50V7K 0.01U_0402_25V7K 7.32K_0402_1% PD6
2
1 2 3 RLS4148_LL34-2
P
+
O 1 2 1 2
6 TM_REF1 2 PQ2
GND1 -
G
7 PU3A DTC115EUA_SC70-3
GND2 LM393DG_SO8
4
OCTEK_tBTJ-0811050
3
2
17.4K_0402_1%
PR20 PR21
1
100_0402_1% 100_0402_1% PR23
1000P_0402_50V7K
PR22
PC14 100K_0402_1%
1
0.22U_0603_10V7K 2 1 VL
1
PR24
PC15
6.49K_0402_1%
2
2 1 +3VALWP
1
1
PR25
PR26 100K_0402_1%
1K_0402_1%
2
2
2 2
BATT_TEMP (25)
EC_SMB_CK1 (25) PH2 near main Battery CONN :

BAT. thermal protection at 92 degree C
EC_SMB_DA1 (25)
Recovery at 56 degree C
VL
www.manuals.clan.su
2
@ PR27
@PR27
VL 47K_0402_1%
@PR28
@ PR28
47K_0402_1%
1
1 2
1
PQ3 @PH2
@ PH2
100K_0603_1%_TH11-4H104FT VL
B+ 3 1 +VSBP
2
0.22U_1206_25V7K
0.1U_0603_25V7K
PR30
1
8
@ 13.7K_0402_1% @PD7
@ PD7
1
1
PC16
PC17
1 2 5 LL4148_LL34-2
P
PR29 +
O 7 2 1
100K_0402_1% @ @ TM_REF1 6
2
G
3 3
TP0610K-T1-E3_SOT23-3 PU3B
2
1
VL LM393DG_SO8
4
1 2 @ PC18
@PC18 @ PR32
@PR32
PR31 0.22U_0603_16V7K 15.4K_0402_1%
2
22K_0402_1%
2
2
PR33
100K_0402_1%
PR34
1
0_0402_5% D
1 2 2 PQ4
(33) SPOK G 2N7002W-T/R7_SOT323-3
0.1U_0402_16V7K
S
3
1
PC19
@
2
4 4

SCHEMATIC,MB A5141
Rev
Custom B
401690
A B C D
5 4 3 2 1
ISL6237_B+
ISL6237_B+
PR35
PJ10 0_0805_5%
2 1 1 2
B+ 2 1
2200P_0402_50V7K
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
JUMP_43X118
5
VL
5
PC20
PC21
PC22
PC23
PC24
PC25
D D
1
2
2
2
PQ5
2
2
1U_0603_10V6K
SI7326DN-T1-E3_PAK1212-8 PC26 4
2
0.1U_0603_25V7K
4.7U_0805_6.3V6K
4
1
PC27
1
PC28
PQ6
1
SI7326DN-T1-E3_PAK1212-8 +5VALWP
3
2
1
1
2
3
PL4
PL3 8.2UH_FDV0630-8R2M=P3_3.7A_20%
7
8.2UH_FDV0630-8R2M=P3_3.7A_20% PU4 PC29 2 1
1 2 1U_0603_10V6K
LDO
VIN
VCC
+3VALWP
5
33 TP PVCC 19 1 2
4.7_1206_5%
1
DH3 26 15 DH5
UGATE2 UGATE1
PR39
PR36 PQ7 PR37 0_0603_5% PR40 0_0603_5%
4.7_1206_5% SI7716DN-T1-E3_PAK1212-8
2 1 BST3A 24 17 BST5A 2 1
BOOT2 BOOT1
1
@ 61.9K_0402_1%
1 4
2
2
2
PR38 4 PC32 PQ8
2
+
PR41
PC30 0_0402_5% PC31 0.1U_0603_25V7K SI7716DN-T1-E3_PAK1212-8
2
680P_0402_50V7K
150U_B2_6.3VM_R45M 0.1U_0603_25V7K
1
1
PC34
LX3 25 16 LX5 1
2
3
2
1
2 PC33 PHASE2 PHASE1
1
2
3
2
680P_0402_50V7K + PC35
2
DL3 23 18 DL5 150U_B2_6.3VM_R45M
1
LGATE2 LGATE1
2
2
0_0402_5%
C 22 C
PGND
2
FB3 30 OUT2
PR43
@ PR42
10K_0402_1% 10
OUT1
VL 32
1
REFIN2
1
11 FB5
2VREF_ISL6237 FB1
1 2 1 REF
PC36 0.22U_0603_10V7K
www.manuals.clan.su
BYP 9
8 LDOREFIN @ PR44 0_0402_5%
SKIP 29 2 1 VL
PR45 0_0402_5%
1 2
20 NC POK2 28
PD8 PR46
GLZ5.1B_LL34-2 100K_0402_1%
1 2 1 2 4 13 SPOK (32)
VS EN_LDO POK1 PR48
2
200K_0402_1%
255K_0402_1%
2
PR47
14 12 ILM1 2 1
PC37 EN1 ILIM1
0.22U_0603_10V7K
1
27 31 ILIM2 2 1
GND
TON
1
EN2 ILIM2
1
B B
NC
2
PR49
VL
0_0402_5%
PD12 @ PR50 TPS51427_QFN32_5X5 226K_0402_1%
21
PR51
1SS355TE-17_SOD323-2 0_0402_5%
2
2
PR52
1
1
1U_0603_10V6K
806K_0603_1% 2VREF_ISL6237 1
PR54 @ PR55 PR53

+5VALWP Ipeak=8.444A ; Imax=5.91A
1
2
PC146
0_0402_5% 47K_0402_5% 0_0402_5%
+3.3VALWP Ipeak=4.687A ; Imax=3.281A 2 1 1 2 Rds(on)=18m ohm(max) ; Rds(on)=15m ohm(typical)
2VREF_ISL6237 2
1
Choke DCRmax=65.6m ohm (32) MAINPWON Vlimit=(5E-06 * 330K)/10=165mV
0.047U_0603_16V7K
Rds(on)=16.5m ohm(max) ; Rds(on)=13.5m ohm(typical)

Ilimit=165mV/18m ~ 165mV/15m
1
PC38
Vlimit=(5E-06 * 200K)/10=100mV
Ilimit=100mV/16.5m ~100mV/13.5m =9.167A ~ 11A
2
=6.06A ~ 7.41A Iocp=Ilimit+Delta I/2

1
Iocp=Ilimit+Delta I/2 @ PC39 =10.147A ~ 11.980A

3
0.047U_0402_16V7K
=6.614A ~ 7.964A
2
Delta I=1.96A (Freq=400KHz)

Delta I=1.108A (Freq=300KHz)
2 PQ35
TP0610K-T1-E3_SOT23-3
A A
1

SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
A B C D
B+
@PD1
@ PD1 B540C_SMC
1 2
P2 PQ10 P3 B+ CHG_B+ PQ12

PD13 P1403EVG_SO8 PR56 0.05_1206_1% PJ11 P1403EVG_SO8
VIN 2 1 1 8 1 4 2 2 1 1 1 8
2 7 2 7
B340A_SMA2 3 6 2 3 JUMP_43X118 CSIN 3 6
5 5
1 1
5600P_0402_25V7K
2200P_0402_25V7K
4.7U_1206_25V6K
4.7U_1206_25V6K
CSIP PR190
4
47K_0402_1%
1
0.1U_0603_25V7K
PQ33 PQ36 TP0610K-T1-E3_SOT23-3 1 2
VIN
1
PC147
PC42
PC43
PC44
DTA144EUA_SC70-3
PC45
PR59 3 1 DCIN PD14
2
P3
2
PR152 2 200K_0402_1% 1SS355TE-17_SOD323-2
1
100K_0402_1%
47K_0402_1% PR192 1 2 ACOFF
2
PQ37 10K_0402_1%
2
1
PR191
DTC115EUA_SC70-3
PR195
1 1
PD15 200K_0402_1%
1
2
PR194 2 FSTCHG 1 2 VIN
FSTCHG (25)
2
1
PD16 2 1 2 1
1SS355TE-17_SOD323-2 3 SUSP# PD17
1 2 6251VDD 100K_0402_1% SUSP# (25,29,35,36) PQ38 1SS355TE-17_SOD323-2
2.2U_0603_6.3V6K
RB715F_SOT323-3 DTC115EUA_SC70-3 2 1 2
PC148
2 PR196
3
1
PQ34 10K_0402_5%
DTC115EUA_SC70-3 2 1 PU5 PC152
(25) FSTCHG
0.1U_0603_25V7K
0.1U_0603_25V7K
3
1
1
D DCIN PQ40D
1 2 1 24 2 1
3
VDD DCIN
1
1
100K_0402_1%
PC150
2 PC149 2 PACIN
G 0.1U_0402_16V7K 2N7002W-T/R7_SOT323-3
G
PR198
S PQ44 PR193 2 23 S
3
3
2N7002W-T/R7_SOT323-3 150K_0402_1% ACSET ACPRN PR199
20_0402_5%
2
2
6251_EN 3 22 1 2 CSON
EN CSON
5
PC153
0.047U_0603_16V7K
4 21 1 2 CSOP
1
CELLS CSOP PR200 PQ11
2
PC154 6800P_0402_25V7K 20_0402_5% SI7326DN-T1-E3_PAK1212-8 2
1 2 5 ICOMP CSIN 20 2 1 4
1
2
PQ39 D PR201
2 PC155 PR202 6.81K_0402_1% PC156 20_0402_5%
G 2N7002W-T/R7_SOT323-3 1 2 1 2 6 19 0.1U_0603_25V7K
1 2
1
PR204 VCOMP CSIP PR203 PL5
S
3
3
2
1
0.01U_0402_25V7K 1 2 100_0402_1% 2_0402_5% 8.2UH_FDV0630-8R2M=P3_3.7A_20% PR62 0.05_1206_1% BATT+
PC157 1 2 7 18 LX_CHG 1 2 CHG 1 4
ICM PHASE
4.7_1206_5%
PR197 @ 100P_0402_50V8J
1
22K_0402_5% (25) ADP_I 2 3
PR57
PACIN 1 2 PC158 6251VREF 8 17 DH_CHG
(31) PACIN VREF UGATE
PR205 1 2 PR206 PC159
10U_1206_25V6M
10U_1206_25V6M
62K_0402_1% 2.2_0603_5% 0.1U_0603_25V7K
www.manuals.clan.su
2 1 0.1U_0402_16V7K 9 16 BST_CHG 1 2 BST_CHGA 2 1 PQ13
2
(25) IREF CHLIM BOOT
1
1
PQ41 PR212 4 SI7326DN-T1-E3_PAK1212-8
1
PC52
PC53
0.01U_0402_25V7K
DTC115EUA_SC70-3 38.3K_0402_1% PD18
680P_0402_50V7K
6251VREF 1 2 6251aclim 10 15 6251VDDP RB751V-40TE17_SOD323-2
ACLIM VDDP
1
PC40
2
1
1
PC160
ACOFF 2 PR207 1 26251VDD

(25) ACOFF
3
2
1
2
100K_0402_1% PR213 11 14 DL_CHG
VADJ LGATE
2
20K_0402_1% PR208
2
4.7_0603_5%
2
12 13 PC161
3
1
GND PGND 4.7U_0805_6.3V6K
ISL6251AHAZ-T_QSOP24
3 3
Iada=0~1.58A(30W) VMB
CP = 85%*Iada ; CP = 1.343A
PR211
18.2K_0402_1%
1
CP mode 1 2
Vaclim=2.39*(20K/(20K+38.3K))=0.8199V (25) CALIBRATE#
2
VS PR74
Iinput=(1/0.05)((0.05*Vaclm)/2.39+0.05) PR220 LI-3S :13.5V----BATT-OVP=1.5012V 340K_0402_1%
where Vaclm=0.8199V, Iinput=1.343A 31.6K_0402_1%
2
0.01U_0402_25V7K
BATT-OVP=0.1112*VMB
1
Per cell=3.5V
PC65
CALIBRATE# Pre Cell
1
PR76
CC=0.3~1.76A
2
H 4.35V 499K_0402_1%
IREF=1.62*Icharge
2
8
L 3.99V PR77 PU1B
IREF=0.486V~2.85V 10K_0402_1% LM358DT_SO8 5
P
+
1 2 7 0
3.24V==>2A (25) BATT_OVP 6
-
0.01U_0402_25V7K
4
1
PR79
PC66
VADJ-->VREF-->4.41V 105K_0402_1%
Charging Voltage
BATT Type CV mode
2
(0x15) VADJ--->Ground--->3.39V
2
Vcell=(0.175*VADJ+3.99)
4 4
Normal 3S LI-ON Cells

12600mV 12.60V
Charger ADJ Calibrate# PR211 PR220
4.2V N/A @ @
- 3.99V L 301K 499K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5141
4.35V H 301K 499K MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A B C D
A B C D
PJ12
1.8V_B+ 2 1 B+
2 1
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X79
2200P_0402_50V7K
1
1
PC76
PC77
PC41
5
2
PR218
300K_0402_5% 4
1 1 2 1
PR103 PR226 PQ23

0_0402_5% 2.2_0603_5% SI7326DN-T1-E3_PAK1212-8
1 2 BST_1.8V 1 2
(25,29) SYSON
3
2
1
1
1
PR223 PL7
15
14
1
30K_0402_5% PC78 PU6 PC171 2.2U_FDV0630-2R2M-P3_7.2A_20%
@0.1U_0402_16V7K BST_1.8V-1 1 2 1 2
EN_PSV
TP
VBST
+1.8VP
2
2
2 13 DH_1.8V 0.1U_0603_25V7K
TON DRVH
4.7_1206_5%
PR217 3 12 LX_1.8V
VOUT LL
PR93
422_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW
V5FILT TRIP PR146 + PC118
2
5 10 8.66K_0402_1% 220U_B2_2.5VM
VFB V5DRV
1
2
680P_0603_50V7K
6 9 DL_1.8V 4
PGOOD DRVL
PGND
PC72
PC169 PQ24
GND
1U_0603_10V6K PC176 SI7716DN-T1-E3_PAK1212-8
2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC175
3
2
1
4.7U_0805_10V6K
2
<Vo=1.8V> VFB=0.75V
PR227
Vo=VFB*(1+PR227/PR228)=0.75*(1+28.7K/20.5K)=1.8V 28.7K_0402_1%
Fsw=262KHz 1 2
1
Cout ESR=15m ohm Rdson(max)=16.5m Rdson(typical)=13.5m
2 Ipeak=4.6A, Imax=3.22A, Iocp=5.52A PR228 2
Delta I=((19-1.8)*(1.8/19))/(2.2u*261K)=2.83A 20.5K_0402_1%

PJ16
=>1/2DeltaI=1.42A
2
1.05V_B+ 2 1 B+
2 1
Vtrip=Rtrip*10uA=8.66K*10uA=0.0866V
2200P_0402_50V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
@ JUMP_43X79
Iocpmin=Vtrip/(Rdsonmax*1.2)+1.265
=0.0866/(0.0165*1.2)+1.42=5.79A
1
PC86
PC91
Iocpmax=(0.0866/(0.0135*1.2))+1.42A=6.77A
PC46
5
Iocp=5.79A~6.77A
2
www.manuals.clan.su
PR144
300K_0402_5% 4
1 2
PR108 PR109 PQ31
0_0402_5% 2.2_0603_5% SI7326DN-T1-E3_PAK1212-8
1 2 BST_1.05V1 2
(25,29,34,36) SUSP#
3
2
1
1
PR189 PC93 PL11

15
14
1
30K_0402_5% @PC89
@PC89 PU12 0.1U_0603_25V7K 1UH_FDV0630-1R0M-P3_10.3A_20%
0.1U_0402_16V7K BST_1.05V-1 1 2 1 2
EN_PSV
TP
VBST +1.05VSP
2
2
4.7_1206_5%
2 13 DH_1.05V
TON DRVH
PR106
PR110 3 12 LX_1.05V
VOUT LL
5
422_0603_1% 1
+5VALW 1 2 4 11 1 2 +5VALW
V5FILT TRIP PR105 + PC94
2
3 3
5 10 14K_0402_1% 330U_B2_2.5VM_R15M
VFB V5DRV
1
1
2
680P_0603_50V7K
6 9 DL_1.05V 4
PGOOD DRVL
PGND
PC88
PC87 PQ30
GND
1U_0603_10V6K PC92 SI7716DN-T1-E3_PAK1212-8

2
2
1
@ 47P_0402_50V8J
1 2 TPS51117RGYR_QFN14_3.5x3.5 PC90
7
3
2
1
4.7U_0805_10V6K
PR145 2
8.2K_0402_1%
1 2
1
PR104
20.5K_0402_1%
<Vo=1.05V> VFB=0.75V
2
Vo=VFB*(1+PR145/PR104)=0.75*(1+8.2K/20.5K)=1.05V
Fsw=261KHz
Cout ESR=15m ohm Rdson(max)=16.5m Rdson(typical)=13.5m

Ipeak=7.09A, Imax=4.963A, Iocp=8.51A
Delta I=((19-1.05)*(1.05/19))/(1.5u*261K)=2.53A
=>1/2DeltaI=1.265A
4
Vtrip=Rtrip*10uA=14K*10uA=0.14V 4
Iocpmin=Vtrip/(Rdsonmax*1.2)+1.265
=0.14/(0.0165*1.2)+1.265=8.34A
Iocpmax=(0.14/(0.0135*1.2))+1.265A=9.91A
Iocp=8.34A~9.91A Security Classification Compal Secret Data Compal Electronics, Inc.
SCHEMATIC,MB A5141
Rev
Custom B
401690
A B C D
5 4 3 2 1
D D
+1.8V
+5VALW
11
PJ17
JUMP_43X79
1
PC166
2
1U_0603_6.3V6M
2
1
PC163 PU13
4.7U_0805_6.3V6K 6 VCNTL
5 3
2
PR151 9
VIN
VIN
VOUT
VOUT 4 +1.5VSP
1
0_0402_5%
1
1 2 8 PC74
EN
C
(25,29,34,35) SUSP# 7 2 PR215 0.01U_0402_25V7K C
GND
POK FB 1.54K_0402_1%
2
2
1
PC82
2
PR214 PC121 APL5913-KAC-TRL_SO8 22U_0805_6.3V6M
1
@ 47K_0402_5% 0.1U_0402_16V7K
2
2
1
1
PR216
1.74K_0402_1%
2
www.manuals.clan.su
Ipeak=3.464A, Imax=2.425A
+1.8V
B B
1
PU11
1
2 3 PJ14
+3VS IN OUT
+2.5VSP JUMP_43X79
2
1
GND PU8
2
1
PC102 APL5508-25DC-TRL_SOT89-3 1 6
1U_0402_6.3V6K 1 PC106 @PR123
@ PR123 VIN VCNTL
+3VALW
4.7U_0805_6.3V6K 150_1206_5% 2 5
2
GND NC
1
PC100
2
1
PC99 3 7 1U_0603_6.3V6M
4.7U_0805_6.3V6K PR118 VREF NC
2
1K_0402_1% 4 8
VOUT NC
9
2
TP
APL5336KAI-TRL SOP
0.1U_0402_16V7K
PR119
+0.9VSP
1
0_0402_5% PQ27 D
Ipeak=0.14A, Imax=0.098A
PC101
(29) SUSP 1 2 2 PR120
1
G 1K_0402_1% Ipeak=1A, Imax=0.7A
2
1
S PC104
3
PC103 2N7002W-T/R7_SOT323-3 10U_0805_6.3V6M
2
0.1U_0402_16V7K
2
A A

SCHEMATIC,MB A5141
5 4 3 2 1
A B C D E F G H
PR107
124K_0402_1%
2 1
PR112
1_0603_5%
1 +5VS 1 2 1
1
PC98
1U_0603_10V6K Ipeak=3A
1
VREF_CPU
2
1
PR111 Imax=2.1A
PR114 PR133 @ 0_0402_5%
PC96 0_0402_5% 0_0402_5% Iocp=5A
27P_0402_50V8J
2
1 2
2
PMON
1 2 +3VS
VR_ON (25)
PR115
0.22U_0603_10V7K
7.87K_0402_1%
2
PC109
33
32
31
30
29
28
27
26
25
1
PU10
VREF_CPU
PR113 +CPU_B+
TP
DROOP
V5FILT
ISLEW
OSRSEL
TONSEL
TRIPSEL
PWRMON
VR_ON
1
PC97 33P_0402_50V8K 10K_0402_1% PL9
1 2 HCB2012KF-121T50_0805
@ PR142 0_0402_5% 1 2 B+
2
PR117 470_0402_1% 1 24 2 1
VREF CLKEN# CLKEN#
CSN 1 2
4700P_0402_25V7K
PR116 0_0402_5%
0.1U_0603_25V7K
4.7U_0805_25V6-K
4.7U_0805_25V6-K
2
2
PC133
2 GND DPRSLP 23 2 1 PM_DPRSLPVR (6,17)
PC113
PC110
PC132
PC108 <BOM Structure>
33P_0402_50V8K
1
1 2 3 CSN PGOOD 22 VGATE (12,17,25)
2
PR129 PR121 470_0402_1% PC117
100_0402_1% CSP 1 2 100P_0402_50V8J 4 21 4
1
CSP V5IN
1 2
TPS51610RHB_QFN32_5X5
(5) VSSSENSE 5 20 LGATE_CPU PQ25
GNDSNS DRVL SI7326DN-T1-E3_PAK1212-8 PL10
3
2
1
2.2U_FDV0630-2R2M-P3_7.2A_20%
(5) VCCSENSE 6 19 PHASE_CPU 1 2 +CPU_CORE
VSNS LL
2 +CPU_CORE 1 2 2
1
PR134 7 18 BOOT_CPU 1 2 1 2
THERM VBST
5
100_0402_1% PR131
1
PR130 PC112 100K_0402_1%
DPRSTP#
2 1 1 2
PR132 8 17 UGATE_CPU 0_0603_5% 0.22U_0603_10V7K PR126 PR125
10K_0402_1% PH4 VR_TT# DRVH 6.8_1206_5% 43.2K_0402_1%
VID6
VID5
VID4
VID3
VID2
VID1
VID0
2
150K +-5% ERTJ1VV154J 0603 1 2 1 2
4
2
(4) H_PROCHOT# H_PROCHOT# PQ26 PH5
10
11
12
13
14
15
16
SI7716DN-T1-E3_PAK1212-8 150K +-5% ERTJ1VV154J 0603
1
PC111
+1.05VSP 2 1 680P_0603_50V8J 1 2
3
2
1
PR128 PR127
2
68_0402_5% 24.9K_0402_1%
+5VS 1 2
PR135 1 2 0_0402_5% 1 2
www.manuals.clan.su
(4,16) H_DPRSTP#
PR140 1 2 0_0402_5% PC114
(5) CPU_VID6
PR136 1 2 0_0402_5% 4.7U_0603_6.3V6K PC115
CSP
(5) CPU_VID5
PR137 1 2 0_0402_5% 6800P_0402_25V7K
CSN
(5) CPU_VID4
PR138 1 2 0_0402_5%
(5) CPU_VID3
PR139 1 2 0_0402_5%
(5) CPU_VID2
PR143 1 2 0_0402_5%
(5) CPU_VID1
PR141 1 2 0_0402_5%
(5) CPU_VID0
3 3
4 4

SCHEMATIC,MB A5141
C B
401690
A B C D E F G H
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 2

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
D Cahnge PR19 to SD034732180 (S RES 1/16W 7.32K +-1% 0402) D
1 Modify CPU OTP circuit For thermal team request 0.1 31

Cahnge PR22 to SD034174280 (S RES 1/16W 17.4K +-1% 0402)
09/01/14 DVT
Cahnge PC30 to SGA00004H00 (S POLY C 150U 6.3V M B2 LESR25M PSL H1.9 )

2 Modify 3/5V output cap design change 0.1 32
Cahnge PC35 to SGA00004H00 (S POLY C 150U 6.3V M B2 LESR25M PSL H1.9 )
09/01/14 DVT
add PR211 to SD034301380 (S RES 1/16W 301K +-1% 0402 )

3 Modify Charger modify redulate charger ADJ voltage 0.1 33
add PR220 to SD034499380 (S RES 1/16W 499K +-1% 0402 )
09/01/14 DVT
Cahnge PR226 to SD013220B80 (S RES 1/10W 2.2 +-5% 0603 )

4 Modify 1.8v/1.05v boost circuit for APW7141 issue 0.1 34
Cahnge PR109 to SD013220B80 (S RES 1/10W 2.2 +-5% 0603 )
09/01/14 DVT
5 add all sunbber for 3G and EMI team request 0.1 34 add all sunbber 09/01/14 DVT
H-side to SB00000IA00 (S TR SIS412DN-T1-GE3 1N POWERPAK1212-8 )

6 Modify HMOS and LMOS for cost down 0.1 34
L-side to SB00000I400 (S TR IRFH3707TRPBF 1N PQFN )
09/01/14 DVT
7 add input capacitance for 3G solution 0.1 34 add PC41 PC46 SE074222K80 (S CER CAP 2200P 50V K X7R 0402) 09/01/21 DVT
C 8 modify 1.05v TRIP R modify ocp point 0.1 34 modify PR105 to SD034140280 ( S RES 1/16W 14K +-1% 0402) 09/02/02 DVT C
9 modify 3V/5V OCP point design change 0.1 34 Cahnge PR48 SD034255380 (S RES 1/16W 255K +-1% 0402 ) 09/02/02 DVT
10 modify 3V/5V OCP point design change 0.1 34 Cahnge PR49 SD034226380 (S RES 1/16W 226K +-1% 0402) 09/02/18 PVT
11 modify chager circuit design change 0.1 34 Add PQ44 SB000006800 S TR 2N7002W T/R7 1N SOT-323 09/02/18 PVT
12
13
modify chager circuit
modify chager circuit www.manuals.clan.su

design change
design change
0.1
0.1
34
34
Add PQ34 SB301150000 S TR DTC115EUA NPN (UMT3)
Add PR152 SD034470280 S RES 1/16W 47K +-1% 0402

09/02/18 PVT
09/02/18 PVT
14 modify chager circuit design change 0.1 34 Add PQ33 SB101440200 S TR DTA144EUA PNP UMT3 09/02/18 PVT
15
B B
16
17
18
19
20
21
22
A A
23

SCHEMATIC,MB A5141
Rev
Custom B
401690
5 4 3 2 1
5 4 3 2 1
KAV10 KAV60 <2008/11/17>

1. ADD WWAN_WAKEUP# ON pin 45 on page 19
A-TEST Change A-TEST Change 2. DEL R79 ,R92 and change net name to WWAN_WAKEUP# on page 25
3. DEL R90 and WWAN_LED_R# on pin 85 on page 25
<2008/11/14> 4. change net name form WWAN_LED_R# to WWAN_LED# on page 28
<8/25> 1. change R28,R32 BOM structure on page 4
1. Update Power SCH 2. change LCD POWER CIRCUIT form KAW10 to JAQ10 on page 13 <2008/11/18>
<8/26> 3. change C670 BOM structure on page 13 1. Place R282,R296 close to F27,D27 on page 8
1. Update Power SCH 4. change L5,L19(BK61608LL121-T0603) to R281,R287(39_0402) on page 14 2. Del R93 R407(0_0402) on page 19
D
2. Change 5. change +CRT_VCC to +5VS on page 14 3. Move R204 from P16 to P25 D
D7 SC300000D00 to SC300000O00 6. del R244(100K_0402) and add T17 on page 15 4. Move R24 from P17 to P25
3.Change 7. change J6 jump size form 43 x 118 to shortpads on page 16 5. change Q10A,Q10B to 0 ohm on page 12
C49C50 SE071180K80 to SE071180J80 8. change R204 BOM structure on page 16 6. del pull up resistance (R112,R108) on page 12
<8/27> 9. change Q11 from SOT23 to SOT323-3 on page 17 7. change C883 from 4.7u to 10u on page 22
1. Updata Power SCH 10.change USB OC# circuit on page 17
2. Modify 11.Del R186(0_0805_5%) and +1.5VS_DMIPLLR on page 18 <2008/11/20>
RJ45 temp footprint FOX_JM3611A-R4122-7F_12P-T 12.CHANGE R62(0_1206) to J9(43x39) on page 19 1. change R112,R108,Q10A,Q10B BOM structure on page 12
<8/28> 13.Del R83 R348 0_0402 on page 19 2. add R149,R150 on page 12
1. Updata Power SCH 14.Mobile EC_TX,EC_RX from WLAN to WWAN and add R96 on page 19 3. add pull up resistance R292 on page 19
<9/1> 15.CHANGE R65,R70(0_1206) to J10,J11(43x39) on page 19 4. del R66(0_0402),R67(10K_0402) on page 25
1. Updata Screw 16.change +UIM_PWR_1 to +UIM_PWR on page 19 5. restore R563,Q31 BOM structure on page 13
<9/5> 17.Del D16(DAN217T146_SC59-3),R94,R408(0_0402) on page 19 6. change D25 BOM structure on page 20
1. SWAP USB20_1 Signal. 18.change +5VS to +3VS on page 19
<9/10> <2008/11/21>
19.change EC signal name form BT_OFF# to BT_ON# on page 19 1. Change +3VS to +3VALW on page 19
1. Remove Mini card pin55pin56 GND 20.del Q21 on page 19
2. Change JREAD1.42H26 to GNDA 2. del R204 on page 25
21.ADD PMOS SOFT START on page 19 3. del R143 and CLK_SD_48M on page 12
<9/12>
1. Swap 3G ESD pin neme 4. Change R137 from 12 ohm to 33 ohm on page 12
<2008/11/16> 5. Move Card Reader to small board on page 23
<9/15> 1. +VDDA CHANGE TO +5VS on page 20
1. Update Audio Jack footprint 6. Move SATA HDD Conn to small board on page 22
2. Analog ground change to digital ground on page 20 7. ADD JP7 on page 22
C
2. Chcnge R641R642 300ohm to 511ohm for Arthros 3. Del L22 on page 20 C
3. Update L footprint 8. change JP2 from 6 pin to 8 pin on page 26
4. DEL R383 R382 R384 GNDA & GND on page 20 9. DEL LID Switch on page 26
<9/16> 5. change R380,R379,R381 form 0805 tO 0603 page 20
1. Update POWER SCH. 6. Add R94,R87 Vender suggesttion on page 21 <2008/11/24>
<9/17> 7. Analog ground change to digital ground on page 21 1. return the H5.2 pootprint on page 11
1. Update POWER SCH. 8. reserve C5,C6,C883,C884 on page 22
2. ADD R380R383 for ESD. 9. reserve +3VALW on page 22 <2008/11/25>
<9/18> 10.change +3VS to +CAM_VCC on page 22 1. add add R90 on page 19
1. Update ATHEROS 10/100 LAN <AR8132/AR8114> 11.change R651,R634 form (0_0603) to 43 x 39 jump on page 23 2. change JMIN1 Conn printfoot on page 19
<9/24> 12.add net name +3VS_READER on page 23 3. change JP2 Conn on page 26
www.manuals.clan.su
1. Change C870 0.1u to 1u. 13.add net name AV_PLL on page 23 4. change JP13 Conn on page 28
<9/26> 14.add net name VREG on page 23 5. update power SCH
1. R88 change to 0ohm. 15.+3VS change to +3VS_READER on page 23
16.change R619 BOM structure on page 23 <2008/11/26>
17.add net name RREF on page 23 1. change JP20 Conn and pin design on page 21
B-TEST Change 18.del R623(0_0402) on page 23 2. change JBT1 form 8 pin to 4 pin on page 19
19.Chang C855 form 4.7U to 10U on page 24 vendor suggest 3. del JP1 on page 13
20.Chang C846 form 4.7U to 10U on page 24 vendor suggest 4. SWAP JP12 on page 27
<10/21> 21.change BJT form MMJT9435T1G to MBT35200 on page 24 5. change JLVDS1 Conn form 20 pin to 30 pin on page 13
1.Remove C389 for Audio can't detect issue on page 16 22.change EC signal name form BT_OFF# to BT_ON# on page 25 6. Del JP4 on page 20
2.Add KSO1/KSO2 PU +3VALW on page25 23.change D12,R103,R104 BOM structure on page 25 7. combine the DMIC Conn and Camera Conn on page 13
B
3.Add R205 for schematic mistake on page 04 24.change J1,J3(43 x 79) to R186,R193(0_0805) on page 26 8. add U7 on page 28 B
4.Change EC RST to PLTRST on page 25 25.change Q3 from 2N70002_SOT23 to 2N7002W-T/R7_SOT323-3 on page 26 9. del JP3 on page 28
5.Add J8 to cost down Audio LDO on page 20 26.change Q1 form 2N70002_SOT23 to 2N7002W-T/R7_SOT323-3 on page 26 10.ADD SATA&CARDREADER&USB Conn(JP7) on page 22
6.Add R72 to reserve +3VALW for 3G on page 19 27.change net name form WWAN_LED# to WWAN_LED_R# on page 28 11.update Power SCH
7.Reserve C238 for CRTDAC on page 10 28.change R130 BOM structure on page 28 12.change C233 BOM structure on page 19
8.Add R87 for Debug card on page 19 29.change JP3 pin assignment on page 28 13.change JRJ45 Conn on page 24
9.Change C108/C255 to 0.1uF for random hang issue 30.change Q2,Q15,Q24,Q7,Q23 form 2N70002_SOT23 to 2N7002W-T/R7_SOT323-3 on P29 <2008/11/28>
10.Change JP3 pin assignment on page 28 31.change R18,R169,R280,R61,R279,Q2,Q15,Q24,Q7,Q23 BOM structure on age 29 1. update Power SCH
<10/21> 32.+5VALW CHANG TO VL on page 29
1. Update Power SCH
<10/29> <2008/12/01>
1. Audio AMP 10dB update to 6dB 1. chang JP2 Conn on page 26
<11/3> <2008/11/17> 2. udate Power SCH
1. Update Power SCH 1. update POW SCH
<11/4> 2. change DIMMA from H5.2 to H4 on page 11
1. Change R373R374 to 56.2 ohm for DA-HP FSOV 3. change +3VS to +5VS on page 14 <2008/12/02>
2. Add C834C851 for 3G noise 4. change J9,J10,J11 from 43x39 to 43x79 on page 19 1. SWAP JLVDS1 on page 13
3. Change KB926 C1 to D2 5. change R563,Q31 BOM structure on page 13 2. del C843,C844 on page 24
4. Card reader RT5158E change to RT5159-GR 6. del +3VALW on page 22 3. change C847 from 0.1u to 1u on page 24
<11/5> 7. del +1.5VS,+VCCP,+0.9VS,+1.8V Discharge 4. change C873 from 0.1u to 1u on page 24
1. Swap D7 pin define path R18,R280,R61,R279 Q2,Q24,Q7,Q23 on page 29 5. move R441,R438 form P13 to P20 on page 20
<11/10> 8. change R24 BOM structure on page 17 6. change +5VAMP to +5VS on page 21
A
1. EC add R79R90R92 for SMS wakeup 9. del R253 on page 19 7. R2,R4,R518 close to EC on page 26 A
10.change L14 to R382 on page 25 8. R1 close to Q3 on page 26

SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1
5 4 3 2 1
<2008/12/03>
1. SWAP JP7 pin define on page 22 <2009/01/20>
<2008/12/22> 1. add JDIM1 pin 200 and pin 201 to GND
2. change PJP2 connector on page 32 1. change D1 BOM structure on page 26 <2009/02/06>
on page 11
<2008/12/04> 2. change C116 form 1U to 4.7U on page 25 2. JMINI1 pin 55,56 change to 1. change C226 BOM structure on page 19
1. update Screw on page 30 3. change R24 from 10k to 47K non-GND on page 19 2. Change U3 from SA000035G00
2. change JCRT1 Conn to SP010811273 on page 14 R103 from 0 to 2.2K on page 25 3. SWAP JP20 on page 21 to SA000022J00 on page 28
3. SWAP PJP2 pin define on page 32 4. change D12,R104 BOM structure on paage 25 4. change H18 to non-GND on page 30 3. change L13 from SM01000AL00 to SM010004010
4. add J12 on page 21 5. change L30,C856,C857 BOM structure on page 24 5. Chang C160 from 0603(4.7u) to 0402(2.2u) on page 25
6. change D17 P/N from SCA00000700 on page 24 4. change L23 from SM010032020 to SM010004010
<2008/12/05> to SCA00000A00 and BOM structure on page 13 on page 20
1. del D8 and change D5 P/N on page 28 7. change D2 P/N from SC300000O00 <2009/01/21 Ivan> 5. change U26,C459 BOM structure(@) on page 20
D D
2. SWAP D2 pin define on page 13 to SC300000B00 and BOM structure on page 13 1. change R441 from 0ohm/0603 to 33ohm/0402 6. change R1,R2,R4 from 300 to 200 ohm on page 26
3. change JBT1 Conn on page 19 8. change D3,D4 P/N from SCA00000G00 2. change C459 from 0.01uF/0402 to 4.7uF/0603 7. change R518 from 300 to 422 ohm on page 26
4. update POWER SCH to SCA00000A00 and BOM structure on page 14 3. change R438 from 0ohm/0603 to 0ohm/0402 8. change R137 from 33 to 39 ohm on page 12
9. change D33 P/N from SC10T24C000 9. change C32 from 10P to 15p ohm on page 12
<2008/12/08> to SCA00000A00 and BOM structure on page 26 <2009/01/21-1> 10.change C42,C45 from 22p to 15p on page 12
1. add J15 J16 on page 22 10.change D18 P/N from SC10T24C010 1. change U26 BOM structure on page 20 11.change R115,R121 from 39 ohm to 47 ohm on page 12
2. return D2 pin define on page 13 to SCA00000A00 and BOM structure on page 27 2. del C11,C28,C26 on page 22 Pre C memo
3. change JUSB1 Conn on page 28 11.change D9 P/N from SC10T24C010 3. Update Power SCH
4. swap JP6 pin define on page 27 to SCA00000A00 and BOM structure on page 27
5. add C32,C33,C42 for keypart on page 12 12.change D29 P/N from SC300000O00 <2009/02/18>
to SC300000B00 and BOM structure on page 28 <2009/01/22> 1. change R279,R280,R294,R295 BOM structure
6. add C5 for keypart on page 13 1. update H15,H19,H20,H30 from 3P8 to 3P6
7. add C9 for keypart on page 16 <2008/12/24> on page 17
01/22 2. change U26,C459 BOM structure
8. add C11,C21,C26,C27 for keypart on page 22 1. change C32 C33 C42 C45
BOM structre on page 12 on page 20
<2009/01/22-1> 3. change L13 from SM010004010 to SM010032020
<2008/12/10> 2. change C117 BOM structure on page 25 1. del C94 C95 on page 11
1. del H11 H_3P0N on page 30 3. change R88 from 0 ohm to 22 ohm on page 25 on page 25
2. add C164,C165 01/22 4. change L23,L24 from SM010004010 to
2. Change to SA00002CI10 to SA00002CI20 4. U2 Change to SA000033H00 on page 28 3. move C159 from page 11 to page 12
S IC ALC272X-GR LQFP 48P CODEC on page 20 5. U7 Change to SA000033H00 on page 28 SM010032020 on page 20
4. add R383 on page 20
3. add net name(+VCCP_D) 20mil on page 10
4. SWAP D29 Pin Define on page 28 <2009/01/22-2>
5. change R185 from 200K to 33K on page 29 Pre MP-TEST Change
1. change C396 from 10U/0806 to 4.7U/0603
C 6. change R68 from 200K to 22K on page 29 Pre C-TEST Change on page 28 <2009/02/18> C
2. add C469 on page 28 1. Del J6 and add R219 on page 16

<2008/12/11> <2008/12/29> 2. Del C249 on page 10
1. change H17 from H_2P5 to H_2P5x4P4 on page 30 1. change R141,R140,R147,R81,R91 3. change LED2 BOM structure on page 26
2. del R388,R387,R386,R385,D10,D13 on page 21 R82,R97,R95,R98 BOM structure on page 12 <2009/01/22-3>
1.add C268 01/22 <2009/02/20>
3. update Power SCH 2. Change R130 from 200K to 100K Pre C gerber
1. update Power SCH
4. +5VS change to +5VALW on page 21 and change BOM structure on page 28 2. del L8,R145,R146 on page 13
3. change D5 BOM structure on page 28 <2009/01/23>
<2008/12/14> 1. change C249 BOM structure(@) on page 10 <2009/02/22>
1. Del R129 on page 12 1. update H15,H19,H20,H30 from 3P6 to 3P3
www.manuals.clan.su
<2008/12/231> 2. change C603 from 220P to 100P on page 13
2. add C45 for keypart on page 12 1. change R371 from 0 ohm to 22 ohm on page 20 3. change C21 from 10p to 22p on page 16 on page 30
3. del R76 on page 25 2. U3 Change to SA000035G00 on page 28 4. change C459 from 4.7uF to 1uF on page 20 2. change H18 from 3P2N to 3P1N on page 30
5. change R371,C470 BOM structure(@) on page 20 3. add R107,R110 on page 19
<2008/12/15>
1. change R137 BOM structure Memo control 6. change C604 from 220P to 18P on page 20 <2009/02/23>
and add R143 on page 12 7. change R122,R123,R124,R125 1. del R644 on page 24
2. change C852,C853,Y5 BOM structure on page 24 from 4.7K to 2.2K on page 25 <2009/02/24>
<2008/12/31> 8. change R284 from 150 ohm to 300 ohm 1. change U5,U1,U6 from R1 P/N to R3 P/N
3. add C55 on page 24
1. del C9 on page 16 R286 from 120 ohm to 100 ohm on page 26 2. change C45 from 15p to 10p on page 12
4. change C842 BOM structure on page 24
2. add C21 for keypart on page 16 9. change D5 BOM structure(@) on page 28
5. del J15,J16,C21 on page 22
3. change R644 from 0603 to 0805 on page 24 10.change C162 from 27P to 22P on page 12 <2009/02/25>
6. add net name BATT_AMB_LED#
4. change R643 from 0603 to 0402 on page 24 11.change C852,C853 from 27p to 15p on page 24 1. change U2,U7 to SA000039E00 <ANPEC> on page 28
BATT_GRN_LED# on page 22
5. change C841 from 0603 to 0402 on page 24 12.change C49 C50 from 18pf to 10pf on page 16 2. change U3 to SA00002XA00 <ANPEC> on page 28
7. +3VS_READER change to +3VALW on page 22
B 6. change L29,L30 from 0805 to 0603 on page 24 13.change c150,c123 from 15p to 22p on page 25 3. change R77,R89,R80 form 0 ohm to 22 ohm on page 25 B
<2008/12/16> 7. del R637 R638 on page 24

1. del R143 on page 12 <2009/02/27>
2. del C55 on page 24 <2009/01/23-1> 1. change D9,D18 P/N from SCA00000A00
3. swap CLK_PCIE_CARD and CLK_PCIE_CARD# on page 27 1. change C42,C45 from 10p to 22p on page 12 to SCA00000200 on page 27
2. R115,R121 from 33 ohm to 39 ohm on page 12 2. change D33 P/N from SCA00000A00
<2008/12/17> <2009/01/13> to SCA00000200 on page 26
1. modify H15,H19,H20,H29,H30 on page 30 1. SWAP JP11 on page 27 3. change C603 from 100P to 47P on page 13
2. add H32 on page 30 2. change SW4 P/N to SN111005800 on page 26 4. change R441 from 33 ohm to 39 ohm on page 20 3. change U2 from SA000039E00 to SA000033H00
5. change C604 Bom structure(@) on page 20 on page 27
3. +5VALW change to +3VALW on page 26 3. ADD C160 on page 24 4.
4. change JMIN1 Conn foorprintt on page 19 Pre C BOM 5. change D3,D4 BOM structure(@) 03/01
<2008/12/18> 5. Change PWR_LED and PWR_SUSP_LED#
C-TEST Change
1. add R102 on page 19 Net name on page 26
<2009/02/03> <2009/03/04>
6. Change C231 P/N to SGA00001E00 on page 28
1. Add R105,R106 on page 19 1.change U8 from D2 to D3(SA00001J580) on page 25
2. ADD BATT_GRN_LED_1# and 2.change R66,R102 BOM structure(@) on page 19
<2008/12/19> <2009/01/14> BATT_AMP_LED_1# on page 25 3.change R120 and R126 BOM structure on page 25
1. change R284 from 453 ohm to 150 ohm 1. add R660 pull up +3VALW on page 25 3. add R651 O_0402 on page 24 4. change R518 from 422 to 220 on page 26
R286 from 300 ohm to 120 ohm on page 26 2. change R120 and R126 to PVT ID on page 25 <2009/02/04> 5. change R1 from 200 to 470 on page 26
2. change 8132 P/N to SA000033N00 on page 40 3. update Screr 1. add R279,R280,R294,R295 on page 17 6. change R286 from 100 to 68 on page 26
4. add C28 for keypart on page 22 2. del C26 on page 22 7. change R2,R4 from 200 to 220 on page 26
3. change C841 from 0402 1U to 0603 1U
on page 24 <2009/03/06>
<2009/01/16> 1. change R1 from 470 to 390 on page 26
A A
1. del H31 on page 30
2. change JP20 Conn on page 21 <2009/02/05>
3. del D29,L9,R144,R136 on page 28 1.Del J10,J11 and add R65,R66 on page 19
C modify gerber
<2009/01/17>
1. Del R110,R119 on page 12 Security Classification Compal Secret Data Compal Electronics, Inc.
2. change R141,R140,R147,R81,R91,R82,R97, Issued Date 2006/08/18 2007/8/18 Title
Deciphered Date
R95,R98 BOM structure on page 12
Pre C BOM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC,MB A5141
Custom B
401690
5 4 3 2 1

Acer Aspire One AOP531H - D520 Compal LA-5141P PDF

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A B C D E

LA-5141P REV1 M/B

Security Classification Compal Secret Data Compal Electronics, Inc.

Compal Confidential Diamondville SC

FSB Clock Generator

BGA652 to I/O board

Power ON/OFF RJ45

S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW

S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF

S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF

S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF

3 ICH7M SM Bus address 3

BOARD ID Table(Page 25) Device Address

ID BRD ID Ra Rb Vab Clock Generator 1101 001Xb

Security Classification Compal Secret Data Compal Electronics, Inc.

A[33]# THRMDA (6) H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 (6)

H_NMI FORCEPR# DPSLP# H_DPWR#

NC2 RSVD2 CPU_BSEL2 BSEL[1] CMREF[1]

1 8 EC_SMB_CK2 EC_SMB_CK2 (25)

Security Classification Compal Secret Data Compal Electronics, Inc.

U5D U5C +VCCP

10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z 10U_0805_10V4Z

PLACE IN CORRIDOR AND CLOSE TO CPU

Security Classification Compal Secret Data Compal Electronics, Inc.

(4) H_D#[0..63] H_A#[3..31] (4)

H_D#_36 H_BPRI# H_BPRI# (4) SM_OCDCOMP_1 PM_ICHSYNC# MCH_ICH_SYNC# (15)

H_D#60 AB1 H_D#_60 Strap Pin Table

H_D#61 AB7 H_D#_61

H_D#62 AA2 C8 H_HIT#

C50 be placed <100mils

D U1C DDR_A_D[0..63] (11)

DDR2 SYSTEM MEMORY

Security Classification Compal Secret Data Compal Electronics, Inc.

U1F R190 +1.5VS_PCIE

Security Classification Compal Secret Data Compal Electronics, Inc.

Security Classification Compal Secret Data Compal Electronics, Inc.

AC26 VCCAUX10 VCCSM16 AH24

1 AE19 VCCAUX12 VCCSM18 AF24

D6 VTT15 VCCSM51 AJ10

U5 VTT16 VCCAMPLL AD1 +1.5VS_MPLL 45mA +2.5VS

+ D5 VTT20 VCCDHMPLL1 AE5 +1.5VS 150mA

P3 VTT29 VCCSYNC J23 70mA

C283 C248 +2.5VS +2.5VS

close pin C29/D29 close pin B31

Security Classification Compal Secret Data Compal Electronics, Inc.

@ For EMI DDR issue 65 66

DDR_A_D34 135 136 DDR_A_D39

DDR_A_D40 141 142 DDR_A_D45

56_0804_8P4R_5% 56_0804_8P4R_5% Place these resistor DDR_A_DM7 185 186 DDR_A_DQS#7

1 1 1 Reserved SA000020K00 (Silego : SLG8SP556VTR ) 1 2

change R141,R140,R147,R81,R91 +3VM_CK505 U11

change R137 BOM structure 12/15 19 VDD_48 CPU_1 68 CLK_MCH_BCLK

(4) CPU_BSEL0 1 2 R142 31 25 CLK_MCH_DREFCLK#

<BOM Structure> MCH_SSCDREFCLK

FSB <BOM Structure> REF_1 SRC_4

for keypart 12/08

FSC PCI_2 SRC_9# SATA_CLKREQ# R111 10K_0402_5%

<BOM Structure> 39 ohm to 47 ohm 02/06 1 2 ITP_EN 17

10P_0402_50V8J VSS_PCI SRC_11#

LCD POWER CIRCUIT

(8) GMCH_ENVDD 2 SWAP D2 pin define 12/05

move R441,R438 form USB20_P1 USB20_P1_1

add C5 for keypart 12/08 2