Compal Electronics Schematics Document

A
Compal Confidential
Schematics Document
2
INTEL Auburndale BGA with IBEX core logic
Swatch UMA
LA-5251P
2010-01-04
REV:0.9
Compal Secret Data
Security Classification
2008/09/15
Issued Date
2010/12/31
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Compal Electronics, Inc.

Cover Sheet
Size Document Number

Custom LA-5251P
Date:
R ev
0.9
Tuesday, January 05, 2010
Sheet
E
of
47
Swatch UMA
Compal Confidential
File Name : LA-5251P
Accelerometer
XDP Conn.
Page 4
LIS302DLTR
Mobile
PEG-eDP
Display port panel
Page 24
Page 20
DDR3 1066/1333MHz 1.5V
Auburndale CPU
BGA 1288pins
BANK 0, 1, 2, 3
Fan Control
DDR3-SO-DIMM X 2
Page 4
Page 9,10
Dual Channel
VGA
RGB
Thermal Sensor
EMC2113 Page 4
Page 4,5,6,7,8
Page 18
DP *1(Docking)
FDI
DDI_D
Display port
Page 29
DMI X4
CK505
Page 18
USB *1(Docking)Page
DDI_B
USB conn*1(Left side)
Express Card 54
WWAN
+SIM Card
PCIE *1 + USB *1
USB*1
Page 23
Page 11
Page 24
DDI
2
Clock Generator
SLG8SP585VTR
29
USB2.0
FingerPrinter Validity VFS451

daughter board Module
Page 32
USB*1
USB2.0
Intel Ibex Peak M
Page 23
Azalia
USB conn x 3(For I/O)-Rear side, Power USB
1071pins
PCI-E BUS
BT Conn USB x 1
SATA0
25mm*27mm
Page 24
SATA1
USB x1(Camara)
10/100/1000 LAN
Intel Hanksville GbE
PHY
WLAN Card
Rico R5C835 Controller
Page 12,13,14,15,16,17
Page 25
PCIE*1
Page 21
PCI BUS
Page 20
SATA3
MDC V1.5
Page 22
ONFI Interface
IDT 92HD75
Page 23
1394 port
Page 21
Page 25
Page 28
TPA6047A4RHBR
Audio CKT
Braidwood
RJ45 CONN
RJ11
Page 28
AMP & Audio Jack
Page 26
Page 27
Smart Card SD/MMC Slot
Page 32
Page 25
SATA ODD Connector
Page 22
NAND Flash Card

Page 23
1.8" SATA HDD Connector
LPC BUS
RTC CKT.
Page 12
Page 22
LED
Page 29
LED Board
Page 28
SMSC KBC 1098
Power OK CKT.
Page 33
Power On/Off CKT.
page 30
Touch Pad CONN.
TPM1.2
SLB9635TT
SATA*1(Docking) Page
Page 32
Int.KBD
Page 28
Page 28
Page 28
29
(2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Docking CONN.
USB 1.channels
Display Port Channels
Line In
Line Out
RJ45 (10/100/1000)
VGA
2 LAN indicator LED's
Power Button
SATA
TrackPoint CONN.
Page 28
DC/DC Interface CKT.

Page 34
A
SPI ROM
Compal Secret Data
2008/09/15
Issued Date
8 MB
2010/12/31
Deciphered Date
Page 31
B
Title

Block Diagram

Custom LA-5251P
Date:
R ev
0.9
Sheet
E
of
47
Voltage Rails
( O MEANS ON
X MEANS OFF )
Symbol Note :
+RTCVCC
+B
+5VALW
+3VM
+1.5V
+5VS
+3VL
+3VALW
+1.05VM
+0.75V
+3VS
: means Digital Ground
+1.5VS
+VCCP
power
plane
+CPU_CORE
: means Analog Ground
+1.05VS
+1.8VS
@ : means just reserve , no build

CONN@ : means ME part.
SV@ : means just build on SV Sku. LV Sku no build.
LV@ : means just build on LV Sku. SV Sku no build.
State
S0
S1
S3
S5 S4/AC
S5 S4/ Battery only
S5 S4/AC & Battery

don't exist
Layout Notes
01/04 update
: Question Area Mark.(Wait check)
Install below 45 level BOM structure for ver. 0.1

45@ : means just put it in the BOM of 45 level.
Install below 43 level BOM structure for ver. 0.1
DEBUG@ : means just build when PCIE port 80 CARD function enable. Remove before MP
SMBUS Control Table
SOURCE
SMB_EC_CK1
SMB_EC_DA1
SMSC1098
SMBCLK
SMBDATA
Calpella
SML0CLK
SML0DATA
Calpella
SML1CLK
SML1DATA
Calpella
BATT
XDP
V
X
X
X
X
V
X
X
SODIMM
X
V
X
X
CLK CHIP
X
V
X
X
MINI CARD
X
V
X
X
DOCK
NIC
THERMAL
SENSOR
G-SENSOR
X
V
X
X
X
X
V
X
X
X
X
V
X
V
X
V
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2010/12/31
A
Title

Notes List

Custom LA-5251P
Date:
R ev
0.9
Sheet
of
47
Layout rule 10mil width trace

length < 0.5", spacing 20mil
COMP2
49.9_0402_1% 1 R7
H_COM P1
AD69
COMP1
H_COM P0
AE66
COMP0
49.9_0402_1% 1 R9
P AD T48
TP_SKTOCC#
M71
H _CATERR#
N61
PROC_DETECT
CATERR#
BCLK
BCLK#
AK7
AK8
C LK_CPU_BCLK
CLK_CPU_BCLK#
BCLK_ITP
BCLK_ITP#
K71
J70
CLK_CPU_XDP
CLK_CPU_XDP#
PEG_CLK
PEG_CLK#
L21
J21
CLK_EXP
CLK_EXP#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
Y2
W4
CLK_CPU_BCLK 15
CLK_CPU_BCLK# 15
07/09 update for INTEL S3 leakage issue.

CLK_EXP 13
CLK_EXP# 13
2
1 R 17
H_THERMTRIP#
H _CPURST#
H_CP UP W RGD
14
N17
H_ CPURST#_R
2
0_0201_5%
H_P M_SYNC_R
1 R 19
2
0_0201_5%
N70
RESET_OBS#
M17
PM_SYNC
1 R21
2 SYS_AGENT_P WROK AM7

0_0201_5%
H_CP UP W RGD
1 R 22
2 V CC PWRGOOD_0
0_0201_5%
PM_DRAM_PWRGD
1 R 26
2 V DDP W RGOOD_R
0_0201_5%
15
B
2 H_THERMTRIP#_R
0_0201_5%
1 R 18
H_ PM_SYNC
PROCHOT#
Y67
AM5
THERMTRIP#
Power Management
14
N67
VCCPWRGOOD_1
VCCPWRGOOD_0
SM_DRAMPWROK
from power
VTTPWRGOOD
H_PWRGD_XDP
15
BUF_PLT_RST#
0_0201_5%
H _PWRGD_XDP_R
1 R 32
2R33 PLT_RST#_R
1.5K_0402_1%
H15
VTTPWRGOOD
Y70
TAPPWRGOOD
G3
RSTIN#
32
SM_DRAMRST#
BJ12
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
BV33
BP39
BV40
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PM_EXT_TS#[0]
PM_EXT_TS#[1]
AV66
AV64
PM_EXTTS#0
PM_EXTTS#1 1
0_0201_5%
PRDY#
PREQ#
U71
U69
XDP_PRDY#
XDP _PREQ#
TCK
TMS
TRST#
T67
N65
P69
X DP_TCK
XDP_TMS
XDP_TRST#
TDI
TDO
TDI_M
TDO_M
T69
T71
P71
T70
XDP_TDI
X DP_TDO
X DP_TDI_M
DBR#
W71
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
J69
J67
J62
K65
K62
J64
K69
M69
2 R 1092
PM_EXTTS#1_R
9 ,10
from DDR
XDP_BPM#0
XDP_BPM#1
XDP_BPM#2
XDP_BPM#3
XDP_BPM#4
XDP_BPM#5
XDP_BPM#6
XDP_BPM#7
XDP_BPM#0 R23
@ R24
XDP_BPM#1 R25
@ R27
XDP_BPM#2 R28
@R29
XDP_BPM#3 R30
@R31
1
1
1
1
1
1
1
1
ESD request to add
5
5
CFG 12
CFG 13
CFG 14
CFG 15
XDP_BPM#4 0_0201_5%
XDP_BPM#5 0_0201_5%
+VCCP
1
C1
0.1U_0402_16V4Z
2
@
C 120
+VCCP
V DDP W RGOOD_R
1
R 12
1
R 13
2
2
0.1U_0402_16V4Z
V CCP_1.5VSPWRGD
1.5K_0402_1%
32
750_0402_1%
P CH_ DDR_RST
08/28 update
14
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
2
2
2
2
2
2
2
2
CF G17
CF G16
2 R43 XDP_BPM#4_R
2 R48 XDP_BPM#5_R
1
1
XDP_BPM#6 0_0201_5% 1
2 R40 XDP_BPM#6_R
XDP_BPM#7 0_0201_5% 1
2 R41 XDP_BPM#7_R
R36 1K_0201_5%
H_CP UP W RGD 1
2 H_CP UP W RGD_R
PM_PWRBTN#_R
PM_PWRBTN#_R
H_PWRGD_XDP 1
R37
2
0_0201_5%
P AD T112
P AD T113
C1 19
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
GND0
OBSFN_A0
OBSFN_A1
GND2
OBSDATA_A0
OBSDATA_A1
GND4
OBSDATA_A2
OBSDATA_A3
GND6
OBSFN_B0
OBSFN_B1
GND8
OBSDATA_B0
OBSDATA_B1
GND10
OBSDATA_B2
OBSDATA_B3
GND12
PWRGOOD/HOOK0
HOOK1
VCC_OBS_AB
HOOK2
HOOK3
GND14
SDA
SCL
TCK1
TCK0
GND16
GND1
OBSFN_C0
OBSFN_C1
GND3
OBSDATA_C0
OBSDATA_C1
GND5
OBSDATA_C2
OBSDATA_C3
GND7
OBSFN_D0
OBSFN_D1
GND9
OBSDATA_D0
OBSDATA_D1
GND11
OBSDATA_D2
OBSDATA_D3
GND13
ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
GND15
TD0
TRST#
TDI
TMS
GND17
24.9_0402_1%
H_ PROCHOT#_D
130_0402_1%
H_ CPURST#_R
1
R45
1
R47
CLK_CPU_XDP
CLK_CPU_XDP#
2
+ VCCP
2 49.9_0402_1%
PM_EXTTS#0
68_0402_5%
2
@ 68_0402_5%
PM_EXTTS#1
1
R1
1
R3
2
2
H_ THERMDC
+3VS _THER
1 C4
0.1U_0402_16V4Z
2
15
+3VS
0112 Remove uninstall parts
F AN_PWM_R
2
10K_0201_5%
@ 2
10K_0201_5%
DP
VDD
PWM_IN
ADDR_SEL
6
7
51_0402_5%
H_THERMTRIP#
1
R 63
2
0_0201_5%
Add
REMOTE2+
DN2/DP3
15
REMOTE2-
TRIP_SET
14
SHDN_SEL
13
GND
12
ALERT#
PWM
11
SYS_SHDN#
TACH
10
SMDATA
Close to U2
16
DP2/DN3
SMB_DATA_S3
DN
17
R71
THERM_SCI#
R 62
9,10,11,13,24
1
R 59
2 H_THERM DA
2200P_0402_50V7K
1
C3
+3VS
XDP_TRST#
10K_0201_5%
10K_0201_5%
U2
Layout Note:Please these

resistors near Processor
11/06 Cancel REMOTE thermal sensor reserve.
+3VS
5
5
5
5
R34
1K_0201_5%
5
5
+ VCCP
XDP_RST#_R
R38
XDP_DB RESET#_R
R39
X DP_TDO
XDP_TRST#
XDP_TDI
XDP_TMS
1
1
1K_0201_5%
H _CPURST#
2
XDP _DBRESET#
2
0_0201_5%
2 P LT_RST#
0_0201_5%
Thermal Sensor EMC2113 with CPU PWM FAN

R50
68_0402_5%
+VCCP
100_0201_1%
R44 1
CFG4
CFG5
CFG6
CFG7
XDP_DBRESET#
12,14
PLT_RST#
12,15,21,22,23,31
GND
SM_RCOMP2
DDR Pullups
H _CATERR#
5
5
Add C119 between JP4 pin 37 and 41;

Add C120 close to R20.1
SM_RCOMP1
5
5
CFG2
CFG3
F AN_PWM_R 1
2
R 46
0_0201_5%
2
C2
@ 0.1U_0402_16V4Z
11/06 update
DDR3 Compensation Signals

2
5
5
CFG0
CFG1
CFG 10
CFG 11
XDP_RST#_R 1
R42
+3VS
1
R52
1
R56
1
R58
CFG8
CFG9
C ONN@
SAMTE_BSH-030-01-L-D-A
01/04 update for ESD
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
0.1U_0402_16V4Z
Processor Pullups
SM_RCOMP0
15
2 .1U_0402_16V7K
JP4
XDP _DBRESET#
X DP_TCK
2
R20
9,10
CPU XDP Connector
PM_PWRBTN#_R
PM_PWRBTN#_R 1
@ 1K_0201_5%
DRAMRST#
Q52A
2N7002DWH 2N SOT363-6
07/17 update
0112 Add test points
C6 1
XDP _PREQ#
XDP_PRDY#

07/17 update for value change back
@ 100K_0402_5%
T49 P AD
2
R 16
INTEL_AUBURNDALE_1288
R35
750_0402_1%
PECI
DDR3
Misc
to power; PU to VCCP at power side also

1 R 15
2 H_ PROCHOT#_D
H _PROCHOT#
0_0201_5%
N19
JTAG & MBP
15
2 H_PECI_ISO
0_0201_5%
Thermal
40
1 R 14
H_ PECI
1K_0402_5%
SM_DRAMRST#
15
+1.5V
R 1093
C LK_DP 13
CLK_DP# 13
COMP3
AC70
AD71
H_COM P2
SMCLK
R51
R55
FAN_PWM
30
C5
+5VS
2200P_0402_50V7K
2
H_COM P3
2.05K_0402_1%
15K_0402_5%
R54
10K_0201_5%
+3VS
J P2
1
1 R5
Misc
1 R2
20_0402_1%
Clocks
U1B
20_0402_1%
FAN_PWM_OUT
R61
T ACH
1
2
3
4
5
6
10K_0201_5% +5VS
SMB_CLK_S3
9,10,11,13,24
EMC2113-1-AP-TR QFN 16P
1
2
3
4
G5
G6
ACES_85205-04001
C ONN@
0ohm and 0.1u

D
Close to XDP
+ VCCP
X DP_TDO
1
2
R10
51_0402_5%
This shall place near XDP
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

Auburndale(1/5)-Thermal/XDP
Size D ocument Number

Cus tom LA -5251P
Dat e:
Rev
0.9

5
Sheet
of
47
U 1A
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_TX#[0]
DMI_TX#[1]
DMI_TX#[2]
DMI_TX#[3]
14
14
14
14
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
G17
M15
G13
J11
DMI_TX[0]
DMI_TX[1]
DMI_TX[2]
DMI_TX[3]
14
14
14
14
14
14
14
14
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_N0 L2
FDI_CTX_PRX_N1 N7
FDI_CTX_PRX_N2 M4
FDI_CTX_PRX_N3 P1
FDI_CTX_PRX_N4 N10
FDI_CTX_PRX_N5 R7
FDI_CTX_PRX_N6 U7
FDI_CTX_PRX_N7 W8
FDI_TX#[0]
FDI_TX#[1]
FDI_TX#[2]
FDI_TX#[3]
FDI_TX#[4]
FDI_TX#[5]
FDI_TX#[6]
FDI_TX#[7]
14
14
14
14
14
14
14
14
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P0 K1
FDI_CTX_PRX_P1 N5
FDI_CTX_PRX_P2 N2
FDI_CTX_PRX_P3 R2
FDI_CTX_PRX_P4 N9
FDI_CTX_PRX_P5 R8
FDI_CTX_PRX_P6 U6
FDI_CTX_PRX_P7 W10
FDI_TX[0]
FDI_TX[1]
FDI_TX[2]
FDI_TX[3]
FDI_TX[4]
FDI_TX[5]
FDI_TX[6]
FDI_TX[7]
14
14
FDI_FS Y NC0
FDI_FS Y NC1
FDI_FS Y N C0
FDI_FS Y N C1
AC7
AC9
FDI_FSYNC[0]
FDI_FSYNC[1]
14
FDI_ INT
FDI _INT
AB5
FDI_INT
14
14
FDI_LS Y NC0
FDI_LS Y NC1
FDI_LS Y NC0
FDI_LS Y NC1
AA1
AB2
FDI_LSYNC[0]
FDI_LSYNC[1]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
1 R65
2
750_0402_1%
MB_C_DP_AUXN
N40
L38
M32
D40
A38
G32
B33
B35
L30
A31
B32
L28
N26
M24
G21
J20
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
L40
N38
N32
B39
B37
H32
A34
D36
J30
B30
D33
N28
M25
N24
F21
L20
C9 03
2
MB_DP_AUXN
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
20
0.1U_0402_16V4Z
F40
J38
G34
M34
J28
G25
K24
B28
A27
B25
A24
B21
B19
B18 MB_C_DP_AUXP
B16
D15
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
U1E
+ VCCP
R8 01
7.5K_0402_1%
1
2
C 904
0.1U_0402_16V4Z
MB_DP_AUXP
CFG0 AL4
CFG1 AM2
CFG2 AK1
CFG3 AK2
CFG4 AK4
CFG5 AJ2
CFG6 AT2
CFG7 AG7
CFG8 AF4
CFG9 AG2
CF G10 AH1
CF G11 AC2
CF G12 AC4
CF G13 AE2
CF G14 AD1
CF G15 AF8
CF G16 AF6
CF G17 AB7
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CF G10
CF G11
CF G12
CF G13
CF G14
CF G15
CF G16
CF G17
CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]
CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]
CFG[16]
CFG[17]
W66
W64
T116 P AD
T117 P AD
RSVD34
RSVD35
AC69
AC71
T118 P AD
RSVD36
RSVD37
AA71
AA69
RSVD38
RSVD39
R66
R64
RSVD_NCTF[3]
RSVD_NCTF[4]
BT5
BR5
RSVD_NCTF[2]
RSVD_NCTF[1]
BV6
BV8
RSVD45
RSVD46
RSVD47
RSVD48
RSVD49
RSVD50
RSVD51
RSVD52
RSVD53
RSVD54
RSVD55
RSVD56
RSVD57
RSVD58
Q46A
2
2N7002DWH 2N SOT363-6
MB_DP_HPD
20
P AD T50
AU1
RSVD_TP[0]
R8 00
100K_0402_5%~D
C9 05
MB_C_DP_DATA0_N 1
2
MB_DP_DATA0_N
20
0.1U_0402_16V4Z
C8 58
MB_C_DP_DATA0_P 1
2
RSVD32
RSVD33
20
14
14
14
14
H17
K15
J13
F10
E XP_RBIAS
T4
T2
RSVD15
RSVD16
U1
V2
RSVD17
RSVD18
AV71
AW70
RSVD19
RSVD20
AY69
BB69
RSVD21
RSVD22
D8
B7
RSVD23
RSVD24
A10
B9
RSVD26
RSVD27
DMI_RX[0]
DMI_RX[1]
DMI_RX[2]
DMI_RX[3]
G40
G38
H34
P34
G28
H25
H24
D29
B26
D26
B23
D22
A20
D19
A17
B14
49.9_0402_1%
1 R64
2
F9
J6
K9
J2
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
E XP_ICOMPI
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
B12
A13
D12
B11
14
14
14
14
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RBIAS
DMI_RX#[0]
DMI_RX#[1]
DMI_RX#[2]
DMI_RX#[3]
PCI EXPRESS -- GRAPHICS
F7
J8
K8
J4
Intel(R) FDI
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI
14
14
14
14
MB_DP_DATA0_P
C5
A6
RSVD_NCTF[7]
RSVD_NCTF[8]
E3
F1
RSVD_NCTF[6]
RSVD_NCTF[5]
RESERVED
20
0.1U_0402_16V4Z
04/20 INTEL #418125 update
T119 P AD
T120 P AD
AV69
AK71
AN69
AP66
AH66
AK66
AR71
AM66
AK69
AU71
AT70
AR69
AU69
AT67
RSVD_TP[2]
RSVD_TP[1]
AP2
AN7
RSVD62
RSVD63
AV4
AU2
RSVD64
RSVD65
BE69
BE71
DC_TEST_BV71
DC_TEST_BV69
DC_TEST_BV68
DC_TEST_BV5
DC_TEST_BV3
DC_TEST_BV1
DC_TEST_BT71
DC_TEST_BT69
DC_TEST_BT3
DC_TEST_BT1
DC_TEST_BR71
DC_TEST_BR1
DC_TEST_E71
DC_TEST_E1
DC_TEST_C71
DC_TEST_C69
DC_TEST_C3
DC_TEST_A71
DC_TEST_A69
DC_TEST_A68
DC_TEST_A5
BV71
BV69
BV68
BV5
BV3
BV1
BT71
BT69
BT3
BT1
BR71
BR1
E71
E1
C71
C69
C3
A71
A69
A68
A5
T51 P AD
T52 P AD
VSS_NCTF2_R
VSS_NCTF6_R
8
8
VSS_NCTF1_R
VSS_NCTF7_R
8
8
CFG Straps for PROCESSOR

CFG0
R68
@ 3.01K_0402_1%
PCI-Express Configuration Select

1: Single PEG
CFG0
0: Bifurcation enabled
Not applicable for Clarksfield Processor
CFG3
R69
CFG3-PCI Express
1:
CFG3
0:
15
CFG4
D
R70
@ 3.01K_0402_1%
Static Lane Reversal

Normal Operation
Lane Numbers Reversed
-> 0, 14 ->1, .....
2 3.01K_0402_1%
ES1 sample need negative voltage

ES2 sample contact to GND
CFG4-Display Port Presence
1: Disabled; No Physical Display Port
attached to Embedded Display Port
CFG4
0: Enabled; An external Display Port
device is connected to the Embedded
Display Port
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

Auburndale(2/5)-DMI/PEG/FDI

Cus tom LA -5251P
Dat e:
Rev
0.9

5
Sheet
of
47
U1D
U1C
DDR_A _D[0..63]
DDR_A _D0
DDR_A _D1
DDR_A _D2
DDR_A _D3
DDR_A _D4
DDR_A _D5
DDR_A _D6
DDR_A _D7
DDR_A _D8
DDR_A _D9
DDR_ A_D10
DDR_ A_D11
DDR_ A_D12
DDR_ A_D13
DDR_ A_D14
DDR_ A_D15
DDR_ A_D16
DDR_ A_D17
DDR_ A_D18
DDR_ A_D19
DDR_ A_D20
DDR_ A_D21
DDR_ A_D22
DDR_ A_D23
DDR_ A_D24
DDR_ A_D25
DDR_ A_D26
DDR_ A_D27
DDR_ A_D28
DDR_ A_D29
DDR_ A_D30
DDR_ A_D31
DDR_ A_D32
DDR_ A_D33
DDR_ A_D34
DDR_ A_D35
DDR_ A_D36
DDR_ A_D37
DDR_ A_D38
DDR_ A_D39
DDR_ A_D40
DDR_ A_D41
DDR_ A_D42
DDR_ A_D43
DDR_ A_D44
DDR_ A_D45
DDR_ A_D46
DDR_ A_D47
DDR_ A_D48
DDR_ A_D49
DDR_ A_D50
DDR_ A_D51
DDR_ A_D52
DDR_ A_D53
DDR_ A_D54
DDR_ A_D55
DDR_ A_D56
DDR_ A_D57
DDR_ A_D58
DDR_ A_D59
DDR_ A_D60
DDR_ A_D61
DDR_ A_D62
DDR_ A_D63
AT8
AT6
BB5
BB9
AV7
AV6
BE6
BE8
BF11
BE11
BK5
BH13
BF9
BF6
BK7
BN8
BN11
BN9
BG17
BK15
BK9
BG15
BH17
BK17
BN20
BN17
BK25
BH25
BJ20
BH21
BG24
BG25
BJ40
BM43
BF47
BF48
BN40
BH43
BN44
BN47
BN48
BN51
BH53
BJ55
BH48
BJ48
BM53
BN55
BF55
BN57
BN65
BJ61
BF57
BJ57
BK64
BK61
BJ63
BF64
BB64
BB66
BJ66
BF65
AY64
BC70
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
10
10
10
D DR_A_BS0
D DR_A_BS1
D DR_A_BS2
BT38
BH38
BF21
SA_BS[0]
SA_BS[1]
SA_BS[2]
10
10
10
DD R_A_CAS#
DD R_A_RAS#
DDR_ A_WE#
BK43
BL38
BF38
SA_CAS#
SA_RAS#
SA_WE#
DDR SYSTEM MEMORY A
10
SA_CK[0]
SA_CK#[0]
SA_CKE[0]
BM34
BP35
BF20
M _CLK_DDR0 10
M _CLK_DDR#0 10
DDR_CKE0_DIMMA 10
SA_CK[1]
SA_CK#[1]
SA_CKE[1]
BK36
BH36
BK24
M _CLK_DDR1 10
M _CLK_DDR#1 10
DDR_CKE1_DIMMA 10
SA_CS#[0]
SA_CS#[1]
BH40
BJ47
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
SA_ODT[0]
SA_ODT[1]
BF43
BL47
M_ODT0
M_ODT1
SA_DM[0]
SA_DM[1]
SA_DM[2]
SA_DM[3]
SA_DM[4]
SA_DM[5]
SA_DM[6]
SA_DM[7]
BB10
BJ10
BM15
BN24
BG44
BG53
BN62
BH59
DD R_A_DM0
DD R_A_DM1
DD R_A_DM2
DD R_A_DM3
DD R_A_DM4
DD R_A_DM5
DD R_A_DM6
DD R_A_DM7
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
AY5
BJ7
BN13
BL21
BH44
BK51
BP58
BE62
DD R_A_DQS#0
DD R_A_DQS#1
DD R_A_DQS#2
DD R_A_DQS#3
DD R_A_DQS#4
DD R_A_DQS#5
DD R_A_DQS#6
DD R_A_DQS#7
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
AY7
BJ5
BL13
BN21
BK44
BH51
BM60
BE64
DDR _A_DQS0
DDR _A_DQS1
DDR _A_DQS2
DDR _A_DQS3
DDR _A_DQS4
DDR _A_DQS5
DDR _A_DQS6
DDR _A_DQS7
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
BT36
BP33
BV36
BG34
BG32
BN32
BK32
BJ30
BN30
BF28
BH34
BH30
BJ28
BF40
BN28
BN25
DDR_B _D0
DDR_B _D1
DDR_B _D2
DDR_B _D3
DDR_B _D4
DDR_B _D5
DDR_B _D6
DDR_B _D7
DDR_B _D8
DDR_B _D9
DDR_ B_D10
DDR_ B_D11
DDR_ B_D12
DDR_ B_D13
DDR_ B_D14
DDR_ B_D15
DDR_ B_D16
DDR_ B_D17
DDR_ B_D18
DDR_ B_D19
DDR_ B_D20
DDR_ B_D21
DDR_ B_D22
DDR_ B_D23
DDR_ B_D24
DDR_ B_D25
DDR_ B_D26
DDR_ B_D27
DDR_ B_D28
DDR_ B_D29
DDR_ B_D30
DDR_ B_D31
DDR_ B_D32
DDR_ B_D33
DDR_ B_D34
DDR_ B_D35
DDR_ B_D36
DDR_ B_D37
DDR_ B_D38
DDR_ B_D39
DDR_ B_D40
DDR_ B_D41
DDR_ B_D42
DDR_ B_D43
DDR_ B_D44
DDR_ B_D45
DDR_ B_D46
DDR_ B_D47
DDR_ B_D48
DDR_ B_D49
DDR_ B_D50
DDR_ B_D51
DDR_ B_D52
DDR_ B_D53
DDR_ B_D54
DDR_ B_D55
DDR_ B_D56
DDR_ B_D57
DDR_ B_D58
DDR_ B_D59
DDR_ B_D60
DDR_ B_D61
DDR_ B_D62
DDR_ B_D63
10
10
10
10
DDR _A_DM[0..7]
DDR_ A_DQS#[0..7]
DDR_A_M A0
DDR_A_M A1
DDR_A_M A2
DDR_A_M A3
DDR_A_M A4
DDR_A_M A5
DDR_A_M A6
DDR_A_M A7
DDR_A_M A8
DDR_A_M A9
DDR_A_MA 10
DDR_A_MA 11
DDR_A_MA 12
DDR_A_MA 13
DDR_A_MA 14
DDR_A_MA 15
DDR_B _D[0..63]
10
10
DDR_ A_DQS[0..7]
10
DDR_A_MA[0..15]
10
BA2
AW2
BD1
BE4
AY1
BC2
BF2
BH2
BG4
BG1
BR6
BR8
BJ4
BK2
BU9
BV10
BR10
BT12
BT15
BV15
BV12
BP12
BV17
BU16
BP15
BU19
BV22
BT22
BP19
BV19
BV20
BT20
BT48
BV48
BV50
BP49
BT47
BV52
BV54
BT54
BP53
BU53
BT59
BT57
BP56
BT55
BU60
BV59
BV61
BP60
BR66
BR64
BR62
BT61
BN68
BL69
BJ71
BF70
BG71
BC67
BK70
BK67
BD71
BD69
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
9
9
9
D DR_B_BS0
D DR_B_BS1
D DR_B_BS2
BV43
BV41
BV24
SB_BS[0]
SB_BS[1]
SB_BS[2]
9
9
9
DD R_B_CAS#
DD R_B_RAS#
DDR_ B_WE#
BU46
BT40
BT41
SB_CAS#
SB_RAS#
SB_WE#
SB_CK[0]
SB_CK#[0]
SB_CKE[0]
BU33
BV34
BT26
M _CLK_DDR2 9
M _CLK_DDR#2 9
DDR_CKE2_DIMMB
SB_CK[1]
SB_CK#[1]
SB_CKE[1]
BV38
BU39
BT24
M _CLK_DDR3 9
M _CLK_DDR#3 9
DDR_CKE3_DIMMB
SB_CS#[0]
SB_CS#[1]
BP46
BT43
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
9
9
SB_ODT[0]
SB_ODT[1]
BV45
BU49
M_ODT2
M_ODT3
SB_DM[0]
SB_DM[1]
SB_DM[2]
SB_DM[3]
SB_DM[4]
SB_DM[5]
SB_DM[6]
SB_DM[7]
BB4
BL4
BT13
BP22
BV47
BV57
BU65
BF67
DD R_B_DM0
DD R_B_DM1
DD R_B_DM2
DD R_B_DM3
DD R_B_DM4
DD R_B_DM5
DD R_B_DM6
DD R_B_DM7
9
9
DDR _B_DM[0..7]
DDR SYSTEM MEMORY - B
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
BE2 DD R_B_DQS#0
BM3 DD R_B_DQS#1
BU12 DD R_B_DQS#2
BT19 DD R_B_DQS#3
BT52 DD R_B_DQS#4
BV55 DD R_B_DQS#5
BU63 DD R_B_DQS#6
BG69 DD R_B_DQS#7
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
BD4
BN4
BV13
BT17
BT50
BU56
BV62
BJ69
DDR _B_DQS0
DDR _B_DQS1
DDR _B_DQS2
DDR _B_DQS3
DDR _B_DQS4
DDR _B_DQS5
DDR _B_DQS6
DDR _B_DQS7
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
BT34
BP30
BV29
BU30
BV31
BT33
BT31
BP26
BV27
BT27
BU42
BU26
BT29
BT45
BV26
BU23
DDR_B_M A0
DDR_B_M A1
DDR_B_M A2
DDR_B_M A3
DDR_B_M A4
DDR_B_M A5
DDR_B_M A6
DDR_B_M A7
DDR_B_M A8
DDR_B_M A9
DDR_B_MA 10
DDR_B_MA 11
DDR_B_MA 12
DDR_B_MA 13
DDR_B_MA 14
DDR_B_MA 15
DDR _B_DQS#[0..7]
DDR _B_DQS[0..7]
DDR_B_MA[0..15]
D
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

Auburndale(3/5)-DDR3

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
of
47
+GFX_CORE
+CP U_CORE
0112 change size

C
+ VCCP
10U_0805_6.3V6M
C49
22U_0805_6.3V6M
C48
C62
22U_0805_6.3V6M
C61
10U_0805_6.3V6M
C60
22U_0805_6.3V6M
C59
10U_0805_6.3V6M
11/13 update
04/29 Change C55,C56,C57 from

@47P_0402 to 1UF_0402 by HP.
11/13 update
+CP U_CORE
+C PU_CORE
0116 add
1U_0402_6.3V6K
1U_0402_6.3V6K
C6 12
1U_0402_6.3V6K
1U_0402_6.3V6K
C6 14
1U_0402_6.3V6K
C6 13
1U_0402_6.3V6K
C3 83
1U_0402_6.3V6K
1U_0402_6.3V6K
C5 34
1U_0402_6.3V6K
C5 33
C57
1U_0402_6.3V6K
C3 82
40
AN1
VTT_SELECT[1]
PROC_DPRSLPVR
F64
F63
VCC_SENSE
VSS_SENSE
VTT_SENSE
N13
VTT_SENSE
VSS_SENSE_VTT
R12
VSS_SENSE_VTT
IMVP_IMON
VCCSENSE
VSS SENSE
2
2
0_0201_5%
R73 1
1
R74
0_0201_5%
VTT0_11
VTT0_12
VTT0_13
VTT0_14
VTT0_15
VTT0_16
VTT0_17
VTT0_18
VTT0_19
VTT0_20
VTT0_21
VTT0_22
VTT0_23
VTT0_24
VTT0_25
VTT0_26
VTT0_27
VTT0_28
VTT0_29
VTT0_30
VTT0_31
VTT0_32
VTT0_33
VTT0_34
VTT0_35
VTT0_36
VTT0_37
VTT0_38
VTT0_39
VTT0_40
VTT0_41
VTT0_42
VTT0_1
VTT0_2
VTT0_3
VTT0_4
VTT0_5
VTT0_6
VTT0_7
VTT0_8
VTT0_9
VTT0_10
VTT0_43
VTT0_44
VTT0_45
VTT0_46
VTT0_47
VTT0_48
VTT0_49
VTT0_50
VTT0_51
VTT0_52
VTT0_53
VTT0_54
VTT0_55
VTT0_56
VTT0_57
VTT0_58
VTT0_59
VTT0_60
VTT0_61
VTT0_62
VTT0_63
VTT0_64
VTT0_65
VTT0_66
VTT0_67
VTT0_68
VTT0_69
VTT0_70
VTT0_71
VTT0_72
VTT0_73
+VCAP1
BD44
BD41
BD37
BB44
BB41
BB37
AY46
AY42
AY39
AW46
AW42
AW39
AU44
AU41
AU37
AR44
AR41
AR37
AN46
AN42
AN39
AL46
AL42
AL39
AK46
AK42
AK39
VCAP1_1
VCAP1_2
VCAP1_3
VCAP1_4
VCAP1_5
VCAP1_6
VCAP1_7
VCAP1_8
VCAP1_9
VCAP1_10
VCAP1_11
VCAP1_12
VCAP1_13
VCAP1_14
VCAP1_15
VCAP1_16
VCAP1_17
VCAP1_18
VCAP1_19
VCAP1_20
VCAP1_21
VCAP1_22
VCAP1_23
VCAP1_24
VCAP1_25
VCAP1_26
VCAP1_27
+C PU_CORE
Close to CPU
VCCSENSE
1
R75
1
R76
VSS SENSE
2
100_0402_1%
2
100_0402_1%
+1.8VS
10U_0805_6.3V6M
1
4.7U_0603_6.3V6K
1
C37
C 38
W39
W37
U37
R39
R37
VCCPLL1
VCCPLL2
VCCPLL3
VCCPLL4
VCCPLL5
+1.5VS_CPU_VDDQ
L32
2
1
0_0603_5%
+ VDDQ_CK
C 50
1U_0402_6.3V4Z
BB14
BB12
VDDQ_CK[1]
VDDQ_CK[2]
AW14
AW12
AU60
AU59
AU12
AR60
AR59
AR12
AN60
AN59
AN35
AN33
AN17
AN15
AN14
AN12
AM10
AL60
AL59
AL17
AL15
AL14
AL12
AK35
AK33
AF39
AF37
AF35
AF33
AF32
AF30
AD39
BF60
BF59
BD60
BD59
BB60
BB59
AY60
AW60
AW35
AW33
AD37
AD35
AD33
AD32
AD30
W35
W33
W32
W30
W28
W26
W24
W23
U35
U33
U32
U30
U28
U26
U24
U23
R35
R33
R32
R30
R28
R26
R24
R23
AY10 VTT0_72
AN9 VTT0_73
2
VTT0_72
VTT0_73
10/01 update
Change +VCAP0/+VCAP1/ MLCC Caps from
1U_0402 to 2.2U_0402 on SI-2B SV&LV Sku
SMT build.
+VCAP1
0112 add 7pcs Caps to follow Design guide

1
C68
2.2U_0402_6.3V4M
2
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
ISENSE
37
37
PSI#
A61
D61
D62
A62
B63
D64
D66
A41
40
40 VCCSENSE
40 VSSSENSE
2.2U_0402_6.3V4M2.2U_0402_6.3V4M
1
H_V ID0
H_V ID1
H_V ID2
H_V ID3
H_V ID4
H_V ID5
H_V ID6
F68
1PM_DPRSLP VR_R F66

R72
0_0201_5%
P ROC_DPRSLPVR
CPU CORE SUPPLY
+VCAP0
40 PSI#
H_V I D[0..6]
H_VTTVID1
40
1U_0402_6.3V6K
C3 81
C56
C 58
47P_0402_50V8J
C55
H_VTTVID1 = High, 1.05V
1.1V RAIL POWER
SENSE
LINES
POWER
+ VCCP
U 1F
H_VTTVID1 = Low, 1.1V
POWER
+VTT_DDR
10U_0805_6.3V6M
C47
11/13 update
11/27 update
L 31
0_0603_5%
10U_0805_6.3V6M
C46
+VCCP
+ VCCP
AD15
AD14
AD12
AB12
AA12
W17
W15
W14
W12
R15
VTT1_12
VTT1_13
VTT1_14
VTT1_15
VTT1_16
VTT1_17
VTT1_18
VTT1_19
VTT1_20
VTT1_21
AW32
AW30
AW28
AW26
AW24
AW23
AW21
AW19
AW17
AW15
+VCAP0
BD55
BD51
BD48
BB55
BB51
BB48
AY57
AY53
AY50
AW57
AW53
AW50
AU55
AU51
AU48
AR55
AR51
AR48
AN57
AN53
AN50
AL57
AL53
AL50
AK57
AK53
AK50
VCAP0_1
VCAP0_2
VCAP0_3
VCAP0_4
VCAP0_5
VCAP0_6
VCAP0_7
VCAP0_8
VCAP0_9
VCAP0_10
VCAP0_11
VCAP0_12
VCAP0_13
VCAP0_14
VCAP0_15
VCAP0_16
VCAP0_17
VCAP0_18
VCAP0_19
VCAP0_20
VCAP0_21
VCAP0_22
VCAP0_23
VCAP0_24
VCAP0_25
VCAP0_26
VCAP0_27
SENSE LINES
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
VCC_36
VCC_37
VCC_38
VCC_39
VCC_40
VCC_41
VCC_42
VCC_43
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52
VCC_53
VCC_54
VCC_55
VCC_56
VCC_57
VCC_58
VCC_59
VCC_60
VCC_61
VCC_62
VCC_63
VCC_64
VCC_65
VCC_66
VCC_67
VCC_68
VCC_69
VCC_70
VCC_71
VCC_72
VCC_73
VCC_74
VCC_75
VCC_76
VCC_77
VCC_78
VCC_79
VCC_80
VCC_81
VCC_82
VCC_83
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
CPU VIDS
VCAP2_1
VCAP2_2
VCAP2_3
VCAP2_4
VCAP2_5
VCAP2_6
VCAP2_7
VCAP2_8
VCAP2_9
VCAP2_10
VCAP2_11
VCAP2_12
VCAP2_13
VCAP2_14
VCAP2_15
VCAP2_16
VCAP2_17
VCAP2_18
VCAP2_19
AF57
AF55
AF53
AF51
AF50
AF48
AF46
AF44
AF42
AF41
AD55
AD51
AD48
AD44
AD41
AB55
AB51
AB48
AB44
AB41
AA55
AA51
AA48
AA44
AA41
W55
W51
W48
W44
W41
U55
U51
U48
U44
U41
R55
R51
R48
R44
R41
P60
N55
N51
N48
N44
N42
M60
M51
M44
L55
K60
K51
K44
J55
H60
H51
H44
G60
G55
G51
G44
F55
E60
E57
E53
E50
E46
E42
D59
D57
D55
D54
D52
D50
D48
D47
D45
D43
B60
B56
B53
B49
B46
B42
A57
A54
A50
A47
A43
1.8V
1U_0402_6.3V4Z
C36
1U_0402_6.3V4Z
C35
1U_0402_6.3V4Z
C34
1U_0402_6.3V4Z
C33
1U_0402_6.3V4Z
C32
AK62
AK60
AK59
AH60
AH59
AF60
AF59
AD60
AD59
AB60
AB59
AA60
AA59
W60
W59
U60
U59
R60
R59
1U_0402_6.3V4Z
C 44
VTT0_DDR
VTT0_DDR[1]
VTT0_DDR[2]
VTT0_DDR[3]
VTT0_DDR[4]
VTT0_DDR[5]
VTT0_DDR[6]
VTT0_DDR[7]
VTT0_DDR[8]
VTT0_DDR[9]
+VCAP2
1U_0402_6.3V4Z
C 43
BU40
BU35
BU28
BN38
BM25
BL30
BJ38
BH32
BH28
BG43
BF16
BF15
BD35
BD33
BD32
BD30
BD28
BD26
BD24
BD23
BD21
BD19
BD17
BD15
BB35
BB33
BB32
BB30
BB28
BB26
BB24
BB23
BB21
BB19
BB17
BB15
1U_0402_6.3V4Z
C 42
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21
VDDQ22
VDDQ23
VDDQ24
VDDQ25
VDDQ26
VDDQ27
VDDQ28
VDDQ29
VDDQ30
VDDQ31
VDDQ32
VDDQ33
VDDQ34
VDDQ35
VDDQ36
C24
1U_0402_6.3V4Z
11/13 update
@ 4.7K_0201_5% 1
2 R7 05
+ VCCP
AH69
GFXVR_EN 42
AL71
GFXVR_DPRSLPVR 42
AL69
GFXVR_IMON 42 +1.5VS_CPU_VDDQ
GFX_VR_EN
GFX_DPRSLPVR
GFX_IMON
C23
1U_0402_6.3V4Z
0116 add
C27
22U_0805_6.3V6M
VTT1_1
VTT1_2
VTT1_3
VTT1_4
VTT1_5
VTT1_6
VTT1_7
VTT1_8
VTT1_9
VTT1_10
VTT1_11
PEG & DMI
C31
10U_0805_6.3V6M
C30
@ 10U_0805_6.3V6M
C29
22U_0805_6.3V6M
C28
10U_0805_6.3V6M
W21
W19
U21
U19
U17
U15
U14
U12
R21
R19
R17
42
42
42
42
42
42
42
C22
1U_0402_6.3V4Z
+ VCCP
GFXVR_VID_0
GFXVR_VID_1
GFXVR_VID_2
GFXVR_VID_3
GFXVR_VID_4
GFXVR_VID_5
GFXVR_VID_6
C26
22U_0805_6.3V6M
0116 add
AF71
AG67
AG70
AH71
AN71
AM67
AM70
GFX_VID[0]
GFX_VID[1]
GFX_VID[2]
GFX_VID[3]
GFX_VID[4]
GFX_VID[5]
GFX_VID[6]
C25
330U_B2_2.5VM_R15M
VCC_AXG_SENSE 42
VSS_AXG_SENSE 42
C21
1U_0402_6.3V4Z
AF12
AF10
VAXG_SENSE
VSSAXG_SENSE
C20
1U_0402_6.3V4Z
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
GRAPHICS
C2 21
1U_0402_6.3V4Z
C2 17
1U_0402_6.3V4Z
C2 13
1U_0402_6.3V4Z
C3 80
1U_0402_6.3V4Z
C2 18
1U_0402_6.3V4Z
C2 14
1U_0402_6.3V4Z
C2 19
1U_0402_6.3V4Z
C2 20
1U_0402_6.3V4Z
C2 15
1U_0402_6.3V4Z
C2 16
1U_0402_6.3V4Z
C1 79
1U_0402_6.3V4Z
C2 12
1U_0402_6.3V4Z
AN32
AN30
AN28
AN26
AN24
AN23
AN21
AN19
AL32
AL30
AL28
AL26
AL24
AL23
AL21
AL19
AK14
AK12
AJ10
AH14
AH12
AF28
AF26
AF24
AF23
AF21
AF19
AF17
AF15
AF14
AD28
AD26
AD24
AD23
AD21
AD19
AD17
GRAPHICS VIDs
1U_0402_6.3V4Z
U1H
U1G
- 1.5V RAILS
2 GFXVR_EN
4.7K_0201_5%
1
R7 00
DDR3
09/22 update
POWER
C 974
330U_V_2VM_R6M
C 973
330U_V_2VM_R6M
10U_0805_6.3V6M
10U_0805_6.3V6M
1U_0402_6.3V4Z
C19
C18
C17
C16 1
Follow SCH check list

1
1
C69
1
C70
1
C 71
2.2U_0402_6.3V4M2.2U_0402_6.3V4M
1
C72
2
1
C93
1
C1 14
1
C1 13
2.2U_0402_6.3V4M2.2U_0402_6.3V4M
1
C 94
2
1
C92
1
C 140
C1 15
C63
2.2U_0402_6.3V4M
2
2
2 0_0402_5%
2 0_0402_5%
1
1
+VCCP
04/28 Change P/N from SD034000080 to

SD028000080
0112 add 7pcs Caps to follow Design guide
2.2U_0402_6.3V4M
1
R77
R78
2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M
1
C64
1
C65
1
C 66
1
C67
1
C86
1
C89
1
C88
2.2U_0402_6.3V4M2.2U_0402_6.3V4M
1
C 87
2
1
C85
1
C91
C90
2
+ VCCP
+CP U_CORE
1U_0402_6.3V6K
C6 51
1U_0402_6.3V6K
C6 53
1U_0402_6.3V6K
C6 52
1U_0402_6.3V6K
C6 48
1U_0402_6.3V6K
C6 50
1U_0402_6.3V6K
C6 49
1U_0402_6.3V6K
C6 47
1U_0402_6.3V6K
C6 44
1U_0402_6.3V6K
C6 46
1U_0402_6.3V6K
C6 45
1U_0402_6.3V6K
C6 17
1U_0402_6.3V6K
C6 43
1U_0402_6.3V6K
C6 23
1U_0402_6.3V6K
C6 16
1U_0402_6.3V6K
C6 15
C 54
47P_0402_50V8J
C 53
47P_0402_50V8J
C 52
47P_0402_50V8J
C 51
47P_0402_50V8J
2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M
0116 add
2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M2.2U_0402_6.3V4M
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
3
Title

Auburndale(4/5)-PWR

Cus tom LA -5251P
Dat e:
Rev
0.9

5
Sheet
of
47
0112 Add to follow design guide
+ VCCP
CPU CORE
U 1I
2
1U_0402_6.3V6K
1
1
C 304
1U_0402_6.3V6K 1U_0402_6.3V6K
1
C3 03
1
C3 02
1
C1 92
C 305
1
C 510
1
C 509
1
C5 08
1
C3 07
1
C5 12
C 511
SV@
1
1
+
2
05/06 update to change

C95,C96,C97,C98 from
SGA00002X00(330U_7mR) to
SGA00004200(470U_4.5mR)
1- SV BGA 4x470uF bulk on C95,C96,C97,C98

2- LV BGA 3x330uF 9mR (SGA20331E10) bulk on C96,C97,C98
Under cavity
C6 28
C1 10
22U_0805_6.3V6M
1
C6 36
Under cavity
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
BGA Ball Cracking Prevention and Detection

C
+3VS
+3VS
R79
R80
3
CRACK_BGA
17,30
100K_0201_5%
2
CRACK_BGA
100K_0201_5%
Q3A
2N7002DW-T/R7_SOT363-6
Q3B
2
5
2N7002DW-T/R7_SOT363-6
4
VSS_NCTF1_R
VSS_NCTF2_R
+3VS
+3VS
CRACK_BGA
R81
R82
100K_0201_5%
100K_0201_5%
VSS_NCTF6_R
2008/09/15
Deciphered Date
2010/12/31
3
VSS_NCTF7_R
Compal Secret Data
Q4B
2N7002DW-T/R7_SOT363-6
Q4A
2N7002DW-T/R7_SOT363-6
CRACK_BGA
3
C1 09
22U_0805_6.3V6M
C5 13
Issued Date
C1 08
SV@22U_0805_6.3V6M
C1 07
22U_0805_6.3V6M
C 515
2
C1 06
SV@22U_0805_6.3V6M
C 618
2
C1 05
22U_0805_6.3V6M
C6 19
2
1U_0402_6.3V6K 1U_0402_6.3V6K
C1 04
SV@22U_0805_6.3V6M
C1 03
SV@22U_0805_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K
C 98
470U_D2_2VM_R4.5M
2
1U_0402_6.3V6K 1U_0402_6.3V6K
C 97
470U_D2_2VM_R4.5M
1
+
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
1U_0402_6.3V6K
Inside cavity
1
C 306
C84
22U_0805_6.3V6M
1U_0402_6.3V6K 1U_0402_6.3V6K
C83
22U_0805_6.3V6M
C82
22U_0805_6.3V6M
C 201
2
C81
22U_0805_6.3V6M
C80
22U_0805_6.3V6M
1
C 190
C79
22U_0805_6.3V6M
1
C1 41
C78
22U_0805_6.3V6M
1
C1 91
C77
22U_0805_6.3V6M
C1 42
C76
22U_0805_6.3V6M
C 189
1U_0402_6.3V6K
2
C75
22U_0805_6.3V6M
A40
A36
A33
A29
A26
A22
A19
A15
A12
A8
B62
B58
B55
B51
B48
B44
A59
A55
A52
A48
A45
AA17
AA15
AA14
AA4
W69
W62
W57
W53
W50
W46
W42
W6
W1
V70
U64
U62
U57
U53
U50
U46
U42
U39
U9
U4
T1
R70
R62
R57
R53
R50
R46
R42
R5
P4
N63
N57
N53
N50
N46
N30
N21
N15
M53
M42
M36
M1
L70
L57
L48
L47
L13
K64
K53
K43
K36
K34
K32
K25
K17
K11
K6
K4
J65
J57
J48
J47
J40
J9
H53
H43
H36
H1
G70
G57
G53
G48
G47
G43
G30
G24
G20
G15
F61
F48
F47
F28
C1 02
22U_0805_6.3V6M
VSS
VSS404
VSS405
VSS406
VSS407
VSS408
VSS409
VSS410
VSS411
VSS412
VSS413
VSS393
VSS394
VSS395
VSS396
VSS397
VSS398
VSS399
VSS400
VSS401
VSS402
VSS403
VSS288
VSS289
VSS290
VSS291
VSS292
VSS293
VSS294
VSS295
VSS296
VSS297
VSS298
VSS299
VSS300
VSS301
VSS302
VSS303
VSS304
VSS305
VSS306
VSS307
VSS308
VSS309
VSS310
VSS311
VSS312
VSS313
VSS314
VSS315
VSS316
VSS317
VSS318
VSS319
VSS320
VSS321
VSS322
VSS323
VSS324
VSS325
VSS326
VSS327
VSS328
VSS329
VSS330
VSS331
VSS332
VSS333
VSS334
VSS335
VSS336
VSS337
VSS338
VSS339
VSS340
VSS341
VSS342
VSS343
VSS344
VSS345
VSS346
VSS347
VSS348
VSS349
VSS350
VSS351
VSS352
VSS353
VSS354
VSS355
VSS356
VSS357
VSS358
VSS359
VSS360
VSS361
VSS362
VSS363
VSS364
VSS365
VSS366
VSS367
VSS368
VSS369
VSS370
VSS371
VSS372
VSS373
C 96
470U_D2_2VM_R4.5M
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VSS223
VSS224
VSS225
VSS226
VSS227
VSS228
VSS229
VSS230
VSS231
VSS232
VSS233
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS287
VSS374
VSS375
VSS376
VSS377
VSS378
VSS379
VSS380
VSS381
VSS382
VSS383
VSS384
VSS385
VSS386
VSS387
VSS388
VSS389
VSS390
VSS391
VSS392
VSS415
+CP U_CORE
1U_0402_6.3V6K
C74
22U_0805_6.3V6M
AH53
AH51
AH50
AH48
AH46
AH44
AH42
AH41
AH39
AH37
AH35
AH33
AH32
AH30
AH28
AH26
AH24
AH23
AH21
AH19
AH17
AH15
AH4
AG64
AG9
AG6
AF69
AF62
AF1
AE70
AE64
AD62
AD57
AD53
AD50
AD46
AD42
AD4
AC67
AC64
AC10
AC5
AC1
AB70
AB62
AB57
AB53
AB50
AB46
AB42
AB39
AB37
AB35
AB33
AB32
AB30
AB28
AB26
AB24
AB23
AB21
AB19
AB17
AB15
AB14
AB9
AA66
AA64
AA62
AA57
AA53
AA50
AA46
AA42
AA39
AA37
AA35
AA33
AA32
AA30
AA28
AA26
AA24
AA23
AA21
AA19
F20
F4
E37
E33
E30
E16
E12
D41
D38
D34
D31
D27
D24
D20
D17
D13
D10
D6
B65
B40
1U_0402_6.3V6K 1U_0402_6.3V6K
C1 01
22U_0805_6.3V6M
VSS
U1J
C 95
SV@470U_D2_2VM_R4.5M
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
AY24
AY23
AY21
AY19
AY17
AY15
AY14
AY12
AY8
AY4
AW67
AW62
AW59
AW55
AW51
AW48
AW44
AW41
AW37
AV9
AV1
AU70
AU62
AU57
AU53
AU50
AU46
AU42
AU39
AU35
AU33
AU32
AU30
AU28
AU26
AU24
AU23
AU21
AU19
AU17
AU15
AU14
AU4
AT64
AT10
AR62
AR57
AR53
AR50
AR46
AN51
AN48
AN44
AN41
AN37
AN5
AN4
AM64
AM8
AL62
AL55
AL51
AL48
AL44
AL41
AL37
AL35
AL33
AL1
AK70
AK64
AK55
AK51
AK48
AK44
AK41
AK37
AK32
AK30
AK28
AK26
AK24
AK23
AK21
AK19
AK17
AK15
AJ70
AH62
AH57
AH55
BV66
BV64
BT68
BR69
BR68
BR3
BN71
BN1
BL71
BL1
R14
H71
F71
E69
E68
A66
A64
E5
C68
C73
SV@22U_0805_6.3V6M
BU62
BU58
BU55
BU51
BU48
BU44
BU37
BU32
BU25
BU21
BU18
BU14
BU11
BU7
BP42
BN64
BN6
BM70
BM51
BM44
BM32
BM24
BM17
BL57
BL55
BL48
BL40
BL28
BL20
BK63
BK60
BK53
BK34
BK10
BJ64
BJ21
BJ9
BJ1
BH70
BH57
BH55
BH47
BH24
BH20
BH15
BG51
BG36
BF62
BF30
BF13
BF8
BE70
BE65
BE9
BE1
BD57
BD53
BD50
BD46
BD42
BD39
BD14
BB71
BB62
BB57
BB53
BB50
BB46
BB42
BB39
BB7
BB1
BA70
AY71
AY66
AY62
AY59
AY55
AY51
AY48
AR42
AR39
AR35
AR33
AR32
AR30
AR28
AR26
AR24
AR23
AR21
AR19
AR17
AR15
AR14
AR4
AR1
AP70
AP64
AN62
AN55
AY44
AY41
AY37
AY35
AY33
AY32
AY30
AY28
AY26
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS187
VSS188
VSS189
VSS190
VSS191
VSS192
VSS193
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS200
VSS201
VSS202
VSS203
VSS204
VSS205
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
Title

Auburndale(5/5)-GND/Bypass

Cus tom LA -5251P
Dat e:
Rev
0.9

5
Sheet
of
47
DDR3 SO-DIMM B
+1.5V
+1.5V
+1.5V
1
3A@ 1.5V
+V _D DR_CPU_REF
DDR_B _D2
DDR_B _D3
DDR_B _D8
DDR_B _D9
DD R_B_DQS#1
DDR _B_DQS1
DDR_ B_D10
DDR_ B_D11
DDR_ B_D16
DDR_ B_D17
DD R_B_DQS#2
DDR _B_DQS2
DDR_ B_D18
DDR_ B_D19
DDR_ B_D24
DDR_ B_D25
DD R_B_DM3
DDR_ B_D26
DDR_ B_D27
DDR_CKE2_DIMMB
DDR_CKE2_DIM MB
D DR_B_BS2
D DR_B_BS2
DDR_B_MA 12
DDR_B_M A9
DDR_B_MA8
DDR_B_M A5
DDR_B_M A3
DDR_B_M A1
M _ CLK_DDR2
M _CLK_DDR#2
M _CLK_DDR2
M _CLK_DDR#2
D DR_B_BS0
DDR_B_MA 10
D DR_B_BS0
6
6
DDR_ B_WE#
DDR _B_CAS#
DDR _B_WE#
DD R_B_CAS#
DDR_CS3_DIMMB#
DDR_B_MA 13
DDR_CS3_DIMM B#
6
6
DDR_ B_D34
DDR_ B_D35
DDR_ B_D40
DDR_ B_D41
DD R_B_DM5
DDR_ B_D42
DDR_ B_D43
DDR_ B_D48
DDR_ B_D49
DD R_B_DQS#6
DDR _B_DQS6
DDR_ B_D50
DDR_ B_D51
DDR_ B_D56
DDR_ B_D57
DD R_B_DM7
DDR_ B_D20
DDR_ B_D21
DD R_B_DM2
DDR_ B_D22
DDR_ B_D23
DDR _B_DQS#[0..7]
DDR_B _D[0..63]
DDR _B_DM[0..7]
DDR _B_DQS[0..7]
DDR_B_MA[0..15]
DDR_ B_D28
DDR_ B_D29
DD R_B_DQS#3
DDR _B_DQS3
DDR_ B_D30
DDR_ B_D31
DDR_CKE3_DIM MB
DDR_CKE3_DIMMB
6
B
DDR_B_MA 15
DDR_B_MA 14
DDR_B_MA11
DDR_B_M A7
DDR_B_MA6
DDR_B_M A4
DDR_B_M A2
DDR_B_M A0
M _CLK_DDR3
M _CLK_DDR#3
M _CLK_DDR3 6
M_CLK_DDR#3 6
D DR_B_BS1
DD R_B_RAS#
DDR_B_BS1 6
DD R_B_RAS# 6
DDR_CS2_DIMM B#
M _ODT2
M _ODT3
DDR_CS2_DIMMB#
M_ODT2 6
M_ODT3
6
+VREF_CA
R94
DDR_ B_D36
DDR_ B_D37
DD R_B_DM4
DDR_ B_D38
DDR_ B_D39
DDR_ B_D44
DDR_ B_D45
+V _D DR_CPU_REF
2 0_0402_5%
DD R_B_DQS#5
DDR _B_DQS5
DDR_ B_D46
DDR_ B_D47
DDR_ B_D52
DDR_ B_D53
JP3
S MB_DATA_S3
SMB _CLK_S3
DD R_B_DM6
3
2
1
3
2
1
G2
G1
Layout Note:
Place near JDIMB1
5
4
Layout Note:
Place near JDIMB1
ACES_85204-03001
C ONN@
DDR_ B_D54
DDR_ B_D55
DDR_ B_D60
DDR_ B_D61
For ME/AMT debug
+0.75VS
+1.5V
DD R_B_DQS#7
DDR _B_DQS7
10U_0805_6.3V6M
C1 35
1U_0402_6.3V6K
1U_0402_6.3V6K
C1 34
C1 33
1U_0402_6.3V6K
C1 32
1U_0402_6.3V6K
0. 65A@0.75V
FOX_AS0A626-U4SN-7F~D
C ONN@
Compal Secret Data
Issued Date
Bottom Side H:5.2mm
2008/09/15
Deciphered Date
2010/12/31
Wait update the symbol for correct (LTCX001HL00)

1
C1 31
C1 18
330U_B2_2.5VM_R15M
+0.75VS
C 130
0.1U_0402_16V4Z
PM_EXTTS#1_R 4,10
SMB_DATA_S3 4,10,11,13,24
SMB_CLK_S3 4,10,11,13,24
C 129
0.1U_0402_16V4Z
PM_EXTTS#1_R
S MB_DATA_S3
SMB _CLK_S3
C 128
0.1U_0402_16V4Z
DDR_ B_D62
DDR_ B_D63
C 127
0.1U_0402_16V4Z
BOSS1
BOSS2
4 ,10
C 126
10U_0603_6.3V6M
GND1
GND2
206
208
DRAMRST#
DDR_ B_D14
DDR_ B_D15
C 125
10U_0603_6.3V6M
205
207
DD R_B_DM1
DRAMRST#
C 124
10U_0603_6.3V6M
R 86
1K_0402_1%
DDR_ B_D12
DDR_ B_D13
C 123
10U_0603_6.3V6M
10K_0201_5%
R96
DDR_B _D6
DDR_B _D7
C 122
10U_0603_6.3V6M
C 137
0.1U_0402_16V4Z
C 136
2.2U_0402_6.3V6M
+3VS
D
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
+V _D DR_CPU_REF
DD R_B_DQS#0
DDR _B_DQS0
C 121
10U_0603_6.3V6M
DDR_ B_D58
DDR_ B_D59
1 R 95
2
10K_0201_5%
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
R 83
1K_0402_1%
DDR_B _D4
DDR_B _D5
C 117
2.2U_0805_16V4Z
DD R_B_DQS#4
DDR _B_DQS4
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
C 116
0.1U_0402_16V4Z
DDR_ B_D32
DDR_ B_D33
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
DD R_B_DM0
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
C 112
2.2U_0805_16V4Z
C 111
0.1U_0402_16V4Z
2
A
DDR_B _D0
DDR_B _D1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
JDIMB1
Title

DDRIII-SODIMM SLOT1

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
of
47
DDR3 SO-DIMM A
+1.5V
+1.5V
3A@ 1.5V
JDIMA1
DDR_A _D8
DDR_A _D9
DD R_A_DQS#1
DDR _A_DQS1
DDR_ A_D10
DDR_ A_D11
DDR_ A_D16
DDR_ A_D17
DD R_A_DQS#2
DDR _A_DQS2
DDR_ A_D18
DDR_ A_D19
DDR_ A_D24
DDR_ A_D25
DD R_A_DM3
DDR_ A_D26
DDR_ A_D27
DDR_CKE0_DIM MA
DDR_CKE0_DIMMA
6
D DR_A_BS2
D DR_A_BS2
DDR_A_MA 12
DDR_A_M A9
DDR_A_M A8
DDR_A_M A5
DDR_A_M A3
DDR_A_M A1
6
M _CLK_DDR0
M _CLK_DDR#0
6
6
6
6
6
M _CLK_DDR0
M _CLK_DDR#0
DDR_A_MA 10
D DR_A_BS0
D DR_A_BS0
DDR _A_WE#
DD R_A_CAS#
DDR_ A_WE#
DD R_A_CAS#
DDR_A_MA 13
DDR_CS1_DIMM A#
DDR_CS1_DIMMA#
DDR_ A_D34
DDR_ A_D35
DDR_ A_D40
DDR_ A_D41
DD R_A_DM5
DDR_ A_D42
DDR_ A_D43
DDR_ A_D48
DDR_ A_D49
DD R_A_DQS#6
DDR _A_DQS6
DDR_ A_D50
DDR_ A_D51
DDR_ A_D56
DDR_ A_D57
+V _ DDR_CPU_REF_A
DD R_A_DM2
DDR_ A_D22
DDR_ A_D23
R 1095
DDR_ A_D28
DDR_ A_D29
1K_0402_1%
DD R_A_DQS#3
DDR _A_DQS3
DDR_ A_D30
DDR_ A_D31
Place R1094,R1095 close to JDIMA1 pin1 with C138,C139

4/24 New add R1094, R1095, R1096 and the Vref
circuit for DIMM A Ref Voltage.
DDR_CKE1_DIM MA
DDR_CKE1_DIMMA
DDR_A_MA 15
DDR_A_MA 14
DDR_A_MA11
DDR_A_M A7
DDR_A_MA6
DDR_A_M A4
DDR_A_M A2
DDR_A_M A0
M _CLK_DDR1
M _CLK_DDR#1
D DR_A_BS1
DD R_A_RAS#
DDR_CS0_DIMM A#
M _ODT0
M _ODT1
M _CLK_DDR1 6
M_CLK_DDR#1 6
DDR_A_BS1 6
DD R_A_RAS# 6
DDR_CS0_DIMMA#
M_ODT0 6
M_ODT1
6
+VREF_CA_A
+VREF_CA
DDR_ A_D36
DDR_ A_D37
DD R_A_DM4
DDR_ A_D38
DDR_ A_D39
Top Side H:4mm
Wait update the symbol for correct (LTCX001HH00)
+V _DDR_CPU_REF_A
R 1096 1
2 0_0402_5%
Place R1096 close to JDIMA1 pin126 with C143,C144

C
DDR_ A_D44
DDR_ A_D45
DD R_A_DQS#5
DDR _A_DQS5
DDR_ A_D46
DDR_ A_D47
Layout Note:
Place near JDIMA1
DDR_ A_D52
DDR_ A_D53
Layout Note:
Place near JDIMA1
DD R_A_DM6
DDR_ A_D54
DDR_ A_D55
+0.75VS
+1.5V
DDR_ A_D60
DDR_ A_D61
0. 65A@0.75V
2
PM_EXTTS#1_R 4 ,9
SMB_DATA_S3 4,9,11,13,24
SMB_CLK_S3 4,9,11,13,24
+0.75VS
FOX_AS0A626-U2SN-7F
C ONN@
Compal Secret Data
2008/09/15
Deciphered Date
2010/12/31
2
Issued Date
C1 60
1U_0402_6.3V6K
PM_EXTTS#1_R
S MB_DATA_S3
SMB _CLK_S3
C1 59
1U_0402_6.3V6K
DDR_ A_D62
DDR_ A_D63
C1 58
1U_0402_6.3V6K
DD R_A_DQS#7
DDR _A_DQS7
C1 57
1U_0402_6.3V6K
R 1094
1K_0402_1%
DDR_ A_D20
DDR_ A_D21
C1 56
0.1U_0402_16V4Z
206
208
DDR_ A_D14
DDR_ A_D15
C1 55
0.1U_0402_16V4Z
GND2
BOSS2
4,9
C1 54
0.1U_0402_16V4Z
R 105
10K_0201_5%
+1.5V
+V _ DDR_CPU_REF_A
DRAMRST#
C1 53
0.1U_0402_16V4Z
GND1
BOSS1
DD R_A_DM1
DRAMRST#
C1 52
10U_0603_6.3V6M
205
207
DDR_ A_D12
DDR_ A_D13
C1 51
10U_0603_6.3V6M
DDR_A _D6
DDR_A _D7
C1 50
10U_0603_6.3V6M
DDR_A_MA[0..15]
C1 49
10U_0603_6.3V6M
C1 62
0.1U_0402_16V4Z
+3VS
C1 61
2.2U_0402_6.3V6M
DDR _A_DQS#[0..7]
C1 48
10U_0603_6.3V6M
DDR_ A_D58
DDR_ A_D59
1 R1 04
2
10K_0201_5%
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
DDR_ A_DQS[0..7]
C1 47
10U_0603_6.3V6M
DD R_A_DM7
CKE1
VDD
A15
A14
VDD
A11
A7
VDD
A6
A4
VDD
A2
A0
VDD
CK1
CK1#
VDD
BA1
RAS#
VDD
S0#
ODT0
VDD
ODT1
NC
VDD
VREF_CA
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
EVENT#
SDA
SCL
VTT
DD R_A_DQS#0
DDR _A_DQS0
C 144
2.2U_0805_16V4Z
DD R_A_DQS#4
DDR _A_DQS4
CKE0
VDD
NC
BA2
VDD
A12/BC#
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0#
VDD
A10/AP
BA0
VDD
WE#
CAS#
VDD
A13
S1#
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT
DDR_A _D4
DDR_A _D5
C 143
0.1U_0402_16V4Z
DDR_ A_D32
DDR_ A_D33
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
DDR_A _D2
DDR_A _D3
VSS
DQ4
DQ5
VSS
DQS0#
DQS0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
RESET#
VSS
DQ14
DQ15
VSS
DQ20
DQ21
VSS
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
DD R_A_DM0
VREF_DQ
VSS
DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS
DDR_A _D[0..63]
DDR _A_DM[0..7]
DDR_A _D0
DDR_A _D1
1
C1 39
C1 38
0.1U_0402_16V4Z
2.2U_0805_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
6
6
+V _ DDR_CPU_REF_A
Title

DDRIII-SODIMM SLOT2
Size
D ocument Number
Rev
0.9
L A-5251P
Dat e:

5
Sheet
10
of
47
+3VS_CK505_G
+3VS_CK505
U6
CLK_BUF_DOT96
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_DOT96#
13
13
2 0_0201_5%
2 0_0201_5%
+3VS_CK505
CL K_BUF_CKSSCD R1 09 1
CL K_BUF_CKSSCD# R1 11 1
CL K_BUF_CKSSCD
CL K_BUF_CKSSCD#
13
13
R1 06 1
R1 08 1
CLK_DMI
CLK_DMI#
CLK_DMI
CLK_DMI#
R1 13 1
R1 14 1
2 0_0201_5%
2 0_0201_5%
2 0_0201_5%
2 0_0201_5%
+1.05VS_CK505
1
2
3
4
5
6
7
8
L_CLK_BUF_DOT96
L_CLK_BUF_DOT96#
VDD_DOT
VSS_DOT
DOT_96
DOT_96#
VDD_27
27MHZ
27MHZ_SS
VSS_27
9
10
11
12
13
14
15
16
L _CLK_BUF_CKSSCD
L_CLK_BUF_CKSSCD#
L_CLK_DMI
L_CLK_DMI#
CPU_S TOP#
VSS_SATA
SRC_1/SATA
SRC_1#/SATA#
VSS_SRC
SRC_2
SRC_2#
VDD_SRC_IO
CPU_STOP#
SCL
SDA
REF_0/CPU_SEL
VDD_REF
XTAL_IN
XTAL_OUT
VSS_REF
CKPWRGD/PD#
32
31
30
29
28
27
26
25
VDD_CPU
CPU_0
CPU_0#
VSS_CPU
CPU_1
CPU_1#
VDD_CPU_IO
VDD_SRC
24
23
22
21
20
19
18
17
TGND
13
13
SMB _CLK_S3
S MB_DATA_S3
R EF_0/CPU_SEL
R 107 1
2 33_0402_5%
CLK _XTAL_IN
CLK_XTAL_OUT
SMB_CLK_S3 4,9,10,13,24
SMB_DATA_S3 4,9,10,13,24
CLK_14M_PCH 13
CLK_14M_PCH
CK _P WRGD
R _CLK_BUF_BCLK
R_CLK_BUF_BCLK#
R 110 1
R 112 1
C1 63
@ 10P_0402_50V8C
2 0_0201_5%
2 0_0201_5%
CLK_BUF_BCLK
CLK_BUF_BCLK#
CLK_BUF_BCLK 13
CLK_BUF_BCLK# 13
+1.05VS_CK505
+3VS_CK505_G
B
33
ICS9LVS3197BKLFT MLF 32P
1 R1 15
2
10K_0201_5%
6
CK _P WRGD
+3VS_CK505
Q55A
09/21 update
1
C LK_EN#
40
2N7002DWH 2N SOT363-6
09/10 update
+3VS_CK505
+3VS
+3VS_CK505
+1.05VS
+1.05VS_CK505
Close to U6
Close to U6
R 116 1
2 10K_0201_5%
2
0_0603_5%
+3VS
1
R1 43
2
@ 0_0603_5%
1
R1 20
2
0_0603_5%
C1 64
10U_0805_10V4Z
C1 69
0.1U_0402_16V4Z
C1 68
0.1U_0402_16V4Z
C1 67
0.1U_0402_16V4Z
C1 66
0.1U_0402_16V4Z
1
R1 17
C1 65
0.1U_0402_16V4Z
C 176
47P_0402_50V8J
C 175
0.1U_0402_16V4Z
C 174
0.1U_0402_16V4Z
C 173
0.1U_0402_16V4Z
C 172
10U_0805_10V4Z
C 171
10U_0805_10V4Z
CPU_S TOP#
2
0_0603_5%
C1 70
47P_0402_50V8J
1
R1 18
+3VS_CK505_G
07/01 update
+1.5VS
CLK_XTAL_OUT
Low Power Chip: Install R120 and remove R143.

Standard Power Chip: Remove R120 and Install R143.
CLK _XTAL_IN
14.31818MHZ_20PF_7A14300038~D
Y1
2
C 177
33P_0402_50V8J
C1 78
33P_0402_50V8J
Close to U2 within 500mil
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

CLOCK GENERATOR
Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

5
Sheet
11
of
47
+R TCVCC
PCH_RTCX1
R1 21
PCH_RTCX2
2
10M_0402_5%
R1 24
S M_INTRUDER#
2
1M_0402_5%
PCH_INTVRMEN
2
330K_0402_5%
1
1
R1 22 1
2 10K_0201_5%
S I RQ
@ R1 25 2
1 10K_0201_5%
H DA_SPKR
C14
PCH_SRTCRS T#
CLR P2
@ SHORT PADS
1
1
1
1
2
2
2
2
33_0402_5%
33_0402_5%
33_0402_5%
33_0402_5%
SRTCRST#
S M_INTRUDER#
A16
INTRUDER#
PCH_INTVRMEN
A14
INTVRMEN
HDA_BIT_CLK
A30
HDA_BCLK
HDA _S Y NC
D29
HDA_SYNC
H DA_SPKR
P1
28
26
28
26
26
HDA_BIT_CLK_MDC
HDA_BIT_CLK_CODEC
HDA _S Y NC_MDC
HDA _S Y NC_ CODEC
H DA_SPKR
28
26
HDA_RST#_MDC
HD A_RST#_CODEC
HDA_RST#
C30
HDA_RST#
26
HDA _ SDIN0
HDA _ SDIN0
G30
HDA_SDIN0
28
HDA _ SDIN1
HDA _ SDIN1
2 33_0402_5%
2 33_0402_5%
F30
HDA_SDIN1
HDA_SDIN2
F32
HDA_SDIN3
H DA_SDOUT
B29
HDA_SDO
R 138 1
2 PCH_GPIO33
1K_0201_5%
R8
1
2 PCH_GPIO13
10K_0402_5%
H32
HDA_DOCK_EN# / GPIO33
J30
HDA_DOCK_RST# / GPIO13
PCH_JTA G_TCK
M3
JTAG_TCK
PCH_JTAG_TMS
K3
JTAG_TMS
PCH_JTAG_TDI
K1
JTAG_TDI
PCH_JTAG_TDO
J2
JTAG_TDO
PCH_TRST#
J4
JTAG_RST#
2 33_0402_5%
2 33_0402_5%
AQUAWHITE _BATLED
B
+3VALW
KBC_SPI_S I_R
1
2
R1 39
@ 1K_0201_5%
Enable=Stuff Disable=No Stuff
P AD
30
KBC_SPI_CLK_R
30
KBC_SPI_CS0#_R
30
KBC_SPI_CS1#_R
30
AF11
AF9
AF7
AF6
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
AH3
AH1
AF3
AF1
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AD9
AD8
AD6
AD5
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
AD3
AD1
AB3
AB1
SATAICOMPO
AF16
SATAICOMPI
AF15
SATAICOMPI
1
R 142
1
R 145
AY1
SPI_MOSI
SATA0GP / GPIO21
Y9
GPIO21
KBC_SPI_SO
AV1
SPI_MISO
SATA1GP / GPIO19
V1
HD D_HALTLED
22
22
22
22
SUYIN_060003FA002G202NL
CONN@
SATA_PRX_DTX_N5
SATA_PRX_DTX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5
2
37.4_0402_1%
29
29
29
29
+3VS
+1.05VS
R1 46
10K_0201_5%
+3VS
R1 47
10K_0201_5%
28,29
HD D_HALTLED
HD D_HALTLED
28
GPIO21
iAMT setting
@ 100_0402_1%
2
R 165
@ 100_0402_1%
2
R1 66
@ 100_0201_1%
VGATE
Production
4,15,21,22,23,31 PLT_RST#
4 ,14 XDP_DBRESET#
All
R2 14 1K_0402_5%
1
2
R157
Unstuff
200 ohm
Unstuff
PCH_JTAG_TDO
R166
Unstuff
100ohm
Unstuff
PCH_JTAG_TDI
PCH_JTAG_TMS
PCH_JTA G_TCK
R158
200 ohm
200 ohm
Unstuff
R167
100ohm
100ohm
Unstuff
R156
200 ohm
200 ohm
Unstuff
Unstuff
+3VS
J P5
+3VS
PCH_JTAG_TMS
R1 67
PCH_JTAG_TDO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
OBSFN_A0
OBSFN_A1
GND
OBSDATA_A0
OBSDATA_A1
GND
OBSDATA_A2
OBSDATA_A3
GND
HOOK0
HOOK2
HOOK4
HOOK5
VCCOBS_AB
HOOK6
HOOK7
GND
TDO
TRST#
TDI
TMS
TCK1
GND
TCK0
R1 41
R 140
@ 10K_0201_5%
@ 330K_0402_5%
28,30
AQUAWHITE_BATLED#
GPIO33
PCH_JTAG_TDI
D
1
@ 200_0402_5%
PCH_JTAG_TDO
@ 200_0402_5%
ES2
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_LED#
1K_0402_5%
ES1
@ 200_0402_5%
Pre-Production Units
IBEXPEAK-M_FCBGA1071
14,40
Ref.
22
22
22
22
2
10K_0201_5%
R 179
PCH Pin
23
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
SATA_PRX_DTX_N5
SATA_PRX_DTX_P5
SATA_PTX_DRX_N5
SATA_PTX_DRX_P5
KBC_SPI_SI_R
+3VALW
T3
2
1
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATALED#
R 156
2
2 PCH_JTA G_TCK
51_0402_5%
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SPI_CS1#
R1 57
1
R1 76
AH6
AH5
AH9
AH8
2
1K_0201_5%
C 184
22,25,30,31
SPI_CLK
R1 58
PCH_JTAG_TDI
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
NAND_DETECT#
S I RQ
SPI_CS0#
+3VALW
08/28 update
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N0
SATA_PTX_DRX_P0
22,30,31
1U_0603_10V4Z
2
AV3
0_0402_5%
2
AY3
0_0402_5%
+3VALW
C
AK7
AK6
AK11
AK9
R1 27
R_B ATT1.1
30
BA2
1
R1 44
1
R1 48
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
0202 D i sabl e iTPM
T121
S I RQ
07/02 update
SPI
iTPM ENABLE/DISABLE
JTAG
08/31 update
+3VM
AB9
SPKR
E32
R1 36 1
R1 37 1
H DA_SDOUT_MDC
HDA _SDOUT_CODEC
NAND_DETECT#
SERIRQ
LPC_LFRAME#
BAV70W 3P C/C SOT-323
28
26
R1 33 1
R1 34 1
LDRQ0#
LDRQ1# / GPIO23
A34
F34
22,30,31
22,30,31
22,30,31
22,30,31
AQUAWHITE _BATLED
R1 29
R1 30
R1 31
R1 32
FWH4 / LFRAME#
C34
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
Q31A
2N7002DWH 2N SOT363-6
2
1
D17
D33
B33
C32
A32
RTCRST#
LPC
PCH_RTCRST#
LAD0
LAD1
LAD2
LAD3
FWH0 /
FWH1 /
FWH2 /
FWH3 /
RTC
C 183
1U_0603_10V4Z
CLR P1
@ SHORT PADS
2 HDA_BIT_CLK_MDC
47P_0402_50V8J
2 HDA_BIT_CLK_CODEC
47P_0402_50V8J
2 H DA_SDOUT_MDC
47P_0402_50V8J
2 HDA _SDOUT_CODEC
47P_0402_50V8J
C 180
1U_0603_10V4Z
2
2
20K_0201_1%
R1 28 1
2
20K_0201_1% 1
R1 26 1
JBATT1
RTCX1
RTCX2
C1 82
18P_0402_50V8J
B13
D13
BATT1.1
+R TCVCC
1
PCH_RTCX1
PCH_RTCX2
SATA
+VREG3_51125
D1
1
IHDA
@
C1 85
@
C1 86
@
C1 87
@
C1 88
OSC
OSC
2
Y2
NC
NC
C 181
32.768KHZ_12.5PF_Q13MC14610002
18P_0402_50V8J
+R TCVCC
U7A
1
R 123
+3VS
iAMT Enable /Disable
Hi
Enable (Default)
Lo
Disable
MOLEX_52435-2472_24P-T
C ONN@
PCH_JTAG_TMS
R165
100ohm
100ohm
R176
51 ohm 5%
51 ohm 5%
Compal Secret Data
PCH_JTAG_TCK
51 ohm 5%
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

IBEX-M(1/6)-HDA/JTAG/SATA

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
12
of
47
SMB _CLK_S3
S MB_DATA_S3
1
R1 83
1
R1 85
2
10K_0201_5%
2
10K_0201_5%
SM BCLK
+3VS
SMBDATA
SML0CLK
4/23 Change R187,R188 from 4.7K_0201

to 2.2K_0402.
S ML0DATA
SML1CLK
S ML1DATA
U 7B
S ML0ALERT#
PCIE_PRX_DTX_N6
PCIE_PRX_DTX_P6
PCIE_PTX_C_DRX_N6
PCIE_PTX_C_DRX_P6
2 0.1U_0402_25V4K
2 0.1U_0402_25V4K
C1 97 1
C1 98 1
2 0.1U_0402_25V4K
2 0.1U_0402_25V4K
PCIE _PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE _PTX_DRX_N4
PCIE_PTX_DRX_P4
PERN4
PERP4
PETN4
PETP4
BF33
BH33
BG32
BJ32
PERN5
PERP5
PETN5
PETP5
PCIE _PRX_DTX_N6 BA34

PCIE_PRX_DTX_P6 AW34
PCIE _PTX_DRX_N6 BC34
PCIE_PTX_DRX_P6 BD34
+3VALW
R2 00 1
BA32
BB32
BD32
BE32
2 10K_0201_5%
AT34
AU34
AU36
AV36
PERN7
PERP7
PETN7
PETP7
BG34
BJ34
BG36
BJ36
PERN8
PERP8
PETN8
PETP8
AK48
AK47
CLKOUT_PCIE0N
CLKOUT_PCIE0P
P9
AM43
AM45
07/01 update
+3VS
21
23
23
CLK_PCIE_EXP#
CLK_PCIE_EXP
23
CLKREQ_EXP#
R 203 1
R 204 1
U4
CLK_PCIE_EXP#_R
CLK_PCIE_EXP_R
10K_0201_5%
R2 05 1
2
R 208 1
R 209 1
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
22
2 0_0402_5%
2 0_0402_5%
AM47
AM48
N4
+3VALW
22
22
2 10K_0201_5%
CLK_PCIE_LAN_REQ1#
+3VS
R2 02 1
AH42
AH41
R2 07 1
2 10K_0201_5%
2 0_0402_5%
2 0_0402_5%
CLK_PCIE_MCARD#_R
C LK_PCIE_MCARD_R
A8
AM51
AM53
M9
C LKREQ_WLAN#
+3VALW
R2 12 1
2 10K_0201_5%
+3VALW
R2 13 1
2 10K_0201_5%
+3VALW
R7 01 1
AJ50
AJ52
H6
AK53
AK51
2 10K_0201_5%
PERN6
PERP6
PETN6
PETP6
P13
CLKOUT_PCIE1N
CLKOUT_PCIE1P
PCIECLKRQ1# / GPIO18
CLKOUT_PCIE2N
CLKOUT_PCIE2P
S ML0ALERT#
SML0CLK
SML0DATA
G8
S ML0DATA
SML1ALERT# / GPIO74
M14
S ML1ALERT#
CLKOUT_PCIE4N
CLKOUT_PCIE4P
CLKOUT_PCIE5N
CLKOUT_PCIE5P
CLKOUT_PEG_B_N
CLKOUT_PEG_B_P
PEG_B_CLKRQ# / GPIO56
2
10K_0201_5%
21
SML0DATA
21
SML1CLK / GPIO58
E10
SML1CLK
SML1DATA / GPIO75
G12
S ML1DATA
CL_CLK1
T13
C L_CLK1
CL_DATA1
T11
CL_DATA1
22
CL_RST1#
T9
CL_RST1#
22
PEG_A_CLKRQ# / GPIO47
H1
CLKOUT_DMI_N
CLKOUT_DMI_P
Q8A
2N7002DW-T/R7_SOT363-6
SM BCLK
6
1
22
SMB _CLK_S3
SMB_CLK_S3
4,9,10,11,24
+3VS
SMBDATA
S MB_DATA_S3
SMB_DATA_S3
4,9,10,11,24
2N7002DW-T/R7_SOT363-6
Q8B
AD43
AD45
AN4 R_CLK_EXP#
AN2 R_CLK_EXP
R 195 1
R 196 1
2 0_0402_5%
2 0_0402_5%
CLK_EXP# 4
CLK_EXP 4
AT1 R _CLK_DP#
AT3 R_ CLK_DP
R 197 1
R 198 1
2 0_0201_5%
2 0_0201_5%
CLK_DP# 4
C LK_DP 4
AW24
BA24
CLK_DMI# 11
CLK_DMI 11
CLKIN_BCLK_N
CLKIN_BCLK_P
AP3
AP1
CLK_BUF_BCLK# 11
CLK_BUF_BCLK 11
CLKIN_DOT_96N
CLKIN_DOT_96P
F18
E18
CLK_BUF_DOT96# 11
CLK_BUF_DOT96 11
AH13
AH12
CL K_BUF_CKSSCD# 11
CL K_BUF_CKSSCD 11
REFCLK14IN
P41
CLK_14M_PCH
CLKIN_PCILOOPBACK
J42
C LK_PCI_FB
CLKIN_DMI_N
CLKIN_DMI_P
CLKIN_SATA_N / CKSSCD_N
CLKIN_SATA_P / CKSSCD_P
CLKOUT_PCIE3N
CLKOUT_PCIE3P
SML0CLK
1
R1 94
S ML1ALERT#
C6
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
SMBDATA
J14
CLKOUT_DP_N / CLKOUT_BCLK1_N
CLKOUT_DP_P / CLKOUT_BCLK1_P
C8
07/03 update
C1 95 1
C1 96 1
SM BCLK
07/03 update
20
21
21
21
21
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
H14
LID_SW#_ISO#
+3VALW
Q2A
2N7002DW-T/R7_SOT363-6
SML1CLK
1
2
0_0201_5%
R2 63
CAP_CLK
2 8,30
22
22
22
22
LID_SW#_ISO#
SML0CLK
SML0ALERT# / GPIO60
PERN3
PERP3
PETN3
PETP3
B9
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
2.2K_0402_5%
2
4.7K_0201_5%
2
4.7K_0201_5%
2
10K_0201_5%
+3VALW
5
AU30
AT30
AU32
AV32
PERN2
PERP2
PETN2
PETP2
SMBus
2 0.1U_0402_25V4K
2 0.1U_0402_25V4K
Link
C1 93 1
C1 94 1
Controller
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
SMBCLK
SMBDATA
PEG
23
23
23
23
PCIE _PRX_DTX_N2 AW30

PCIE_PRX_DTX_P2 BA30
PCIE _PTX_DRX_N2 BC30
PCIE_PTX_DRX_P2 BD30
SMBALERT# / GPIO11
PCI-E*
11/13 update
PERN1
PERP1
PETN1
PETP1
From CLK BUFFER
XTAL25_IN
XTAL25_OUT
AH51
AH53
X TAL25_IN
XTAL25_OUT
XCLK_RCOMP
AF38
XCLK _RCOMP R2 11 1
S ML1DATA
R2 64
1
2
0_0201_5%
CAP_DAT
28,30
2N7002DW-T/R7_SOT363-6
Q2B
11
15
X TAL25_IN
2 90.9_0402_1%
CLKOUTFLEX0 / GPIO64
T45
T55 P A D
P43
T56 P A D
T42
N50
+1.05VS
XTAL25_OUT
1
R 210
2
1M_0402_5%
Y3
1
Clock Flex
BG30
BJ30
BF29
BH29
1
R1 84
1
R1 86
1
R1 87
1
R1 88
1
R1 89
1
R1 91
1
R1 92
25MHZ_20PF_7A25000012
1 C 199
18P_0402_50V8J
1 C2 00
18P_0402_50V8J
6/16 Reserve back the 25MHz design circuit. (Reserve Y3,

R210,C199); Move R1093 to close to Y3 and C199.
7/1 Del T122, Del R1093(0_0402) and replace by add C200
(18P); Install R210,Y3,C199 by Intel finalized DP
workaround and need them.
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

IBEX-M(2/6)-PCI-E/SMBUS/CLK

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
13
of
47
5
5
5
5
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P3
BD24
BG22
BA20
BG20
DMI0RXP
DMI1RXP
DMI2RXP
DMI3RXP
5
5
5
5
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
BE22
BF21
BD20
BE18
DMI0TXN
DMI1TXN
DMI2TXN
DMI3TXN
5
5
5
5
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
BD22
BH21
BC20
BD18
DMI0TXP
DMI1TXP
DMI2TXP
DMI3TXP
BH25
DMI_ZCOMP
BF25
DMI_IRCOMP
DMI_IRCOMP
2
49.9_0402_1%
1
R2 20
4 ,12
12,40
30,40
1
R2 23
XDP_DBRESET#
VGATE
VGATE
R4 08 1
P GD _IN
2 SYS_RS T#
0_0201_5%
2 1K_0402_5%
32
M_PWROK
4
28,30
R PGOOD
PM_RSMRST#
30
+3VALW
SUS_PWR_ACK
PM_PWRBTN#_R
O N/OFFBTN#
30
O N/OFFBTN#
FDI
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_INT
BJ14
FDI _INT
FDI_FSYNC0
BF13
FDI_FS Y N C0
FDI_FSYNC1
BH13
FDI_FS Y N C1
FDI_LSYNC0
BJ12
FDI_LS Y NC0
FDI_LSYNC1
BG14
FDI_LS Y NC1
CLKRUN# / GPIO32
K5
PWROK
2 AUXP WROK A10

0_0201_5%
LAN_RST#
PM_DRAM_PW RGD D9
DRAMPWROK
2 0_0201_5%
2
C16
10K_0201_5%
2 10K_0201_5%
M1
2
0_0201_5%
BB18
BF17
BC16
BG16
AW16
BD14
BB14
BD12
SYS_PWROK
1
R 225
1
R2 31
FDI_RXP0
FDI_RXP1
FDI_RXP2
FDI_RXP3
FDI_RXP4
FDI_RXP5
FDI_RXP6
FDI_RXP7
M6
B17
P5
P7
AC_PRESENT
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
WAKE#
2
0_0201_5%
R2 28 1
1
R2 29
R2 30 1
BA18
BH17
BD16
BJ16
BA16
BE14
BA14
BC12
SYS_RESET#
1
R 224
PM_DRAM_PWRGD
36
30
FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7
T6
07/01 update
DMI
+1.05VS
DMI0RXN
DMI1RXN
DMI2RXN
DMI3RXN
MEPWROK
RSMRST#
SUS_PWR_ACK / GPIO30
PWRBTN#
J12
PCIE_WA KE#
Y1
P M_CLKRUN#
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
5
5
5
5
5
5
5
5
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
5
5
5
5
5
5
5
5
FDI _INT
20
20
ENABLT
E NA VDD
20
INV_PWM
PAD
T57
FDI_FS Y N C1
FDI_LS Y NC0
FDI_LS Y NC1
PCIE_WAKE#
P M_CLKRUN#
22,23
25,30,31
08/25 update
SUS_STAT# / GPIO61
P8
SUS_STAT#
T87 P AD
SUSCLK / GPIO62
F3
SUS_CLK
T58 P AD
SLP_S5# / GPIO63
E4
ACPRESENT / GPIO31
DA C _BLU
DA C_G RN
DA C_R ED
L_BKLTEN
L_VDD_EN
Y48
L_BKLTCTL
AB48
Y45
L_DDC_CLK
L_DDC_DATA
AB46
V48
L_CTRL_CLK
L_CTRL_DATA
AP39
AP41
LVD_IBG
LVD_VBG
AT43
AT42
LVD_VREFH
LVD_VREFL
AV53
AV51
LVDSA_CLK#
LVDSA_CLK
BB47
BA52
AY48
AV47
LVDSA_DATA#0
LVDSA_DATA#1
LVDSA_DATA#2
LVDSA_DATA#3
BB48
BA50
AY49
AV48
LVDSA_DATA0
LVDSA_DATA1
LVDSA_DATA2
LVDSA_DATA3
AP48
AP47
LVDSB_CLK#
LVDSB_CLK
AY53
AT49
AU52
AT53
LVDSB_DATA#0
LVDSB_DATA#1
LVDSB_DATA#2
LVDSB_DATA#3
AY51
AT48
AU50
AT51
LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3
AA52
AB53
AD53
CRT_BLUE
CRT_GREEN
CRT_RED
04/25 Delete U7.AT42 and U7.AT43 DGND

connection (confirmed with INTEL)
FDI_FS Y N C0
T48
T47
SDVO_TVCLKINN
SDVO_TVCLKINP
BJ46
BG46
SDVO_STALLN
SDVO_STALLP
BJ48
BG48
SDVO_INTN
SDVO_INTP
BF45
BH45
SDVO_CTRLCLK
SDVO_CTRLDATA
Digital Display Interface
DMI_CTX_PRX_N0 BC24
DMI_CTX_PRX_N1 BJ22
DMI_CTX_PRX_N2 AW20
DMI_CTX_PRX_N3 BJ20
H7
SLP_S4#
24,29,33,39
SLP_S3#
P12
SLP_S3#
23,29,30,32,33,35,37,38
SLP_M#
K8
PM_SLP_M#
TP23
N2
V51
V53
CRT_DDC_CLK
CRT_DDC_DATA
18
18
CRT_HS Y NC
CRT_V SYNC
Y53
Y51
CRT_HSYNC
CRT_VSYNC
AD48
AB51
DAC_IREF
CRT_IRTN
C6 69
0.1U_0402_16V4Z
11/11 update for EMI.

T51
T53
DPB_AUX# 29
DPB_AUX 29
DP B_HPD 29
DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P
DPB_TXN0
DPB_TXP0
DPB_TXN1
DPB_TXP1
DPB_TXN2
DPB_TXP2
DPB_TXN3
DPB_TXP3
DDPC_CTRLCLK
DDPC_CTRLDATA
Y49
AB49
DDPC_AUXN
DDPC_AUXP
DDPC_HPD
BE44
BD44
AV40
DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P
BE40
BD40
BF41
BH41
BD38
BC38
BB36
BA36
DPB_CTRLCLK 29
DPB_CTRLDATA 29
29
29
29
29
29
29
29
29
R 226
R 227
U50
U52
DP D_CTRLCLK
2.2K_0402_5%
2.2K_0402_5%
DDPD_AUXN
DDPD_AUXP
DDPD_HPD
BC46
BD46
AT38
C_DPD_AUX# C2 22 1
C_DPD_A UX C2 23 1
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P
BJ40
BG40
BJ38
BG38
BF37
BH37
BE36
BD36
C_DPD_TXN0
C_DP D_TXP0
C_DPD_TXN1
C_DP D_TXP1
C_DPD_TXN2
C_DP D_TXP2
C_DPD_TXN3
C_DP D_TXP3
2
2
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R 232
C2 24
C2 25
C2 26
C2 27
C2 28
C2 29
C2 30
C2 31
1
1
1
1
1
1
1
1
19
+3VS
DPD_CTRLDATA
CRT_D DC_CLK
C RT_DDC_DATA
DA C_I REF
2.2K_0402_5%
BD42
BC42
BJ42
BG42
BB40
BA40
AW38
BA38
DDPD_CTRLCLK
DDPD_CTRLDATA
18
18
30,32,33
R2 15
2.2K_0402_5%
BG44
BJ44
AU38
SLP_S5#
SLP_S4#
R 216
Place C669 close to R215.
DDPB_AUXN
DDPB_AUXP
DDPB_HPD
CRT
DMI_CTX_PRX_N0
DMI_CTX_PRX_N1
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
System Power Management
+3VS
U7D
5
5
5
5
LVDS
U7C
19
DPD_AUX# 19
DPD_AUX 19
DP D_H PD 19
DPD_TXN0
DPD_TXP0
DPD_TXN1
DPD_TXP1
DPD_TXN2
DPD_TXP2
DPD_TXN3
DPD_TXP3
19
19
19
19
19
19
19
19
IB EX_R#
A6
F14
BATLOW# / GPIO72
PMSYNCH
BJ10
H_ PM_SYNC
RI#
SLP_LAN#
F6
PM_SLP_LAN#
30,33,39
Add C145 close to R231 pin 1.

+3VS
P M_CLKRUN#
04/28 Remove R238

(Confirm why pull up to
Sus-Power different to
INTEL DG Core-Power)
1
R2 37
VGATE
1
R 236
DP B_HPD
1
R2 33
2
100K_0201_5%
DP D_H PD
1
R2 35
2
100K_0201_5%
2
10K_0201_5%
2
10K_0201_5%
+3VALW
SYS_RS T#
LOW_B AT_R
PM_SLP_LAN#
IB EX_R#
PCIE_WA KE#
AC_PRE SENT
1
2
R2 38 @ 10K_0201_5%
1
2
R2 39
10K_0201_5%
1
2
R2 41
10K_0201_5%
1
2
R2 43
10K_0201_5%
1
2
R2 45
1K_0201_5%
1
2
R2 46
@ 10K_0201_5%
SLP_S3#
SLP_S4#
SLP_S5#
1/4 update L1~L6 PCB Footprint
1
2
R 240 @ 10K_0201_5%
1
2
R 242 @ 10K_0201_5%
1
2
R 244 @ 10K_0201_5%
L1
HLC0603CSCC33NJT_0603
1
2
L3
1
2
L5
1
2
DA C_R ED
DA C_G RN
DA C _BLU
1
2
C2 34
18P_0402_50V8J
11/27 update
C2 33
18P_0402_50V8J
C2 32
18P_0402_50V8J
R2 49
@ 150_0402_1%
R2 48
@ 150_0402_1%
@ 150_0402_1%
R2 47
07/01 update
L2
0_0603_5%
1
2
L4
0_0603_5%
1
2
L6
0_0603_5%
1
2
RE D_L
G REEN_L
BLUE _L
@18P_0402_50V8J
C2 35
1K_0402_0.5%
RE D_R
18
GR EEN_R
B LUE_R
18
18
@18P_0402_50V8J
C2 37
0.1U_0402_16V4Z
LOW_B AT_R
O N/OFFBTN#
C 145
@18P_0402_50V8J
C2 36
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
5
Title

IBEX-M(3/6)-DMI/GPIO/LVDS

Cus t om L A-5251P
Dat e:
Rev
0 .9

1
Sheet
14
of
47
22,25,30,31
25
25
25
25
25
25
25
PCI_PIRQE#
O DD_DET#
P CI_PIRQG#
ACCEL_INT#
PCI_PIRQE#
ODD_DET#
P CI_PIRQG#
ACCEL_INT#
P C I_SERR#
P C I_PERR#
P C I_SERR#
P C I_PERR#
P CI_IRD Y#
P CI_IRD Y#
P CI_PAR
PCI_DEVSEL#
PCI_FRAME#
GNT0#
GNT1# / GPIO51
GNT2# / GPIO53
GNT3# / GPIO55
P CI_IRD Y#
P C I_PERR#
PCI_DEVS EL#
P C I_SERR#
PCI_REQ0#
PCI_PIRQB#
O DD_DET#
PCI_REQ3#
D49
PLOCK#
D41
C48
STOP#
TRDY#
M7
PME#
D5
PLTRST#
1
2
3
4
8
7
6
5
C6 61
1
+3VS
8.2K_0804_8P4R_5%
RP 2
8
7
6
5
1
2
3
4
8.2K_0804_8P4R_5%
RP 3
8
7
6
5
1
2
3
4
8.2K_0804_8P4R_5%
RP 4
8
7
6
5
AV11
BF5
USBRBIAS
USBRBIAS
D25
1
R 300
2
1K_0201_5%
0.1U_0402_16V4Z
2
+1.05VM
+1.05VS
+1.05VS
C LK_PCI_KBC
22,31
13
31
CL K_PCI_DB
C LK_PCI_FB
CLK_PCI_TPM
R 266 1
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
WEBCAM_ON
06/16 update
23
23
24
24
24
24
24
24
24
24
23
23
29
DOCK _ID0
29
DOCK _ID1
CLK_PCIE_LAN_REQ#
+3VALW
PCH_XDP_GPIO49
22
WLAN_TRANSMIT_OFF#
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
USB20_N8
USB20_P8
USB20_N9
USB20_P9
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N12
USB20_P12
1
R2 59
24
24
23
23
31
31
29
29
20
20
17
17
17
2
22.6_0402_1%
USB_OC#2
FP R_ OFF
USB_OC#4
R 282 1
CLK_PCI_1394
R 265
2
1
0_0402_5%
17
H10
WWAN_TRANSMIT_OFF# AB12
C LK_PCI_KBC_R
2 22_0402_5%
2 22_0402_5%
2 22_0402_5%
CLK_PCI_DB_P
CL K_PCI_FB_R
CLK_PCI_TPM_R
STP_PCI# / GPIO34
DOCK _ID0
DOCK _ID1
CLK_PCIE_LAN_REQ#
10K_0201_5%
R4 30 1
2
MISC
AF48
AF47
A20GATE
CLK_PCIE_LAN#_R
CLK_PCIE_LAN_R
1
10K_0201_5%
U2
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AM3
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AM1
RCIN#
P CH _PECI_R
T1
KB _RST#
PROCPWRGD
BE10
THRMTRIP#
BD10
T59 P AD
AB13
SATA3GP / GPIO37
TP2
AW22
T60 P AD
T61 P AD
SLOAD / GPIO38
TP3
P3
SDATAOUT0 / GPIO39
TP4
AY45
T62 P AD
H3
TP5
AY46
T63 P AD
F1
TP6
AV43
T64 P AD
AB6
SDATAOUT1 / GPIO48
TP7
AV45
T65 P AD
AA4
SATA5GP / GPIO49
TP8
AF13
T66 P AD
GPIO57
TP9
M18
T67 P AD
TP10
N18
T68 P AD
TP11
AJ24
T69 P AD
TP12
AK41
T70 P AD
TP13
AK42
T71 P AD
TP14
M32
T72 P AD
TP15
N32
T73 P AD
TP16
M30
T74 P AD
TP17
N30
T75 P AD
TP18
H12
T76 P AD
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS_NCTF_17
VSS_NCTF_18
VSS_NCTF_19
VSS_NCTF_20
VSS_NCTF_21
VSS_NCTF_22
VSS_NCTF_23
VSS_NCTF_24
VSS_NCTF_25
VSS_NCTF_26
VSS_NCTF_27
VSS_NCTF_28
VSS_NCTF_29
VSS_NCTF_30
VSS_NCTF_31
TP19
AA23
T77 P AD
NC_1
AB45
T78 P AD
NC_2
AB38
T79 P AD
NC_3
AB42
T80 P AD
NC_4
AB41
T81 P AD
NC_5
T39
T82 P AD
P6
T83 P AD
C10
T84 P AD
INIT3_3V#
MODE M_DISABLE
R 271 1
2 @ 1K_0201_5%
R 302 1
WLAN_TRANSMIT_OFF#
Danbury Technology Enable

NV_ALE
High=Endabled
Low=Disable (@)
2 LV@10K_0201_5%
+V_NVRAM_VCCQ
NV_A LE
CPU Type Detect : High-->SV , Low-->LV

1
R2 88
1
R2 84
2
1K_0201_5%
DMI Termination Voltage

NV_CLE
Set to Vss when LOW
Set to Vcc when HIGH
2
0_0201_5%
+3VS
1
2
3
4
ACCEL_INT#
PCI_LOCK#
1
2
3
4
8
7
6
5
U10
4
BUF_PLT_RST#
N V_CLE
IN1
IN2
8.2K_0804_8P4R_5%
RP 6
8
7
6
5
P LT_RST#
@ SN74AHC1G08DCKR_SC70-5
1
R2 97
2
1K_0201_5%
H_THERMTRIP#
CLK_PCI_1394
1
CLK_PCI_KBC
1
@
C6 35
12P_0402_50V8C
C LK_PCI_FB
1
@
C 660
12P_0402_50V8C
CLK_P CI_TPM
1
C6 58
12P_0402_50V8C
C 659
12P_0402_50V8C
NPCI_RST#
R2 68 1
2 10K_0201_5%
WWAN_TRANSMIT_OFF# R 273 1
2 10K_0201_5%
SATA_CLKREQ#
R2 72 1
2 10K_0201_5%
GPIO24
R 277 1
2 10K_0201_5%
PCH_XDP_GPIO49
R2 75 1
2 10K_0201_5%
GPIO15
R 280 1
2 SV@1K_0201_5%
W WAN_DET#
R2 79 1
2 100K_0201_5%
PRE P#
R 283 1
2 10K_0201_5%
ALS_EN#
R2 81 1
2 10K_0201_5%
CLK_PCIE_LAN_REQ#
R 286 1
2 10K_0201_5%
RUNS CI _EC#
R2 85 1
2 10K_0201_5%
USB_OC#0
R 289 1
2 10K_0201_5%
WEBCAM_ON
R2 87 1
2 @ 10K_0402_5%
P CH_ DDR_RST
R 291 1
2@ 10K_0201_5%
PCH_XDP_GPIO16
R2 90 1
2 10K_0201_5%
USB_OC#4
R 293 1
2 10K_0201_5%
DOCK _ID0
R2 92 1
2 10K_0201_5%
W OW #
R 295 1
2 10K_0201_5%
DOCK _ID1
R2 94 1
2 10K_0201_5%
GPIO48
R2 96 1
2 10K_0201_5%
STP_PCI#
R2 99 1
2 10K_0201_5%
PCH_XDP_GPIO28
R 368 1
2 10K_0201_5%
USB_OC#6
R 258 2
1 10K_0201_5%
USB_OC#2
R 301 2
1 10K_0201_5%
L AN_DIS#
Deciphered Date
2010/12/31
Title
07/02 update
+3VM_LAN
07/02 update
Compal Secret Data

2008/09/15
3
+3VS
2 10K_0201_5%
Issued Date
30
H_CP UP W RGD
R 269 1
+3VS
RP 5
KB_RST#
+3VALW
2 @ 1K_0201_5%
+3VS
PCI_PIRQA#
THERM_S CI#
P CI _PIRQC#
P CI_PIRQG#
H_P ECI
+ VCCP
BB22
TP24
R 267 1
GPIO15
30
R2 56
56_0402_5%
BA22
PCH_XDP_GPIO49
P CH _NCTF26
GATEA20
2 R 254
2
+3VS
R 260
1
2
R2 55 54.9_0402_1%
SATACLKREQ# / GPIO35
GPIO48
P CH _NCTF19
1
0_0201_5%
1
10K_0201_5%
H_THERMTRIP#_L
TP1
A4
A49
A5
A50
A52
A53
B2
B4
B52
B53
BE1
BE53
BF1
BF53
BH1
BH2
BH52
BH53
BJ1
BJ2
BJ4
BJ49
BJ5
BJ50
BJ52
BJ53
D1
D2
D53
E1
E53
21
21
+3VS
C LK_CPU_BCLK
BG10
SATA2GP / GPIO36
WLAN_TRANSMIT_OFF# F8
CLK_PCIE_LAN
CLK_CPU_BCLK#
AB7
V3
2
R 253
CLK_PCIE_LAN#
09/12 update
CLK_PCI_1394_R
CLKOUT_PCIE7N
CLKOUT_PCIE7P
PECI
GPIO27
M11
23
PCI_GNT0#
MEM_LED / GPIO24
STP_PCI#
+3VS
2 22_0402_5%
SCLOCK / GPIO22
GPIO28
08/25 update
CPPE#
TACH0 / GPIO17
V13
WEBCAM_ON
AH45
AH46
SATA4GP / GPIO16
PCH_XDP_GPIO28
V6
CLKOUT_PCIE6N
CLKOUT_PCIE6P
Y7
P CH_ NCTF6
P CH_ NCTF7
8.2K_0804_8P4R_5%
5
W WAN_DET#
31
0.1U_0402_16V4Z
2 22_0402_5%
F38
PREP# 18,21,29
LA NLINK_R# 21,30
USB_OC#6
W OW #
0.1U_0402_16V4Z
2
+1.05VM
24
GPIO15
AA2
USB_OC#0
BT_OFF
LAN_PHY_PWR_CTRL / GPIO12
T7
ALS_EN#
NPCI_RST#
20
23
23
K9
PCH_XDP_GPIO16
SATA_CLKREQ#
30
21
10/19 update
R 274 1
R 276 1
R 278 1
ALS_EN#
W W AN_DET#
WWAN_TRANSMIT_OFF#

30
LA N_DIS#
10/13 update
N16
J16
F16
L16
E14
G16
F12
T15
C 662
1
GPIO8
21
23
N V_WE#_CK0
N V_WE#_CK1
B25
F10
2
@ 32.4_0402_1%
NV_WE#_CK0
NV_WE#_CK1
USBRBIAS#
TACH3 / GPIO7
P CH_ DDR_RST
P CH_D DR_RST
23
23
NV _ RE#_WR#0
NV _ RE#_WR#1
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
USBP12N
USBP12P
USBP13N
USBP13P
TACH2 / GPIO6
J32
GPIO24
AY8
AY5
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
D37
THERM_S CI#
20
NV_WR#0_RE#
NV_WR#1_RE#
H18
J18
A18
C18
N20
P20
J20
L20
F20
G20
A20
C20
M22
N22
B21
D21
H22
J22
E22
F22
A22
C22
G24
H24
L24
M24
A24
C24
RUNS CI _EC#
THERM_SCI#
23
NV _RB#
TACH1 / GPIO1
RUNS CI _EC#
09/03 update
1
R2 57
BMBUSY# / GPIO0
GPIO15
23,28
Y3
C38
30
07/08 update for INTEL

S3 leakage issue.
AV7
C 663
25
0_0402_5%
0_0402_5%
2
1
2
1
R 251
R 252
AU2 NV_RCOMP
2 10K_0201_5% PCH_XDP _GPIO0

PCH_XDP_GPIO0
41 O CP#
CPU
NV_ALE
N V_CLE
R2 50 1
+3VS
NV_RB#
OC0# / GPIO59
OC1# / GPIO40
OC2# / GPIO41
OC3# / GPIO42
OC4# / GPIO43
OC5# / GPIO9
OC6# / GPIO10
OC7# / GPIO14
CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4
BD3 NV_A LE
AY6 N V_CLE
23
23
23
23
GPIO
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
23
8.2K_0804_8P4R_5%
PCI_GNT3#
SERR#
PERR#
PCI_LOCK#
RP 1
1
2
3
4
PCI_REQ2#
PCI_REQ1#
PCI_FRAM E#
P CI_ TRDY#
23
23
NV _DQ0
NV _DQ1
NV _DQ2
NV _DQ3
NV _DQ4
NV _DQ5
NV _DQ6
NV _DQ7
NV _DQ8
NV _DQ9
NV _DQ10
NV _DQ11
NV _DQ12
NV _DQ13
NV _DQ14
NV _DQ15
+3VS
10/21 update
P CI _PIRQD#
PCI_PIRQE#
PCI_STOP#
PCIRST#
IRDY#
PAR
DEVSEL#
FRAME#
C LK_PCI_KBC_RN52
CL K_PCI_FB_R P53
CLK_PCI_TPM_R P46
CLK_PCI_1394_RP51
CLK_PCI_DB_P P48
N V_DQS0
N V_DQS1
AP7
AP6
AT6
AT9
BB1
AV6
BB3
BA4
BE4
BB6
BD6
BB7
BC8
BJ8
BJ6
BG6
PIRQE# / GPIO2
PIRQF# / GPIO3
PIRQG# / GPIO4
PIRQH# / GPIO5
A42
H44
F46
C46
PLT_RST#
NVRAM
F48
K45
F36
H53
PCI_DEVS EL#
PCI_FRAM E#
PCI_STOP#
P CI_ TRDY#
PCI_STOP#
P CI_ TRDY#
AV9
BG8
NV_RCOMP
REQ0#
REQ1# / GPIO50
REQ2# / GPIO52
REQ3# / GPIO54
E44
E50
NV_DQS0
NV_DQS1
NV_DQ0 / NV_IO0
NV_DQ1 / NV_IO1
NV_DQ2 / NV_IO2
NV_DQ3 / NV_IO3
NV_DQ4 / NV_IO4
NV_DQ5 / NV_IO5
NV_DQ6 / NV_IO6
NV_DQ7 / NV_IO7
NV_DQ8 / NV_IO8
NV_DQ9 / NV_IO9
NV_DQ10 / NV_IO10
NV_DQ11 / NV_IO11
NV_DQ12 / NV_IO12
NV_DQ13 / NV_IO13
NV_DQ14 / NV_IO14
NV_DQ15 / NV_IO15
NV_ALE
NV_CLE
F51
A46
B45
M53
K6
PIRQA#
PIRQB#
PIRQC#
PIRQD#
B41
K53
A36
A48
PCI_RST#
4,12,21,22,23,31
G38
H51
B37
A44
N V_CE0#
N V_CE1#
N V_CE2#
N V_CE3#
NCTF
P AD T114
PCI_GNT2#
C/BE0#
C/BE1#
C/BE2#
C/BE3#
AY9
BD1
AP15
BD8
22,25
PCI_GNT0#
MODE M_DISABLE
PCI_GNT2#
PCI_GNT3#
J50
G42
H47
G34
NV_CE#0
NV_CE#1
NV_CE#2
NV_CE#3
25
22
25
24
PCI_REQ2#
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
25
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
H40
N34
C44
A38
C36
J34
A40
D45
E36
H48
E40
C40
M48
M45
F53
M40
M43
J36
K48
F40
C42
K46
M51
J52
K51
L34
F42
J40
G46
F44
M47
H36
25
RSVD
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PCI_PIRQA#
PCI_PIRQB#
P CI _PIRQC#
P CI _PIRQD#
U 7F
USB
P C I_AD0
P C I_AD1
P C I_AD2
P C I_AD3
P C I_AD4
P C I_AD5
P C I_AD6
P C I_AD7
P C I_AD8
P C I_AD9
P CI_AD10
P CI_AD11
P CI_AD12
P CI_AD13
P CI_AD14
P CI_AD15
P CI_AD16
P CI_AD17
P CI_AD18
P CI_AD19
P CI_AD20
P CI_AD21
P CI_AD22
P CI_AD23
P CI_AD24
P CI_AD25
P CI_AD26
P CI_AD27
P CI_AD28
P CI_AD29
P CI_AD30
P CI_AD31
25
25
25
25
U 7E
P C I_AD[0..31]
PCI
25
R2 98 1
2 10K_0201_5%

IBEX-M(4/6)-PCI/USB/RSVD

Cus t om L A-5251P
Dat e:
Rev
0 .9

1
Sheet
15
of
47
+3VS
C2 62
0.1U_0402_16V4Z
+3VS
AD13
+3VS
0.1U_0402_16V4Z
1
1
2
C2 70 0.1U_0402_16V4Z
T126
T127
AK3
AK1
R 303 1
+1.8VS
P AD
P AD
C2 71
2
P AD
2 0_0402_5%
+1.05VS_VCCFDIPLL
T125
6/22
VCCVRM[4]
AT20
VCCIO[10]
AH19
VCCIO[11]
AD20
VCCIO[12]
AF22
VCCIO[13]
VCCIO[14]
VCCIO[15]
VCCIO[16]
AD19
AF20
AF19
AH20
VCCIO[17]
VCCIO[18]
VCCIO[19]
VCCIO[20]
AB19
AB20
AB22
AD22
VCCME[13]
VCCME[14]
VCCME[15]
VCCME[16]
AA34
Y34
Y35
AA35
AB34
VCC3_3[3]
AB35
VCC3_3[4]
AD35
VCCVRM[2]
AT24
VCCDMI[1]
AT16
VCCDMI[2]
AU16
VCCPNAND[1]
VCCPNAND[2]
VCCPNAND[3]
VCCPNAND[4]
VCCPNAND[5]
VCCPNAND[6]
VCCPNAND[7]
VCCPNAND[8]
VCCPNAND[9]
AM16
AK16
AK20
AK19
AK15
AK13
AM12
AM13
AM15
VCCIO[54]
VCCIO[55]
AN35
VCC3_3[1]
AT22
VCCVRM[1]
0.035A
BJ18
VCCFDIPLL
6mA
VCCME3_3[1]
VCCME3_3[2]
VCCME3_3[3]
VCCME3_3[4]
AM8
AM9
AP11
AP9
AM23
VCCIO[1]
LVDS
HVCMOS
AN30
AN31
+3VS
1
C 254
+1.8VS
0.061A
+VCCP
1
C 261
VCCSUS3_3[30]
+V_NVRAM_VCCQ
0.156A
+3VM
0.085A
VCCSUS3_3[32]
+3VS
0. 4A@3.3V
2
0.1U_0402_16V4Z
C 280
V15
VCC3_3[5]
V16
VCC3_3[6]
Y16
VCC3_3[7]
C2 91
0.1U_0402_16V4Z
C2 90
0.1U_0402_16V4Z
2mA @3.3V
V_CPU_IO[1]
AU18
V_CPU_IO[2]
A12
>1mA
VCCRTC
2mA
HDA
AT18
RTC
0.1U_0402_16V4Z
C2 86
0.1U_0402_16V4Z
0. 1A@1.1V
CPU
+ VCCP
6mA
VCCSUSHDA
+1.05VS
L10
+V1.05S_VCCA_A_DPL
1
2
10UH_LB2012T100MR_20%_0805
1
1
+ C2 81
C 282
1U_0402_6.3V4Z
220U_B2_2.5VM_R15M
2
<BOM Structure>
+PCH_VCC1_1_20
+PCH_VCC1_1_21
+PCH_VCC1_1_22
+PCH_VCC1_1_23
R 311 1
L30
1
1
1
1
R3 05
R3 06
R3 07
R3 08
+1.05VM
2
2
2
2
2 0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
+5VALW +3VALW
L11
1
+3VALW
0202 Change value +5VS
+V1.05S_VCCA_B_DPL
10UH_LB2012T100MR_20%_0805
1
C 288
1U_0402_6.3V4Z
R3 09
+ C2 87
220U_B2_2.5VM_R15M
D2
100_0402_5%
+3VS
R3 10
CH751H-40PT_SOD323-2
C 289
D3
100_0402_5%
IC H_V5REF_SUS
0202 Change value
1U_0402_6.3V4Z
C 292
1U_0402_6.3V4Z
Issued Date
Deciphered Date
2010/12/31
ICH_V 5R EF_RUN
20 mils
20 mils
Compal Secret Data

2008/09/15
2
+1.05VS
Don't need extra-power
C 279
VCCSUS3_3[31]
U22
+1.8VS
1U_0402_6.3V4Z
U20
2
1U_0603_10V4Z
VCCSUS3_3[29]
U19
2
0.1U_0402_16V4Z
P18
SATA
0. 2A@3.3V
2
0.1U_0402_16V4Z
C 278
C2 84
AH22
VCC3_3[2]
C2 85
4.7U_0603_6.3V6K
VCCIO[9]
AP43
AP45
AT46
AT45
VCCSATAPLL[1]
VCCSATAPLL[2]
VCCTX_LVDS[3]
VCCTX_LVDS[4]
0.032A
VCCTX_LVDS[1]
3.208A
+3VS
VCCIO[25]
VCCIO[26]
VCCIO[27]
VCCIO[28]
VCCIO[29]
VCCIO[30]
VCCIO[31]
VCCIO[32]
VCCIO[33]
VCCIO[34]
VCCIO[35]
VCCIO[36]
VCCIO[37]
VCCIO[38]
VCCIO[39]
VCCIO[40]
VCCIO[41]
VCCIO[42]
VCCIO[43]
VCCIO[44]
VCCIO[45]
VCCIO[46]
VCCIO[47]
VCCIO[48]
VCCIO[49]
VCCIO[50]
VCCIO[51]
VCCIO[52]
VCCIO[53]
DMI
U35
AH39
PCI E*
VCC3_3[13]
+1.05VS
+3VALW
VCC3_3[12]
P36
VCCALVDS
VSSA_LVDS
DCPSUS
N36
Y22
VCC3_3[11]
1
2
10UH_LB2012T100MR_20%_0805
1
+V1.1A_INT_V CCSUS
2
0.1U_0402_16V4Z
C 274
VCC3_3[10]
M36
0.030A
AH38
NAND / SPI
DCPSST
+R TCVCC
L38
ICH_V 5R EF_RUN
AN20
AN22
AN23
AN24
AN26
AN28
BJ26
BJ28
AT26
AT28
AU26
AU28
AV26
AV28
AW26
AW28
BA26
BA28
BB26
BB28
BC26
BC28
BD26
BD28
BE26
BE28
BG26
BG28
BH27
FDI
V12
VCC3_3[9]
C2 75
+VCCSST
J38
0.1U_0402_16V4Z
VCCIO[4]
2
0.1U_0402_16V4Z
C 272
K49
VCC3_3[14]
AF32
0.357A
V5REF
VCC3_3[8]
AF51
C2 66
VCCIO[21]
VCCIO[22]
VCCIO[23]
>1mA
VCCAPLLEXP0.042A
AF53
VSSA_DAC[2]
0.1U_0402_16V4Z
VCCADPLLB[1]
VCCADPLLB[2]
C 265
0.073A
IC H_V5REF_SUS
C 264
VCCADPLLA[1]
VCCADPLLA[2]
VCCIO[3]
F24
+1.05VS
+1.05VS
10U_0603_6.3V6M
0.072A
VCCIO[2]
V5REF_SUS
>1mA
+1.05VS_APLL
C 260
0.035A
VCCVRM[3]
AH34
V23
T124
1U_0402_6.3V4Z
DCPRTC
AF34
U23
VCCIO[56]
P AD
C 259
V9
VCCSUS3_3[28]
C 263
USB
VCCME[12]
Clock and Miscellaneous
VCCME[11]
Y42
PCI/GPIO/LPC
VCCME[10]
Y41
BJ24
VSSA_DAC[1]
0.059AVCCTX_LVDS[2]
Don't need extra-power
1U_0402_6.3V4Z
VCCME[9]
Y39
AH23
AJ35
AH35
1U_0402_6.3V4Z
C2 69
1U_0402_6.3V4Z
C2 67
C2 68
1U_0402_6.3V4Z
VCCME[8]
V42
BD51
BD53
+1.05VS
VCCME[7]
1U_0402_6.3V4Z
+V1.05S_VCCA_B_DPL
1.998A
V41
BB51
BB53
+V1.05S_VCCA_A_DPL
VCCME[6]
AU24
+1.8VS
VCCME[5]
AF42
AE52
+1.05VS
1
1U_0402_6.3V4Z
C 258
1
2 +VCCRTCEXT
0.1U_0402_16V4Z
VCCME[4]
AF41
VCCIO[24]
AE50
VCCADAC[2]
C2 44
22U_0805_6.3V6M
B
AF43
AK24
VCCADAC[1]
0.1U_0402_16V4Z
1
C 257
VCCME[3]
C 251
VCCME[2]
AD41
0.1U_0402_16V4Z
C 256
AD39
0.069A
+3VALW
C 250
C2 55
VCCME[1]
V39
1U_0402_6.3V4Z
DCPSUSBYP
0.1U_0402_16V4Z
C2 52
1U_0402_6.3V4Z
VCCLAN[2]
AD38
VCCSUS3_3[1]
VCCSUS3_3[2]
VCCSUS3_3[3]
VCCSUS3_3[4]
VCCSUS3_3[5]
VCCSUS3_3[6]
VCCSUS3_3[7]
VCCSUS3_3[8]
VCCSUS3_3[9]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
0.163AVCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
VCCSUS3_3[21]
VCCSUS3_3[22]
VCCSUS3_3[23]
VCCSUS3_3[24]
VCCSUS3_3[25]
VCCSUS3_3[26]
VCCSUS3_3[27]
VCCCORE[1]
VCCCORE[2]
VCCCORE[3]
VCCCORE[4] 1.524A
VCCCORE[5]
VCCCORE[6]
VCCCORE[7]
VCCCORE[8]
VCCCORE[9]
VCCCORE[10]
VCCCORE[11]
VCCCORE[12]
VCCCORE[13]
VCCCORE[14]
VCCCORE[15]
C2 43
+1.05VM
0.344A
C 246
1U_0402_6.3V4Z
POWER
AB24
AB26
AB28
AD26
AD28
AF26
AF28
AF30
AF31
AH26
AH28
AH30
AH31
AJ30
AJ31
10U_0805_6.3V6M
2
Y20
0.1U_0402_16V4Z
VCCLAN[1]
C2 42
AF24
V28
U28
U26
U24
P28
P26
N28
N26
M28
M26
L28
L26
J28
J26
H28
H26
G28
G26
F28
F26
E28
E26
C28
C26
B27
A28
A26
0.052A
L7
0.01U_0603_16V7K
AF23
1
C 247
22U_0805_6.3V6M
VCCACLK[2]
V24
V26
Y24
Y26
C2 41
T111
AP53
VCCIO[5]
VCCIO[6]
VCCIO[7]
VCCIO[8]
10U_0805_6.3V6M
P AD
VCCACLK[1]
C2 40
AP51
1U_0603_10V4Z
C2 45
1U_0402_6.3V4Z
POWER
U 7J
+1.05VM
U7G
CRT
+1.05VS
+1.05VS
VCC CORE
T123
PCI/GPIO/LPC
P AD
Title
C 293
1U_0603_6.3V6M

IBEX-M(5/6)-PWR

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
16
of
47
AK30
AK31
AK32
AK34
AK35
AK38
AK43
AK46
AK49
AK5
AK8
AL2
AL52
AM11
BB44
AD24
AM20
AM22
AM24
AM26
AM28
BA42
AM30
AM31
AM32
AM34
AM35
AM38
AM39
AM42
AU20
AM46
AV22
AM49
AM7
AA50
BB10
AN32
AN50
AN52
AP12
AP42
AP46
AP49
AP5
AP8
AR2
AR52
AT11
BA12
AH48
AT32
AT36
AT41
AT47
AT7
AV12
AV16
AV20
AV24
AV30
AV34
AV38
AV42
AV46
AV49
AV5
AV8
AW14
AW18
AW2
BF9
AW32
AW36
AW40
AW52
AY11
AY43
AY47
+3VS
R3 12
Q10A
2N7002DW-T/R7_SOT363-6
2
P CH _NCTF6
15
8,30
CRACK_BGA
100K_0201_5%
2
+3VS
CRACK_BGA
3
R3 13
100K_0201_5%
Q10B
2N7002DW-T/R7_SOT363-6
5
P CH _NCTF7
15
+3VS
CRACK_BGA
C
R3 14
100K_0201_5%
Q11A
2N7002DW-T/R7_SOT363-6
15
P CH _NCTF19
VSS[80]
VSS[81]
VSS[82]
VSS[83]
VSS[84]
VSS[85]
VSS[86]
VSS[87]
VSS[88]
VSS[89]
VSS[90]
VSS[91]
VSS[92]
VSS[93]
VSS[94]
VSS[95]
VSS[96]
VSS[97]
VSS[98]
VSS[99]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[1]
VSS[2]
VSS[3]
VSS[4]
VSS[5]
VSS[6]
VSS[7]
VSS[8]
VSS[9]
VSS[10]
VSS[11]
VSS[12]
VSS[13]
VSS[14]
VSS[15]
VSS[16]
VSS[17]
VSS[18]
VSS[19]
VSS[20]
VSS[21]
VSS[22]
VSS[23]
VSS[24]
VSS[25]
VSS[26]
VSS[27]
VSS[28]
VSS[29]
VSS[30]
VSS[31]
VSS[32]
VSS[33]
VSS[34]
VSS[35]
VSS[36]
VSS[37]
VSS[38]
VSS[39]
VSS[40]
VSS[41]
VSS[42]
VSS[43]
VSS[44]
VSS[45]
VSS[46]
VSS[47]
VSS[48]
VSS[49]
VSS[50]
VSS[51]
VSS[52]
VSS[53]
VSS[54]
VSS[55]
VSS[56]
VSS[57]
VSS[58]
VSS[59]
VSS[60]
VSS[61]
VSS[62]
VSS[63]
VSS[64]
VSS[65]
VSS[66]
VSS[67]
VSS[68]
VSS[69]
VSS[70]
VSS[71]
VSS[72]
VSS[73]
VSS[74]
VSS[75]
VSS[76]
VSS[77]
VSS[78]
VSS[79]
VSS[0]
AA19
AA20
AA22
AM19
AA24
AA26
AA28
AA30
AA31
AA32
AB11
AB15
AB23
AB30
AB31
AB32
AB39
AB43
AB47
AB5
AB8
AC2
AC52
AD11
AD12
AD16
AD23
AD30
AD31
AD32
AD34
AU22
AD42
AD46
AD49
AD7
AE2
AE4
AF12
Y13
AH49
AU4
AF35
AP13
AN34
AF45
AF46
AF49
AF5
AF8
AG2
AG52
AH11
AH15
AH16
AH24
AH32
AV18
AH43
AH47
AH7
AJ19
AJ2
AJ20
AJ22
AJ23
AJ26
AJ28
AJ32
AJ34
AT5
AJ4
AK12
AM41
AN19
AK26
AK22
AK23
AK28
AB16
+3VS
CRACK_BGA
3
R3 15
100K_0201_5%
15
Q11B
2N7002DW-T/R7_SOT363-6
5
P CH _NCTF26
H49
H5
J24
K11
K43
K47
K7
L14
L18
L2
L22
L32
L36
L40
L52
M12
M16
M20
N38
M34
M38
M42
M46
M49
M5
M8
N24
P11
AD15
P22
P30
P32
P34
P42
P45
P47
R2
R52
T12
T41
T46
T49
T5
T8
U30
U31
U32
U34
P38
V11
P16
V19
V20
V22
V30
V31
V32
V34
V35
V38
V43
V45
V46
V47
V49
V5
V7
V8
W2
W52
Y11
Y12
Y15
Y19
Y23
Y28
Y30
Y31
Y32
Y38
Y43
Y46
P49
Y5
Y6
Y8
P24
T43
AD51
AT8
AD47
Y47
AT12
AM6
AT13
AM5
AK45
AK39
AV14
U7H
VSS[259]
VSS[260]
VSS[261]
VSS[262]
VSS[263]
VSS[264]
VSS[265]
VSS[266]
VSS[267]
VSS[268]
VSS[269]
VSS[270]
VSS[271]
VSS[272]
VSS[273]
VSS[274]
VSS[275]
VSS[276]
VSS[277]
VSS[278]
VSS[279]
VSS[280]
VSS[281]
VSS[282]
VSS[283]
VSS[284]
VSS[285]
VSS[286]
VSS[287]
VSS[288]
VSS[289]
VSS[290]
VSS[291]
VSS[292]
VSS[293]
VSS[294]
VSS[295]
VSS[296]
VSS[297]
VSS[298]
VSS[299]
VSS[300]
VSS[301]
VSS[302]
VSS[303]
VSS[304]
VSS[305]
VSS[306]
VSS[307]
VSS[308]
VSS[309]
VSS[310]
VSS[311]
VSS[312]
VSS[313]
VSS[314]
VSS[315]
VSS[316]
VSS[317]
VSS[318]
VSS[319]
VSS[320]
VSS[321]
VSS[322]
VSS[323]
VSS[324]
VSS[325]
VSS[326]
VSS[327]
VSS[328]
VSS[329]
VSS[330]
VSS[331]
VSS[332]
VSS[333]
VSS[334]
VSS[335]
VSS[336]
VSS[337]
VSS[338]
VSS[339]
VSS[340]
VSS[341]
VSS[342]
VSS[343]
VSS[344]
VSS[345]
VSS[346]
VSS[347]
VSS[348]
VSS[349]
VSS[350]
VSS[351]
VSS[352]
VSS[353]
VSS[354]
VSS[355]
VSS[356]
VSS[366]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
VSS[199]
VSS[200]
VSS[201]
VSS[202]
VSS[203]
VSS[204]
VSS[205]
VSS[206]
VSS[207]
VSS[208]
VSS[209]
VSS[210]
VSS[211]
VSS[212]
VSS[213]
VSS[214]
VSS[215]
VSS[216]
VSS[217]
VSS[218]
VSS[219]
VSS[220]
VSS[221]
VSS[222]
VSS[223]
VSS[224]
VSS[225]
VSS[226]
VSS[227]
VSS[228]
VSS[229]
VSS[230]
VSS[231]
VSS[232]
VSS[233]
VSS[234]
VSS[235]
VSS[236]
VSS[237]
VSS[238]
VSS[239]
VSS[240]
VSS[241]
VSS[242]
VSS[243]
VSS[244]
VSS[245]
VSS[246]
VSS[247]
VSS[248]
VSS[249]
VSS[250]
VSS[251]
VSS[252]
VSS[253]
VSS[254]
VSS[255]
VSS[256]
VSS[257]
VSS[258]
U 7I
AY7
B11
B15
B19
B23
B31
B35
B39
B43
B47
B7
BG12
BB12
BB16
BB20
BB24
BB30
BB34
BB38
BB42
BB49
BB5
BC10
BC14
BC18
BC2
BC22
BC32
BC36
BC40
BC44
BC52
BH9
BD48
BD49
BD5
BE12
BE16
BE20
BE24
BE30
BE34
BE38
BE42
BE46
BE48
BE50
BE6
BE8
BF3
BF49
BF51
BG18
BG24
BG4
BG50
BH11
BH15
BH19
BH23
BH31
BH35
BH39
BH43
BH47
BH7
C12
C50
D51
E12
E16
E20
E24
E30
E34
E38
E42
E46
E48
E6
E8
F49
F5
G10
G14
G18
G2
G22
G32
G36
G40
G44
G52
AF39
H16
H20
H30
H34
H38
H42
BGA Ball Cracking Prevention and Detection
D
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

IBEX-M(6/6)-GND

Cus t om L A-5251P
Dat e:
Rev
0 .9

5
Sheet
17
of
47
CRT Connector
+5VS
F1
1.1A_6VDC_FUSE
1
2
+RC RT_VCC
D4
CH4 91D_SC59
2
1
+C RTVDD
W=40mils
+3VS
+5VS
PREP#: DOCK --> L

PREP#: UNDOCK --> H
0.1U_0402_16V4Z
1
C 298
U13
D_DDCC LK 29
D_D DCDATA 29
SCL2
SDA2
19
21
V G A_DDC_CLK
VGA_DDC_DA TA
EN
SEL
23
24
GND
EP
10
25
V GA_GRN_R
VGA_BLUE
R 318 1
2 0_0402_5%
VGA_BLUE_R
15,21,29
MAX4885EETG+T_TQFN24_4X4
75_0402_1%
+3VS
2 10K_0402_5%
PREP#
C3 15
75_0402_1%
C3 21
R3 19 1
PRE P#
VGA_DDC_DA TA
C3 20
75_0402_1%
H1
V1
D_DDCC LK
D_D DCDATA
2 0_0402_5%
@ 10P_0402_50V8J
11
12
20
22
R 317 1
C2 97
@ 10P_0402_50V8J
H0
V0
CRT_ DDC_CLK 14
C RT_DDC_DATA 14
SCL1
SDA1
V GA_GRN
@ 150_0402_1%
H S Y NC
V S Y NC
6
7
CRT_D DC_CLK
CR T_DDC_DATA
C2 95
CRT_HS Y NC
CRT_ VSYNC
SCL0
SDA0
2
1
V GA_RED_R
@ 150_0402_1%
CRT_HS Y NC
CRT_V SYNC
R2
G2
B2
2 0_0402_5%
@ 150_0402_1%
14
14
17
15
13
VL
R 316 1
R3 24
R1
G1
B1
MAX4885E VCC
2
J C RT1
VGA_RED
R3 23
VGA_RED
V GA_GRN
VGA_BLUE
18
16
14
0.1U_0402_16V4Z
C2 96
@ 10P_0402_50V8J
DOCK _RED
DOCK _GRN
DO CK_BLU
R0
G0
B0
Place close to JCRT1 for EMI backup solution.
3
4
5
C 299
R3 22
29 DOCK _RED
29 DOCK _ GRN
29 DO CK_BLU
RE D_R
GRE EN_R
B LUE_R
0.1U_0402_16V4Z
14 R E D_R
14 GRE EN_R
14 B L UE_R
C2 94
V G A_DDC_CLK
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
G
G
16
17
B
S U YIN_070546FR015S233ZR
C ONN@
11/27 update
11/27 update
ESD design inside U13 already
R53
H S Y NC
R3 25 1
2 0_0603_5%
D _ HS Y NC
V S Y NC
R3 26 1
2 0_0603_5%
D_V S Y NC
D _ HS Y NC
29
D_V S Y NC
29
R57
2.2K_0402_5%
C3 00
5P_0402_50V8C
2.2K_0402_5%
2
Place R325,R326,C300,C301 cloce to JP30 (Docking Conn.)
+3VS
11/06 update
C 301
5P_0402_50V8C
CRT_D DC_CLK
CR T_DDC_DATA
C
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

CRT Connector
Size
D ocument Number
Rev
0 .9
LA -5251P
Dat e:

5
Sheet
18
of
47
+3VS
6/16 update
+5VALW
2
+5VALW
R 332
100K_0201_5%
14
Q16B
2N7002DWH 2N SOT363-6
2N7002DWH 2N SOT363-6
Q16A
5
14
DP D_CTRLCLK
DP D_CTRLCLK
Q14A
Q14B
2N7002DWH 2N SOT363-6 2N7002DWH 2N SOT363-6
1
6
3
4
DPD_C_A UX
D DC_E N
R 348
1M_0402_5%
D DC_E N
2 0_0201_5%
R3 46 1
DPD_C_AUX#
DC AD
DPD_CTRLDATA
D DC_E N
DP _EN
Q13A
Q13B
2N7002DWH 2N SOT363-6 2N7002DWH 2N SOT363-6
DPD_CTRLDA TA 1
6
3
4
R3 43
10K_0201_5%
R3 42
10K_0201_5%
08/28 update
R3 37
100K_0201_5%
+3VS
DP _EN
14
+3VS
DPD_A UX#
14
DPD_AUX
DPD_A UX
2N7002DWH 2N SOT363-6
Q15B
2N7002DW-7-F_SOT363-6
Q30B
R3 44
@ 100K_0201_5%
1
10U_0805_10V4Z
C3 09
0.1U_0402_16V4Z
F2
NANOSMDC050F 0.5A 13.2V POLY-FUSE

2
1
R3 49
2N7002DWH 2N SOT363-6
2N7002DW-7-F_SOT363-6
Q15A
Q30A
DP _EN
5
0_0603_5%
2
DPD_AUX#
+3VS_DP
C3 08
+3VS_DP_F
06/18 update
@ 100K_0201_5%
R3 38
6/16 update
+5VS
DPD_TXN0
DPD_TXP1
14
14
DPD_TXN1
DPD_TXP2
DPD_TXN1
DPD_TXP2
14
14
DPD_TXN2
DPD_TXP3
DPD_TXN2
DPD_TXP3
14
DPD_TXN3
DPD_TXN3
DC AD
DPD_C_AUX#
DP D_H PD_R
DPD_C_A UX
+3VS_DP
R 351
5.1M_0402_5%
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LAN0+
LAN0_shield
LAN0LAN1+
LAN1_shield
LAN1LAN2+
LAN2_shield
LAN2LAN3+
LAN3_shield
LAN3CA_DET
GND
AUX_CH+
GND
AUX_CHHP_DET
RTN
DP_PWR
DP D_H PD_R
GND
GND
GND
GND
24
23
22
21
3
2
14
14
DPD_TXN0
DPD_TXP1
R 1076
100K_0402_5%
1
DPD_TXP0
J D P1
DPD_TXP0
14
DP D_H PD
DP D_H PD
14
2N7002DWH 2N SOT363-6
Q46B
2
R 1055 @
0_0402_5%
B
MOLEX_105088-0001
C ONN@
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
5
Title

Display Port Connector
Size
D ocument Number
Rev
0 .9
LA -5251P
Dat e:

1
Sheet
19
of
47
DDI PANEL CONN.
Web camera POWER CIRCUIT

A
I NVPWR_B+
I NVPWR_B+
2 0_0603_5%
680P_0402_50V7K
2
C3 12
0_0805_5%
15
2
R3 58
15
USB20_P12
1
0_0402_5%
+5V_WEBCAM
4 WCM-2012-900T_4P
4
3 3
USB20_P12_R
USB20_N12_R
USB20_N12
1 L18
2
R3 59
INV_PWM
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
32
31
M B_DP_AUXP
MB_DP_AUXN
MB_DP_AUXP
MB_DP_AUXN
1
R 365
2
0_0402_5%
MB_DP_HPD
+LCD VDD
D
+3VS
Q18A
2N7002DW-T/R7_SOT363-6
47K_0402_5%
R 371
2
OUT
2 1M_0402_5%
1
2
0.1U_0402_16V4Z
1
C3 24
4.7U_0805_10V4Z
4.7U_0805_10V4Z
@ C 325
IN
USB20_P12_R
R 377
100K_0402_1%
R6 16
Q20
DTC124EKAT146_SC59-3
C 323
0.1U_0402_16V4Z
GND
E NA VDD
1
VP
CH2
VN
C3 22
14
WEBCAM_ON_R
D12
CH1
R3 70 1
220P_0402_25V
Q18B
2N7002DW-T/R7_SOT363-6
2
G
3 2
6
11/11 update
C 665
100K_0402_5%
+3VS
Q19
3 SI2301CDS-T1-GE3 1P SOT23-3
MB_DP_AUXN
M B_DP_AUXP
R3 69
100_0201_1%
R5 69
USB20_N12_R
+LCDV DD
22_0402_5%
LCD POWER CIRCUIT

MB_HPD
R 372
5
5
C ONN@ ACES_88242-3001_30P
1
0_0402_5%
MB_DP_DATA0_P 5
MB_DP_DATA0_N 5
15
J EDP1
R 374 2
1 0_0402_5%
INV_PWM
WEBCAM_ON R 375 2
1 WEBCAM_ON_R
0_0402_5%
+5V_KL
D ISP_OFF#
15 ALS_EN#
14 INV_PWM
WEBCAM_ON
06/16 update
07/03 update
680P_0402_50V7K
@ 47P_0402_50V8J
R3 76
C3 19
C3 11
C3 18
C 310
680P_0402_50V7K
C3 17
R3 04
C3 14
C3 16
@ 47P_0402_50V8J
2
4.7U_0805_10V4Z
+3VS
+5V_WEBCAM
Close to JEDP1.24
0.1U_0402_16V4Z
+LCD VDD
0.01U_0402_16V7K
+LCD VDD
+5VS
47P_0402_50V8J
C 313
+3VS
B+
L17
HCB2012KF-121T50_0805
1
2
R6 13
100K_0402_5%
@ CM1213-02SR_SOT143-4
100K_0402_5%
+5VS
06/16 update
Keyboard Light circuit

Q78
@ SI2301CDS-T1-GE3 1P SOT23-3
1
S
3
1
@ 0.22U_0603_25V7K
C 976
@ 1U_0603_25V7K
R 1106
+3VS
C3 26
13
D57
D ISP_OFF#
LI D_SW#
LI D_SW#
28,30
ENABLT
ENABLT
14
2K_0402_5%
R3 57
100K_0402_1%
2
2
680P_0402_50V7K
1
1
LID_SW#_ISO#
08/25 update
R3 62
D ISP_OFF#
100K_0402_5%
2
@ 0_0402_5%
2N7002DWH 2N SOT363-6
Q56A
2N7002DWH 2N SOT363-6
Q56B
R3 56
@ 10K_0402_5%
@ 100K_0402_1%
R3 61
R 366
LI D_SW#
2
G
@ 220K_0402_5%
Place R366 close to Q56.
Q23
SI2301CDS-T1-GE3 1P SOT23-3
I NVPWR_B+
C9 75
R 1105
B+
+5VS +5VS
R 149
+3VALW
+5V_KL
10K_0402_5%
09/28 update
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title
LCD CONN & Q-Switch & GPIO Ext.

Size
D ocument Number
Rev
0.9
L A-5251P
Dat e:

5
Sheet
20
of
47
+1.0VM_LAN
+3VM
+1.05VM_LAN
+3VM_LAN
R3 85
0_0603_5%
1
2
R 382
0_0603_5%
1
2
C3 27
0.1U_0402_16V4Z
C3 34
C3 35
C41
C3 28
2
0.1U_0402_16V4Z
330U_B2_2VM_R15M
2
10U_0805_10V4Z
A
10U_0805_6.3V6M
04/20 Cancel +1.0VM_LAN from +3VM reserve

circuit for LAN Layout Placement issue improve.
05/06 Install C41(330U_2V_B2_15mR) by HP request.
07/01 update
0.1U_0402_16V7K
0_0201_5%
LAN_S M_CLK
2
LAN_SM_DAT
2
0_0201_5%
13
13
SML0CLK
SML0DATA
R3 90 1
R3 91 1
15
L AN_DIS#
R3 94 1
0_0201_5%
LA N_P HYPC_R
LAN_MDI1P
L AN_MDI1N
38
39
PETp
PETn
MDI_PLUS2
MDI_MINUS2
20
21
LAN_MDI2P
L AN_MDI2N
41
42
PERp
PERn
MDI_PLUS3
MDI_MINUS3
23
24
LAN_MDI3P
L AN_MDI3N
28
31
SMB_CLK
SMB_DATA
XTAL1
XTAL2
C 411
XTAL1_C
XTAL1
1
R4 03
1
R4 04
Y4
1
XTAL2
2
1K_0201_5%
2
3.01K_0402_1%
32
34
33
35
LED0
LED1
LED2
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TCK
9
10
XTAL_OUT
XTAL_IN
30
TEST_EN
12
LED
26
27
25
R3 92 1
R3 93 1
+3.3V M_LAN_OUT
VDD3P3_15
VDD3P3_19
VDD3P3_29
15
19
29
+3.3VM_LAN_OUT_R 1
R 395
VDD1P0_47
VDD1P0_46
VDD1P0_37
47
46
37
1
R 396
2
0_0603_5%
VDD1P0_43
43
VDD1P0_11
11
+1.0VM_LAN3 1
R 399
+1.0VM_LAN2 1
R 401
2
0_0603_5%
2
0_0603_5%
VDD1P0_40
VDD1P0_22
VDD1P0_16
VDD1P0_8
40
22
16
8
C3 42
33P_0402_50V8J
CTRL_1P0
VSS_EPAD
49
RBIAS
2
C3 41
33P_0402_50V8J
RSVD_VCC3P3_1
RSVD_VCC3P3_2
VDD3P3_IN
1
2
5
LAN_DISABLE_N
JTAG
2
2
25MHZ_20PF_7A25000012
6
2 3.01K_0402_1%
2 3.01K_0402_1%
LANLINK _STATUS#
+3VM_LAN
+3VM_LAN
1
2
0_0603_5%
2
+3VM_LAN_LED
C 338
1U_0603_10V4Z
R3 98 1
R4 00 1
@10K_0201_5%
10P_0402_50V8J
P AD T85
P AD T86
LAN_JTAG_TMS
LAN_J TAG_TCK
@ 10K_0201_5%
+3VM_LAN
LANLINK _STATUS#
LAN_A CT#
R 262 1
2
0_0201_5%
Q9A
VCT
VDD3P3_OUT
R2 61 1
2
@0_0201_5%
LA NLINK_R#
LA NLINK_R#
2N7002DW T/R7_SOT-363-6
15,30
L AN_DIS#
R 397
100K_0402_5%
Q 22
+1.0VM_LAN
15,18,29
Q9B
2N7002DW T/R7_SOT-363-6
PREP#
1
R 402
LAN_CTRL_10
2
0_0603_5%
T115
P AD
04/20 Test Point reserve.
WG82577LM QLMG A3 QFN 48P
1
TAIMAG IH-037-2
L AN_MDI0N 12
T47
TD4-
MX4-
13
MDO0-
MDO0-
10K_0402_5%
R4 05
29
J RJ 45
LAN_MDI1P 8
1
C3 49
TRM_CTR
2
0.1U_0402_16V7K
L AN_MDI2N
TD4+
TCT4
TD3-
TD3+
MX4+
14
MDO0+
MCT4
15
M CT0
MX3-
16
MDO1-
MX3+
17
MDO1+
M CT1
TCT3
MCT3
18
TD2-
MX2-
19
MDO0+
29
C3 47 1
0.01U_0402_50V7K
MDO1-
MDO1+
29
R 409
75_0402_1%
1
2
LAN_ACT#
LAN_A CT#
R 406 1
2
29
29
C3 50 1
2
0.01U_0402_50V7K
MDO2MDO2- 29
R 412
75_0402_1%
1
2
2 300_0603_5%
C3 45 @
680P_0402_50V7K
+3VM_LAN
1
TRM_CTR
2
10
0.1U_0402_16V7K
L AN_MDI1N
9
1:1
LAN_MDI0P 11
1
C3 46
+3VM_LAN_LED
04/25 Delete TRM_CT,R407,R408. leave U14-6 NC.

Add 1uF C339 decoupling cap to TRM_CTR.
1:1
11/03 update
M/E Design change
DC234003O00(TYCO_2006067-1_13P) to
DC020910201(FOX_JM36111-R2225-7H_13P-T)
+3VM_LAN
10/01 update
R 410
10K_0402_5%
TD2+
TRM_CTR
2
0.1U_0402_16V7K
L AN_MDI3N
TCT2
LAN_MDI3P
TD1+
TCT1
TD1-
MX2+
20
MDO2+
MCT2
21
M CT2
MX1-
22
C3 53 1
2
0.01U_0402_50V7K
MDO3MDO3- 29
MX1+
23
MDO3+
MCT1
24
M CT3
MDO2+
29
R 413
75_0402_1%
1
2
29
LANLINK_STATUS#
LANLINK _STATUS#
R4 11
PR4-
PR4+
MDO1-
PR2-
MDO2-
PR3-
MDO2+
PR3+
MDO1+
PR2+
MDO0-
PR1-
MDO0+
PR1+
Green LED+
2
C 351 @
680P_0402_50V7K
10
TRM_CTR
2
0.1U_0402_16V7K
C 339
MDO3+
C3 55 1
0.01U_0402_50V7K
29
2
1U_0603_10V4Z
1000P_1808_3KV7K
D13
PJSOT05C_SOT23-3
Issued Date
Compal Secret Data

2008/09/15
Deciphered Date
2010/12/31
2
14
15
SHLD1
SHLD1
Green LED-
R4 14
75_0402_1%
1
2
C 348
DETECT PIN1
1
C3 54
1:1
13
FOX_JM36111-R2225-7H
CONN@
Yellow LED-
MDO3+
2 300_0603_5%
Yellow LED+
12
MDO3-
+3VM_LAN_LED
1:1
1
C3 52
LAN_MDI2P
11
PCIE_PTX_C_DRX_P6
PCIE_PTX_C_DRX_N6
LAN_MDI0P
L AN_MDI0N
17
18
13
13
0.1U_0402_16V7K
C3 36 1
PCIE_PRX_C_DTX_P6
2
C3 37 1
PCIE_PRX_C_DTX_N6
2
13
14
MDI_PLUS1
MDI_MINUS1
PCIE_PRX_DTX_P6
PCIE_PRX_DTX_N6
MDI_PLUS0
MDI_MINUS0
PE_CLKP
PE_CLKN
13
13
CLK_REQ_N
PE_RST_N
44
45
CLK_PCIE_LAN
CLK_PCIE_LAN#
48
36
15
15
U14
2 @0_0201_5%
PLT_RST#_LAN
2
0_0201_5%
R3 88 1
R3 89 1
MDI
15 CLK_PCIE_LAN_REQ#
4,12,15,22,23,31 PLT_RST#
2 0_0402_5%
PCIE
R4 07 1
SMBUS
CLK_PCIE_LAN_REQ1#
13
Title

Intel 82566 Nineveh
Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:
Sheet
5
21
of
47
B+_DEBUG_R
+3V_WLAN
+1.5VS
+3V_WLAN
C3 61
4.7U_0805_10V4Z
C3 60
0.1U_0402_16V4Z
C3 59
0.01U_0402_16V7K
C3 58
4.7U_0805_10V4Z
C3 57
0.1U_0402_16V4Z
C3 56
0.01U_0402_16V7K
39P_0402_50V8J
1
C6 29
@
1
C4 43
@
P CI _SERR#_R
W W _ LED#
8051RX_R
8051TX_R
DEBUG_KBCRST_R
8051_RECOVER#_R
R4 53
R4 33
R4 37
R4 32
R4 21
R4 31
R4 41
1
1
1
1
1
1
1
2
2
2
2
2
2
2
0_0402_5%
@ 0_0201_5%
@ 0_0201_5%
@ 0_0201_5%
@ 0_0201_5%
@ 0_0201_5%
@ 0_0201_5%
DEG_FRA ME#
D EBUG_AD3
D EBUG_AD2
D EBUG_AD1
D EBUG_AD0
R4 15
R4 16
R4 17
R4 18
R4 19
1
1
1
1
1
2
2
2
2
2
PCI_RST#_R
W W _ LED#
R4 20
R4 75
1
1
2
2
39P_0402_50V8J
P C I_SERR#
S I RQ
8051RX
8051TX
DEBUG_KBCRST
8051_RECOV ER#
B+_DEBUG
P C I_SERR# 15,25,30,31
S I RQ 12,25,30,31
8051RX 30,31
8051TX 30,31
DEBUG_KBCRST 31,36
8051_RECOVER# 30,31
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
LPC_LFRAME# 12,30,31
LPC_LAD3 12,30,31
LPC_LAD2 12,30,31
LPC_LAD1 12,30,31
LPC_LAD0 12,30,31
0_0201_5%
0_0201_5%
W L_LED#
PCI_RST#
07/01 update
15,25
+3V_WLAN
JP6
14,23
+3VALW
R 422
C 362
@ 10K_0201_5%
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
3
1 R4 25
2
220K_0402_1%
+3V_WLAN
MC2_DISABLE
15,31
Q24
SI2305DS-T1-E3_SOT23-3
1
R 119
C LKREQ_WLAN#
13
13
10/19 update
2
2
30
13
CLK_PCIE_MCARD#
CLK_PCIE_MCARD
XMIT_D_OFF#
D14
1
2
0_0603_5%
Close to C443
R4 77
PCI_RST#_R
C LK_PCI_DEBUG
1
2
0_0402_5%
R4 23 1
2 0_0201_5% PCIE_PRX_DTX_N4_R
R4 24 1
2 0_0201_5% PCIE_PRX_DTX_P4_R
C LK_PCI_DB
13
13
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
13
13
PCIE_PTX_C_DRX_N4
PCIE_PTX_C_DRX_P4
+3V_WLAN
WLAN_TRANSMIT_OFF#
15
13
13
13
C L_CLK1
CL_DA TA1
CL_RST#1
C L_CLK1
CL_DATA1
CL_RST1#
R4 26
R4 27
R4 28
1 0_0201_5% C L_CLK1-R
1 0_0201_5% CL_DATA 1-R
1 0_0201_5% CL_RST1#-R
B+_DEBUG_R
2
2
2
1
3
5
7
9
11
13
15
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
2
4
6
8
10
12
14
16
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
53
54
55
56
C LK_PCI_DEBUG
1
@ C 539
12P_0402_50V8J
+1.5VS
DEG_FRA ME#
D EBUG_AD3
D EBUG_AD2
D EBUG_AD1
D EBUG_AD0
XMIT_D_OFF#
PLT_RST#
4,12,15,21,23,31
8051TX_R
8051RX_R
10/13 update
W W _ LED#
W L_LED#
P CI _SERR#_R
W L_LED#
28
G1
G2
G3
G3
07/01 update
8051_RECOVER#_R
DEBUG_KBCRST_R
@ 0.1U_0402_10V6K
PCIE_WA KE#
PCIE_WAKE#
FOX_AS0B226-S99N-7F
C ONN@
06/25 Del JHDD1 and JHDD2 Cable design. Add JHDD3 B to B directly connect design.
J H DD3
J ODD1
CONN@ FOX_LM25163-BA01-9H
2 C3 65
2 C3 67
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
SA TA_PRX_C_DTX_N0
SATA_PRX_C_DTX_P0
0.01U_0402_16V7K 1
0.01U_0402_16V7K 1
2 C3 69
2 C3 70
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N0
12
12
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
12
12
+5VS
GND
A+
AGND
BB+
GND
1
2
3
4
5
6
7
DP
V5
V5
MD
GND
GND
8
9
10
11
12
13
+3VS
+3VS
C 372
0.1U_0402_16V4Z
1
1
C3 73
C3 74
2
10U_0805_10V4Z
0.1U_0402_16V4Z
1
C 375
2
0.1U_0402_16V4Z
SATA_PTX_C_DRX_P1
SA TA_PTX_C_DRX_N1
0.01U_0402_16V7K 1
0.01U_0402_16V7K 1
2 C3 63
2 C3 64
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
SA TA_PRX_C_DTX_N1
SATA_PRX_C_DTX_P1
0.01U_0402_16V7K 1
0.01U_0402_16V7K 1
2 C3 66
2 C3 68
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
SATA_PTX_DRX_P1
SATA_PTX_DRX_N1
12
12
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
12
12
2
R 429 1
2 0_0201_5%
ODD_DET#
1
+5VS
15
C3 79
10U_0805_10V4Z
8
9
10
11
12
13
14
15
16
0.01U_0402_16V7K 1
0.01U_0402_16V7K 1
C3 78
10U_0805_10V4Z
V33
V33
GND
GND
V5
V5
R
Rsv1
Rsv2
SATA_PTX_C_DRX_P0
SA TA_PTX_C_DRX_N0
C3 77
1U_0603_10V4Z
GND
GND
GND
1
2
3
4
5
6
7
C3 76
0.1U_0402_16V4Z
17
18
19
GND
A+
AGND
BB+
GND
C 371 @
0.1U_0402_16V4Z
C ONN@TYCO_2023233-3_NR
7/1 Update JODD1 PCB Footprint from ALLTO_C18522-11303-L_13P_NR to TYCO_2023233-3_13P_NR
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

WLAN/ODD/HDD
Size
D ocument Number
Rev
0.9
L A-5251P
Dat e:

5
Sheet
22
of
47
D16
15,28
J P8
+ 3V_WWAN
PAD
T90
53
GND1
W WAN_DET#
W WAN_DET#
30
1
R 1079
MC1_DISABLE
W W _ LED#
W W _ LED#
C 390
GND
VPP
I/O
DET
VCC
RST
CLK
4.7U_0805_10V4Z
PCIE _PRX_DTX_N2
PCIE_PRX_DTX_P2
D15
27
28
U17
1 0.1U_0402_16V4Z
C 399 2
1 0.1U_0402_16V4Z
C 400 2
+3VALW
1 0.1U_0402_16V4Z
NV _DQ0
NV _DQ1
NV _DQ2
NV _DQ3
NV _DQ4
NV _DQ5
NV _DQ6
NV _DQ7
NV _DQ8
NV _DQ9
N V_DQ10
N V_DQ11
N V_DQ12
N V_DQ13
N V_DQ14
N V_DQ15
15
N V_CLE
N V_CLE
15
NV_ALE
NV_A LE
6
7
45
46
12
13
51
52
28
29
67
68
34
35
73
74
18
57
19
58
60
21
NV _RE#_WR#1
NV _RE#_WR#0
NAND_DETECT#
NAND_DETECT#
5
8
11
14
17
20
23
26
27
30
33
36
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CLE_0
CLE_1
ALE_0
ALE_1
W/R_1#/RE_1#
W/R_0#/RE_0#
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
38
39
78
VCCQ_1
VCCQ_2
VCCQ_3
1
2
3
40
41
42
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
4,12,15,21,22,31
C ONN@
+3VALW
3.3Vout
NC
3
5
+3VS_PEC
15
+3V_PEC
AUX_OUT
P LT_RST#
1 100K_0201_5%
20
SHDN#
STBY#
NC
10
CPPE#
GND
GND
21
PLT_RST#
R 440
AUX_IN
SLP_S3#
CPP E#
CPPE#
SYSRST#
OC#
+3V_PEC
B
PERST#
CPUSB#
19
8
PE RST#
16
+1.5VS_PEC
RCLKEN
1
08/28 update
C5 66
+3VS_PEC
TPS2231MRGPR-2 QFN 20P
@ 22U_0805_6.3VAM
C
DOS_0#
DOS_0
DOS_1#
DOS_1
9
10
31
32
TP_NV_DOS_0#
TP_NV_DOS_1#
T91 P A D
NV_DQS0
T92 P A D
NV_DQS1
RFU_1
RFU_2
RFU_3
RFU_4
15
16
63
64
TP_NV_RFU_1
TP_NV_RFU_2
TP_NV_RFU_3
TP_NV_RFU_4
T93
T94
T95
T96
CE_0#
CE_2#
CE_1#
CE_3#
CE_4#
CE_6#
CE_5#
CE_7#
24
25
22
61
4
43
37
76
CK_0#
CK_0/WE_0#
CK_1#
CK_1/WE_1#
48
49
70
71
R/B#
WP#
15
15
PAD
PAD
PAD
PAD
N V_CE0#
NV_CE0#
15
N V_CE1#
NV_CE1#
15
N V_CE2#
NV_CE2#
15
N V_CE3#
NV_CE3#
15
TP_NV_CK_0#
TP_NV_CK_1#
T97 P A D
NV_WE#_CK0
T98 P A D
NV_WE#_CK1
54
55
TP_NV _WP0#
N V_RB#
T99 P A D
VREF
77
TP_NV_VREF
T100 P A D
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
44
47
50
53
56
59
62
65
66
69
72
75
15
15
15
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
@ NVRAM Connector
+1.5VS_PEC
C4 02
JP11
12
+1.8VS
11
13
4.7U_0805_10V4Z
+
2
3.3Vin
NC
1.5Vout
NC
C4 01
C 571
15
15
+3VS
2 0_0603_5%
Nee d Keep
@ 100U_B2_6.3VM_R45M
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
15
2@ 0_0603_5%
R5 62 1
2
4
18
+V_NVRAM_VCCQ
R5 61 1
1.5Vin
NC
0.1U_0402_16V7K
+3VS
12
14
17
NC_C P#
+3V_NVRAM
29
30
+3VS
15
2@ 0_0603_5%
GND
GND
+1.5VS
14,29,30,32,33,35,37,38
R5 67 1
GND
GND
SANTA_130853-1_RT
C ONN@
C 398
2 0.1U_0402_16V7K PCIE_PRX_DTX_N2_R
2 0.1U_0402_16V7K PCIE_PRX_DTX_P2_R
+ 3V_WWAN
C 394 2
C 403 1
C 404 1
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
4.7U_0805_10V4Z
PCIE_PTX_C_DRX_N2
PCIE_PTX_C_DRX_P2
C 397
PCIE_PRX_DTX_N2
PCIE_PRX_DTX_P2
13
13
0.1U_0402_16V7K
SANTA_135306-3
UI M_PWR
CLK_PCIE_EXP#
CLK_PCIE_EXP
13
13
C 396
@ 47K_0402_5%
13
13
4.7U_0805_10V4Z
R4 34
CLKREQ_EXP#
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
C 395
0.1U_0402_16V4Z
8
9
+3V_PEC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.1U_0402_16V7K
GND
GND
13
DAN217T146_SC59-3
3
1
2
PCIE_WAKE#_R
CLK REQ_EXP#
CPP E#
CLK_P CIE_EXP#
CLK_PCIE_EXP
UI M_PWR
UIM_RST
UIM_CLK
1
2
3
C3 87
U SB20_N4_R
USB20_P 4_R
+3VS_PEC
2
1
0_0805_5%
+ 3V_WWAN
C3 92
@ 39P_0402_50V8J
PCIE_WAKE#
PE RST#
0.1U_0402_16V4Z
C3 86
2 0_0201_5%
2 0_0201_5%
R4 39
+1.5VS_PEC
0_0201_5%
+1.5VS_PEC
1
2
PCIE_WA KE#
R 1080
4.7U_0805_10V4Z
Vp
CH2 CH3
18P_0402_50V8J
14,22
+ 3V_WWAN
JP10
4
5
6
7
UIM _VPP
UIM_DATA
1
C3 89
Vn
C 385
NC_C P#
J3
PAD-OPEN 4x4m
S DIO(BR) NUP4301MR6T1 TSOP-6

U15
@
1 CH1 CH4 6
@ 39P_0402_50V8J
C3 88
28
R4 35 1
R4 36 1
2
220K_0402_1%
USB20_N9 15
USB20_P9 15
+ 3V_WWAN
USB20_N4
USB20_P4
C9 33
1000P_0402_50V7K
Q77
SI2305DS-T1-E3_SOT23-3
0.01U_0402_16V7K
15
15
R 1077
15
+3V_WWAN
C3 91
Place C933 between R1077.1 and R1079.2 for limit inrush current.
@ 10K_0402_5%
09/11 update
M_WXMIT_OFF#
MOLEX_67910-5700
CONN@
JEXP1
+3VALW
07/02 update
54
UI M_PWR
UIM_DATA
UIM_CLK
UIM_RST
UIM _VPP
GND2
M_WXMIT_OFF#
+ 3V_WWAN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
T88
T89
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
PAD
PAD
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
WWAN_TRANSMIT_OFF#
Title

WWAN/NAND
Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

5
Sheet
23
of
47
Rear side USB conn.
R 352 1
07/17 update
(2A,100mils ,Via NO.=4)
+5VALW
+USB_VCCA
U18
C4 05
4.7U_0805_10V4Z
A
1
2
3
4
GND
IN
IN
EN#
OUT
OUT
OUT
OC#
8
7
6
5
220U_6.3V_M
1
+
C4 06
14,29,33,39
SLP_S4#
+5VALW
C4 08
CH1
CH2
VN
VP
USB20_L_N2
2
1
+5VALW
@ CM1213-02SR_SOT143-4
4
3
2
1
USB20_L_N0
USB20_L_P0
10/13 update
D18
USB20_L_P0
15
USB20_N0
15
USB20_P2
USB20_P0
USB20_N0
CH1
CH2
VN
VP
G5
G3
G1
VSS
D1+
D1VCC
13
11
9
8
7
6
5
USB20_N2
15
USB20_N1
15
USB20_P1
USB20_P2
USB20_N2
+5VALW
USB20_L_P2
R 360 1
1
USB20_P1
2 0_0402_5%
R 443 1
USB20_L_N1
USB20_L_P1
4 4
3 3
L19 @ WCM-2012-900T_4P
R 355 1
2 0_0402_5%
Need Correct the Symbol and

reverse the connection.
2 0_0402_5%
USB20_L_N2
4 4
3 3
L9 @ WCM-2012-900T_4P
R 353 1
2 0_0402_5%
USB20_N1
09/01 update
@ CM1213-02SR_SOT143-4
USB20_L_N2
USB20_L_P2
C ONN@
S UYIN_020122GR008S51CZL
USB20_L_P2
15
06/18 update
USB20_L_P0
R 354 1
G6
G4
G2
VSS
D0+
D0VCC
2 0_0402_5%
USB20_L_N0
4 4
3 3
L8 @ WCM-2012-900T_4P
R 350 1
2 0_0402_5%
JP13
14
12
10
0.1U_0402_16V4Z
D 19
2
10K_0201_5%
USB20_L_N0
C4 07
R 442
USB20_P0
1000P_0402_50V7K
G547F1P81U MSOP 8P
15
15
USB20_P8
15
USB20_N8
USB20_P8
USB20_N8
2 0_0402_5%
USB20_P 8_R
U SB20_N8_R
4 4
3 3
L26 @ WCM-2012-900T_4P
R 444 1
2 0_0402_5%
USB+power conn.(Left Side)-debug port
BT Connector
0.01U_0402_16V7K
OC1#
OUT1
OUT2
OC2#
1
C 416
1
C 417
150U_B2_6.3VM_R35M 2
C 418
11/03 update
2
1000P_0402_50V7K
1
2
3
4
5
6
7
8
C5 06
C4 09
10K_0201_5%
USB20_N8
C 410
470_0402_5%
CONN@
1
2
3
4
GND
GND
GND
GND
@ 0.1U_0402_16V4Z
15
USB20_P8
R 447
1
BT_OFF
2
Q55B
2
2
0.1U_0402_16V4Z
10U_0805_10V4Z
220K_0402_1%
09/21 update
2N7002DWH 2N SOT363-6
D17
SUYIN_020173MR004S582ZL
Close to U33 pin3 and pin4
D20
USB20_L_N1
2
1
CH1
CH2
USB20_L_P1
VN
VP
+5VALW
PJDLC05_SOT23-3
USB20_L_N1
USB20_L_P1
1
+
G546A1P1UF_SO8
R4 46
C ONN@ ACES_87212-05G0_5P
JP14
0.1U_0402_16V4Z
2.5A normal with 3.0A Max Peak(1ms)
2
1
+U SB_VCCC
8
7
6
5
R1 35
GND
IN
EN1#
EN2#
470K_0402_5%
C7
SLP_S 4_R
28
SLP_S4#
BT_LED
U33
1
2
3
4
R11
14,29,33,39
USB20_P 8_R
U SB20_N8_R
+3VAUX_BT
Q26
3
1
+3VAUX_BT
1
2
3
4
5
2
1
4.7U_0805_10V4Z
+3VALW
JP12
R 501
100K_0402_5%
R4 45
100K_0402_5%
C5 04
B
+5VALW
+5VALW
@ CM1213-02SR_SOT143-4
ACCELEROMETER
+3VS_ACL
15 USB20_N3
15 USB20_P3
+USB_VCCB
U20
C4 15
4.7U_0805_10V4Z
1
2
3
4
GND
IN
IN
EN#
OUT
OUT
OUT
OC#
8
7
6
5
G547F1P81U MSOP 8P
C 620
R4 48
+5VALW
+USB_VCCB
1000P_0402_50V7K
0.1U_0402_16V4Z
10K_0201_5%
C 621
1
2
3
4
5
6
7
8
9
10
11
12
13
GND
A+
AGND
BB+
GND
R4 49
0_0603_5%
2
C 420
07/17 update
(2A,100mils ,Via NO.=4)
C ONN@
10U_0805_6.3V6M
+5VALW
JP15
+3VS_ACL_IO
C 419
Left side USB conn.(Extra-USB)
+3VS_ACL
0.1U_0402_16V4Z
+3VS
U21
LIS302DL
DP
V5
V5
MD
GND
GND
+3VS_ACL_IO
+3VS_ACL
1
6
VDD_IO
VDD
15
8
9
INT 1
INT 2
ACCEL_INT#
4,9,10,11,13
4,9,10,11,13
SMB_DATA_S3
SMB_CLK_S3
+3VS_ACL
R4 50 2
P-TWO_121057-13251_13P_NR-T
12
13
14
1 10K_0201_5%
GND
GND
GND
GND
2
4
5
10
SDO
SDA / SDI / SDO
SCL / SPC
RSVD
CS
RSVD
3
11
+3VS_ACL
HP302DLTR8_LGA14_3X5
SLP_S4#
<BOM Structure>
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title
USB & BT Connector & Acclerometer

Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

5
Sheet
24
of
47
+3VS
S D_CARD_DET#
SCVCC5EN#
SCVCC3EN#
83
84
S CV CC5EN#
S CV CC3EN#
XI
XO
95
96
R5C832XI
R5C832XO
+3VS
2 0_0201_5%
1
R4 62
+ SC_PWR
15
15
+3VS
C
2
10K_0402_5%
SC_RST
S C _CLK_R
SC_DATA
S C_C D#
SCSENSE
89
88
87
86
85
SCRST
SCCLK
SCIO
SCCD#
SCSENSE
112
113
P CI_PIRQE#
P CI_PIRQG#
R4 65 1
1
R4 66
REXT
VREF
2 10K_0201_5%
2
100K_0201_5%
UDIO0/SRIRQ#
UDIO1
UDIO2
UDIO3
UDIO4
UDIO5
INTA#
INTB#
77
81
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HWSPND#
TEST
98
101
105
109
AGND
AGND
AGND
AGND
SDCLK_MMCCLK
SDWP#
MDIO04
SDPWR0
31
MDIO05
SDPWR1
MDIO06
SDLED#
MSPWR
MMCLED#
MSLED#
MDIO08
SDCCMD
MMCCMD
MSBS
MDIO09
SDCCLK
MMCCLK
MSCCLK
XDRE#
MDIO10
SDCDAT0
MMCDAT0
MSCDAT0
XDCDAT0
MDIO11
SDCDAT1
MMCDAT1
MSCDAT1
XDCDAT1
MDIO12
SDCDAT2
MMCDAT2
MSCDAT2
XDCDAT2
MDIO13
SDCDAT3
MMCDAT3
MSCDAT3
XDCDAT3
MMCDAT4
XDCDAT4
MDIO15
MMCDAT5
XDCDAT5
MDIO16
MMCDAT6
XDCDAT6
MDIO17
MMCDAT7
XDCDAT7
MDIO18
XDCLE
MDIO19
XDALE
S I RQ 12,22,30,31
T107 P A D
T108 P A D
2 @ 15K_0402_5%
R 468 2
1 15K_0402_5%
SC_DATA
SC_DATA
C 449 1
2 12P_0402_50V8J
SC_RST
C 450 1
2 12P_0402_50V8J
S C_CLK
C 451 1
2 12P_0402_50V8J
1
2
C9 67
100K_0402_5%
2N7002DWH 2N SOT363-6
R 1091
2
47K_0402_5%
C9 69
1U_0402_6.3V4Z
S CV CC5EN#
Q 57
AP2301GN-HF_SOT23-3
R 1089
Q51A
+3VS
1U_0402_6.3V4Z
+5VS
100K_0402_5%
1
1
1
1
2
2
2
2
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
IEEE1394_TPBN0_R
IEEE1394_TPBP0_R
IEEE1394_TPAN0_R
IEEE1394_TPAP0_R
1
2
3
4
TPBTPB+
TPATPA+
Function set pin define

GND
GND
GND
GND
UDIO3
5
6
7
8
UDIO4
Pull-down Pull-down
SUYIN_020115FB004S512ZL
CONN@
UDIO5
Pull-up
Function
Disable MS,xD Card,serial ROM
Pull-up
Pull-up Pull-down
Enable serial EEPROM
Pull-up
Pull-up
Ensable MS,xD Card,disable serial ROM
Pull-up
UDIO5
UDIO3
UDIO4
R4 73 1
R4 79 1
R4 82 1
2 100K_0201_5%
2 10K_0201_5%
2 10K_0201_5%
+3VS
IEEE 1394_TPBIAS0
1
@
R 464 1
S C_CLK
+5VS
1U_0402_6.3V4Z
C4 55
0.33U_0603_16V4Z
ACES_85201-1005N
C ONN@
2 @ 15K_0402_5%
C4 54
0.01U_0402_16V7K
0.1U_0402_16V4Z
1 @ 1N4148WS-7-F_SOD323-2
R 471
R 472
R 474
R 476
2
S C_C D#
1
C4 53
R 463 1
IEEE1394_TPBN0
IEE E1394_TPBP0
IEEE1394_TPAN0
IEE E1394_TPAP0
D56
SC_RST
1 C9 68
R 1090
R4 81
56.2_0402_1%
S C_CLK
SC_DATA
SC_DATA
11/13 update
2N7002DWH 2N SOT363-6
R 470
56.2_0402_1%
+S C_PWR
1 @ 1N4148WS-7-F_SOD323-2
+5VS
Q51B
R 467
5.1K_0402_1%
+S C_PWR
SC_RST
Q28
Q27
AP2309AGN-HF_SOT23-3 AP2301GN-HF_SOT23-3
R4 80
56.2_0402_1%
1
2
3
4
5
6
7
8
9
10
11
12
D55
C4 48
1U_0402_6.3V4Z
8
20
35
47
61
80
93
94
115
128
R 469
56.2_0402_1%
1
2
3
4
5
6
7
8
9
10
GND
GND
S C_CLK
S CV CC3EN#
100K_0402_5%
+3VS
JP37
1 @ 1N4148WS-7-F_SOD323-2
+ SC_PWR
S I RQ
TP_UDIO1
TP_UDIO2
UDIO3
UDIO4
UDIO5
+S C_PWR
XDWE#
MDIO14
R 1088
C 452
270P_0402_50V7K
JP16
07/01 update
XDLED#
MSEXTCK
S CV CC3EN#
D54
XDPWR
XDWP#
+3VS
SC_RST
04/23 Add Q28 to prevent +5VS from leaking through Q27.
R5C835-TQFP128P_TQFP128_14X14
SMART Card Connector
XDR/B#
MMCPWR
MDIO07
31
31
31
31
100
99
76
75
74
73
72
71
XDCE#
MDIO03
R4 61
10K_0603_1%
R4 60 1
PCICLK
PCIRST#
GBRST#
CLKRUN#
PME#
SD_MMC_CMD 31
2 0_0201_5%
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MMC_D4 31
MMC_D5 31
MMC_D6 31
MMC_D7 31
T105 P A D
T106 P A D
31
C4 47
0.01U_0402_16V7K
S C_CLK
2 10K_0201_5%
2 0_0201_5%
2 10K_0201_5%
+ SC_PWR
PM_CLKRUN#
XDCD1#
14,30,31
PCI_RST#
R4 57 1
R4 58 1
R4 59 1
CLK_PCI_1394 117
116
CBS_GRST#
82
114
78
PME#
MSCD#
15,22
REQ#
GNT#
XD Card
PIN Name
XDCD0#
CLK_PCI_1394
120
119
MDIO01
MS Card
PIN Name
6 2
15
PCI_REQ2#
PCI_GNT2#
P CI_REQ2#
PCI_GNT2#
MMC Card
PIN Name
MMCCD#
15
15
P C I_PERR#
P C I_SERR#
SD Card
PIN Name
SDCD#
1
2
15
470_0402_5%
15,22,30,31
MDIO
PIN Name
MDIO00
P CI_AD22
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
SD,MMC,MS,XD muti-function pin define
MDIO02
R4 56
25
16
18
17
21
19
3
22
24
P CI_PAR
PCI_FRAM E#
P CI_ TRDY#
P CI_IRD Y#
PCI_STOP#
PCI_DEVS EL#
CBS_IDS EL
P C I_PERR#
P C I_SERR#
P C I_PAR
PCI_FRAME#
P CI_ TRDY#
P CI_IRD Y#
PCI_STOP#
PCI_DEVSEL#
S D_CARD_DET# 31
T101 P A D
T102 P A D
S D _WP 31
SDPWR0_MSPWR_XDPWR
T103 P A D
T104 P A D
XD_CE#
S D _WP
SDPWR0_MSPWR_XDPWR
XDWP#
3 IN1_LED#
TP_MSEXTCK
SD_MMC_CMD
SDCLK_MMCCLK_R R 455 1
SDDA TA0_MSDATA0
SDDA TA1_MSDATA1
SDDA TA2_MSDATA2
SDDA TA3_MSDATA3
MMC_D4
MMC_D5
MMC_D6
MMC_D7
XDCLE
XDALE
C/BE3#
C/BE2#
C/BE1#
C/BE0#
IEEE 1394_TPBIAS0
1
2
1
2
1
2
70
69
63
68
67
66
65
64
62
60
58
57
56
55
53
52
51
50
49
48
1000P_0402_50V7K
C4 29
MDIO00
MDIO01
MDIO02
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
R5C832XO
0.01U_0402_16V7K
C4 28
IEE E1394_TPBP0
IEEE1394_TPBN0
10U_0805_6.3V6M
C4 27
103
102
10U_0805_10V4Z
C4 45
TPBP0
TPBN0
0.01U_0402_16V7K
C4 44
IEE E1394_TPAP0
IEEE1394_TPAN0
+ 3V_PHY
L20
1
2
MBK2012601YZF_2P
+3VS
15P_0402_50V8J
10U_0805_10V4Z
C4 33
107
106
0.01U_0402_16V7K
C4 32
TPAP0
TPAN0
0.1U_0402_16V4Z
C4 31
110
0.01U_0402_16V7K
C4 30
TPBIAS0
0.47U_0603_16V4Z
C4 38
90
R5C832XI
Y7
24.576MHZ_16PF_1Y724576CE1C~D
C 434
1
2
+3VS
0.47U_0603_16V4Z
C4 37
15
15
15
15
15
15
+ 3V_PHY
VCC_SC
97
104
108
15P_0402_50V8J
0.01U_0402_16V7K
C4 36
54
0.01U_0402_16V7K
C4 35
PCI_CBE3#
PCI_CBE2#
PCI_CBE1#
PCI_CBE0#
VCC_MD3V
AVCC_PHY3V
AVCC_PHY3V
AVCC_PHY3V
+3VS
C4 25
15
15
15
15
2
15
26
37
79
10U_0805_10V4Z
4.7P_0402_50V8C
10_0201_5%
C4 46
R 454
@
PCI_CBE3#
PCI_CBE2#
PCI_CBE1#
PCI_CBE0#
VCC_3V
10U_0805_10V4Z
C4 40
SDCLK_MM CCLK
11
33
59
91
111
C4 24
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
VCC_ROUT
92
0.01U_0402_16V7K
VCC_RIN
0.01U_0402_16V7K
C4 41
1U_0603_6.3V6M
R5C835
6
23
38
118
0.01U_0402_16V7K
C4 39
4.7P_0402_50V8C
10_0201_5%
C4 42
R4 52
R 451
100K_0402_1%
@
CBS_GRST#
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
VCC_PCI3V
C4 23
CLK_PCI_1394
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C4 22
+3VS
A
121
122
123
124
125
126
127
1
4
5
7
9
10
12
13
14
27
28
29
30
31
32
34
36
39
40
41
42
43
44
45
46
C4 21
P CI_AD31
P CI_AD30
P CI_AD29
P CI_AD28
P CI_AD27
P CI_AD26
P CI_AD25
P CI_AD24
P CI_AD23
P CI_AD22
P CI_AD21
P CI_AD20
P CI_AD19
P CI_AD18
P CI_AD17
P CI_AD16
P CI_AD15
P CI_AD14
P CI_AD13
P CI_AD12
P CI_AD11
P CI_AD10
P C I_AD9
P C I_AD8
P C I_AD7
P C I_AD6
P C I_AD5
P C I_AD4
P C I_AD3
P C I_AD2
P C I_AD1
P C I_AD0
0.01U_0402_16V7K
U22
P C I_AD[0..31]
0.01U_0402_16V7K
15
C 426
1
2
Compal Secret Data
Issued Date
2008/03/13
Deciphered Date
2010/12/31
3
Title

1394+2 in 1 Card

Cus tom LA -5251P
Dat e:
Rev
0.9

5
Sheet
25
of
47
AMP. FOR INTERNAL SPEAKER
+V DDA_CODEC
1
+5VS
U24
2
6 1
1
2
300K_0201_5%
2 M ON O_IN_HD
0.1U_0402_16V7K_X7R
1
C 457
07/24 update
H DA_SPKR
Q29A
2N7002DWH 2N SOT363-6
2
1
2
3
100P_0402_50V8J
C4 64
SPVDD
C4 65 2
1 1U_0603_16V7_X7R
18
SPVDD
HP_EN
22
HP_DET
R 488
C4 66 2
1 10U_0805_16V6K_X5R
30
VDD
HP_INL
27
HP _L_IN
C 467 1
2 2.2U_0805_10V6K
HP _IN_L
HP_INR
26
HP _R _IN C 468 1
2 2.2U_0805_10V6K
HP _I N_R
HP_OUTL
27
H P_OUTR
27
SPKR_EN
1
C 469
L INE_OUTR
1
C4 71
1
C 472
Place R509,C498,C499 close to U24.23.
C 489 @ 10P_0402_25V8K
2
1
12
12
HDA_BIT_CLK_CODEC
12
HDA _SDOUT_CODEC
R4 99 2
33_0201_1%
HDA _ SDIN0
1
2
C4 75 0.1U_0805_25V7M
12
HDA _S Y NC_ CODEC
12
HD A_RST#_CODEC
C4 86
10U_0805_16V6K_X5R
1
2
25
R4 97
2
AVDD2
HDA_BIT_CLK_CODEC
BITCLK
HDA _SDOUT_CODEC
SDO
HDA _S D IN0_CODEC
SDI_CODEC
HDA _S Y NC_ CODEC
10
HD A_RST#_CODEC
11
PJP603
C 494 2
1 1U_0603_16V7_X7R
M ON O_IN_HD
PAD-OPEN 4x4m
C 497 2
1 10U_0805_16V6K_X5R
Place PJP603 between DGND and AGND by

3vias and 80 mils shape bridge for ESD.
+MIC_BIAS_B
+MIC_BIAS_C
SPKR_RIN-
SPKR_LIN+
ROUT+
20
R_S PK+
SPKR_LIN-
ROUT-
19
R_S PK-
LOUT+
L_SPK+
LOUT-
L_SPK-
C1P
10
C 477 2
1 1U_0603_16V7_X7R
C1N
12
BYPASS
24
C 479 1
2 0.47U_0603_16V7K_X7R
SPGND
GAIN0
31
G AIN0
R4 91
1 @ 100K_0201_5%
TML
GAIN1
32
G AIN1
R4 92
1 @ 100K_0201_5%
G AIN0
R4 85
0_0201_5%
G AIN1
R4 86
0_0201_5%
14
HPVSS
13
CPVSS
SGND
11
CPGND
21
SPGND
+5VS
+V D DA_CODEC
R5 09 1
2 15K_0402_1%
2
0.1U_0402_16V7K_X7R
C4 99 1
1U_0603_16V7_X7R
DVDD_CORE
DVDD_IO
R4 93 2
PORTA_R
41
47uF_6.3V_1.3_H1.9
D OCK_OUT_R C4 87 1
2 DO CK_OUTR
R4 94 2
1 20K_0201_5%
60.4_0402_1%
R4 95 2
DL INE_OUTR L21 2
1
PORTA_L
39
DOCK_OUT_L C4 88 1
DOCK_OUTL
PORTB_R
22
M IC1_C
GAIN1
GAIN:10dB
GAIN:12dB
GAIN:15.6dB
GAIN:21.6dB
1 20K_0201_5%
R4 96 2
DLINE_OUTL
1
60.4_0402_1%
47uF_6.3V_1.3_H1.9
C4 90 2
1 1U_0603_16V7_X7R
GAIN0
SPKR_EN
C4 98 1
M IC1
L22 2
1 MBC1608121YZF_0603 DL INE_OUT_R
D LINE_OUT_R
29
1 MBC1608121YZF_0603 DLINE_OUT_L
DLINE_OUT_L
29
27
PORTB_L
21
M IC2_C
C4 91 2
1 1U_0603_16V7_X7R
PORTC_R
24
IN T_MICR_C
C4 92 2
1 1U_0603_16V7_X7R
INT_MIC1
INT_MIC1
27
PORTC_L
23
INT_MICL_C
C4 93 2
1 1U_0603_16V7_X7R
INT_MIC2
INT_MIC2
27
PORTD_R
36
L INE_OUTR
PORTD_L
35
LINE_OUTL
PORTE_R
15
DLINE _IN _RC_R C4 95 1
PORTE_L
14
DLINE _ IN_RC_L C4 96 1
PORTF_R
17
HP _I N_R
PORTF_L
16
HP _IN_L
EAPD/ SPDIF OUT 0 or 1 / GPIO 0
47
RESET#
46
DMIC_CLK
33
CAP2
12
+5VS
9/3 update
SYNC
15
BAT54AW_SOT323-3~D
@ 10_0201_5%
1
HP_OUTR
2 @ 100K_0402_5%
TPA6047A4RHBR_QFN32_5X5
DVDD_LV
AVDD1
SPKR_RIN+
+V D DA_CODEC
A_SD# 3
A_SD#
U25
1
2
C4 78 0.1U_0805_25V7M
30
0.1U_0402_16V7K
0.1U_0402_16V7K
10U_0805_16V6K_X5R
HP_OUTL
33
1
4.7U_0805_10V4Z
C6 37
0.01U_0402_16V7K
2N7002DWH 2N SOT363-6
1
2
C4 73 0.1U_0805_25V7M
EAP D# 2
+V _CODEC_R
C4 83 C4 84 C 485
0.1U_0402_16V7K
SPKR_EN
16
U76
C 480 C4 81 C 482
2
1
1 1U_0603_16V7_X7R
23
28
2
0.022U_0603_25V4Z_X7R
2 LINE_C_OUTL
0.022U_0603_25V4Z_X7R
R 489
2
0.022U_0603_25V4Z_X7R
2 LI NE_C_OUTR
0.022U_0603_25V4Z_X7R
0_0805_5%
1
2
C4 70 0.1U_0805_25V7M
HPVDD
C ONN@
SENSE_B
38
17
ACES_85204-04001
+3VS
+V D DA_CODEC
HD A_RST#_CODEC
29
+5VALW
1
2
100K_0402_5%
1 1U_0603_16V7_X7R
REG_OUT
R 490
1 10U_0805_16V6K_X5R
L
R 703
4.7K_0201_5%
Q36A
HP_DET
HP_DET
25
C4 60 2
LINE_OUTL
1
C4 74
0.1U_0402_16V7K
27
C4 63
100P_0402_50V8J
+3VS
R5 07
20K_0201_1%
2
1
R5 00
10K_0201_1%
REG_EN
C4 58 2
SENSE_A
2N7002DWH 2N SOT363-6
+V D DA_CODEC
100P_0402_50V8J
MIC_SENSE
CPVDD
1
2
3
4
G1
G2
C 476 2
Q36B
27
C4 62
R6 14
20K_0201_1%
2
1
C4 61
100P_0402_50V8J
0.01U_0402_16V7K
08/28 update
JP17
1
2
3
4
5
6
R 487
10K_0201_5%
Q29B
2N7002DWH 2N SOT363-6
R_S PK+
R_S PKL_SPK+
L_SPK-
H DA_SPKR
C4 59
12
PJMBZ6V8_SOT23
3
R 484
C 456
0.1U_0402_16V7K
1
2
D22
2
D21
PJMBZ6V8_SOT23
3
R4 83
10K_0201_5%
PCBEEP
27
VREFFILT
28
VREFOUT-B
29
VREFOUT-C
32
40
37
18
19
20
NC
NC
NC
NC
NC
NC
2.2U_0603_10V6K_X5R
DLINE _IN_R
DLI NE_IN_L
2.2U_0603_10V6K_X5R
R5 02
R5 03
R5 04
R5 05
2
2
2
2
1
1
1
1
6.04K_0402_1%
2K_0402_5%
6.04K_0402_1%
2K_0402_5%
DOCK _LINE_IN_R
DOCK _LINE_IN_R
DO CK_LINE_IN_L
DO CK_LINE_IN_L
29
29
07/24 update
R5 08
R5 10
2
Q32A
2N7002DWH 2N SOT363-6
LINE_OUT_SENSE
R5 11 2
+V DDA_CODEC
100K_0201_1%
29
LINE_OUT_SENSE#
LINE_IN_SENS E#
3
R5 15
1
SENSE_A
2 1000P_0402_50V7K_X7R
13
VOL_DN/DMIC_1/GPIO 2
GPIO 3
30
VREFOUT-E / GPIO 4
31
SENSE_A
R5 12 2
1 2.49K_0402_1%
GPIO 5
43
R5 13 2
1 2.49K_0402_1%
GPIO 6
44
SPDIF OUT1 / GPIO 7
45
SPDIF OUT0
48
1 39.2K_0402_1%
SENSE_B
34
SENSE_B
26
AVSS1
DVSS
42
AVSS2
GPAD
49
2 1000P_0402_50V7K_X7R
Q32B
2N7002DWH 2N SOT363-6
1
0_0201_5%
MUTE_LE D_CNTL
EAP D#
MUTE_LED_CNTL
Port
Port
Port
Port
Port
Port
30
A
B
C
D
E
F
=
=
=
=
=
=
Dock Line Out

External Mic
Internal Mic
Internal Speakers
Line In
Internal Headphone
A
Compal Secret Data
92HD75B3X5NLGXYBX8_QFN48_7X7
LINE_IN_SENSE
C5 00 1
C5 01 1
100K_0201_1%
29
R5 14 2
1 39.2K_0402_1%
VOL_UP/DMIC_0/GPIO 1
Issued Date
2008/09/15
Deciphered Date
2010/12/31
5
Title

HDA CODEC 92HD75
Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

1
Sheet
26
of
47
R5 27
100K_0402_5%
1
2
+V D DA_CODEC
C ONN@
JP19
1 1
2 2
3 3
4 4
G1 5
G2 6
2
+MIC_BIAS_B
5
3
IN+
O
IN-
MIC_SENSE
26
INT_MIC_1_2
INT_MIC_2_2
D
ACES_85204-04001
2
1
BAV70W 3P C/C SOT-323
INT_MIC_1_2
LMV331IDCKRG4_SC70-5~D
R 526
120K_0402_5%
INT_MIC_2_2
D50
D24
U 75
04/24 Correct the Symbol from SINGA_2SJ-B960-003

to SINGA_2SJ3005-002211, also correct the
connection for fix Audio work abnormal issue.
10K_0402_5%
2.2K_0402_5%
R 528
1
C5 14
1U_0603_16V6K
R6 15
R 529
560K_0402_5%
PJSOT05C_SOT23
D38 @
@ PJDLC05_SOT23
2
1
1
3
JP35
220P_0402_25V8J
1 C6 38
EXT_MIC
L25
2 BLM18BD601SN1D_0603
MIC_EXTOUT
7
5
R 516
2 60.4_0402_1%
HP_OUT_L
L23
2 BLM18BD601SN1D_0603
HP_L_OUT
R 517
2 60.4_0402_1%
H P_OUT_R
L24
2 BLM18BD601SN1D_0603
H P_R_OUT
3
1
2
HP_OUTL
HP _OUTR
26
26
R 519
2
R 518
20K_0402_5%
C5 02
0.01U_0402_16V7K
20K_0402_5%
2 0.01U_0402_16V7K
C 503
SINGA_2SJ3005-002211
C ONN@
HP_DET
26
04/27 Change C642 from 33P to 15P via

IDT recommend to fix the SVTP fail issue.
EXT_MIC_3
C6 42 2
1 15P_0402_50V8J
EXT_MIC_2 1
2
10K_0402_5%
U 44B
TLV2462_SO8
8
3
M IC1
M IC1
R5 24
47K_0402_5%
26
U 44A
TLV2462_SO8
+COD EC_REF
C6 41
68P_0402_50V8J
2
1
C5 07
4.7U_0805_10V4Z
+MIC_BIAS_C
INT_MIC_2_5
C 517 1
R5 33
+CO DEC_REF
O
-
1
R5 34
2 INT_MIC_2_1
@ 3K_0402_5%
1
U 26A
TLV2462_SO8
L29
R5 36
1 10NH_HLC0603CSCCR11JT_5%
10K_0402_5%
2INT_MIC_2_31
2 INT_MIC_2_41
2
1
C 522
0.068U_0603_16V7K
C5 24
1U_0603_10V4Z
8
+
C 525
68P_0402_50V8J
2
26
26
Compal Secret Data
INT_MIC1
Issued Date
2008/09/15
Deciphered Date
2010/12/31
4
U 26B
TLV2462_SO8
A
2
5
R5 35
3K_0402_5%
1
2
@
8
+
+V DDA_CODEC
INT_MIC_2_2
C5 18
2 100P_0402_50V8J
+COD EC_REF
2
100K_0402_5%
0.1U_0402_16V4Z
C5 26
1U_0603_10V4Z
L30
R5 39
10K_0402_5%
2INT_MIC_1_31
2 INT_MIC_1_4
1
2
0.068U_0603_16V7K
1
C 527
68P_0402_50V8J
C5 19
+V D DA_CODEC
100P_0402_50V8J
1
C 523
C 521
2
R5 38
3K_0402_5%
1
2
@
2
100K_0402_5%
0.1U_0402_16V4Z
C 520
100P_0402_50V8J
INT_MIC_2_2
+V DDA_CODEC
2 INT_MIC_1_1
3K_0402_5%
R5 30
+V DDA_CODEC
R5 32
3K_0402_5%
INT_MIC_1_2
1
R5 37
C5 16 1
2 100P_0402_50V8J
INT_MIC_1_5
R 531
3K_0402_5%
R5 25
47K_0402_5%
2 EXT_MIC_1
C 639
+V DDA_CODEC
R6 17
EXT_MIC
1
0.47U_0402_6.3V6K
+V DDA_CODEC
C 640
2
L27
100P_0402_50V8J
2
100K_0402_5%
R7 04
+COD EC_REF
Title
INT_MIC2

AMP & Audio Jack
Size
D ocument Number
Rev
0.9
LA -5251P
Dat e:

1
Sheet
27
of
47
+5VS
2N7002DW T/R7_SOT-363-6
Q34B
+3VL
04/27 Del Q54, change the LED

circuit for common.
+3VS
HDD_STP#
22
@ R560
100K_0201_5%
W L_LED#
W W _LED#1
R1098
2
0_0402_5%
W L_LED# 1
R1097
2
0_0402_5%
R540
47K_0402_5%
W W _LED#
30 AMBER_BATLED#
AQUAW HITE_BATLED#
12,29 SATA_LED#
12,30
W L/BT_LED#
29
HDD_STP#
STB_LED#
W L/BT_LED#
09/01 Update
24
BT_LED
2N7002DW T/R7_SOT-363-6
R541 1
2 100K_0201_5%
07/02 update
12
2 HDA_ SDIN1_MDC
33_0402_5%
1
R543
HDA_RST#_MDC
13
15
17
GND
GND
GND
14
16
18
GND
GND
GND
R544
BITCLK_MDC 2
1
0_0201_5%
HDA_BIT_CLK_MDC
12
@ C531
1
2 10P_0402_25V8K
C530
2
4
6
8
10
12
C529
2
4
6
8
10
12
1
3
5
7
9
11
4.7U_0805_10V4Z
1
3
5
7
9
11
HDA_SDOUT_MDC
0.1U_0402_16V4Z
C528
JP23
HDA_SYNC_MDC
12 HDA_SDIN1
KSO11
KSO0
KSO2
KSO5
KSI_D_14
K SI_D_8
KSI_D_12
KSI_D_10
K SI_D_0
K SI_D_4
K SI_D_2
K SI_D_1
K SI_D_3
KSO3
KSO8
KSO4
KSO7
KSO6
KSO10
KSO1
K SI_D_5
K SI_D_6
K SI7
KSI_D_13
KSI_D_11
K SI_D_9
KSO9
C668
0.1U_0402_16V4Z
11/11 update for EMI.
C536
1000P_0402_50V7K
LEFT
RIGHT
+3VS
1000P_0402_50V7K
+3VS
HDA_SDOUT_MDC
STB_LED#
12
1
2
3
4
5
6
7
8
9
10
GND
GND
KS O[0..11]
KSI[0..7]
JP21
Place C536 close to JP22.8
12
KSI[0..7]
ACES_85201-1005N
CONN@
Q34A
BT_LED
KSO[0..11]
30
+3VL
1
2
3
4
5
6
7
8
9
10
11
12
1
4
23
HDD_HALTLED
12
30
JP22
2
5
0_0402_5%
1
R1099
W W AN_TRANSMIT_OFF#
15,23
2N7002DW H 2N SOT363-6
Q31B
+3VS
Place C668 close to JP22.2.
KSO11
KSO0
KSO2
KSO5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
GND1
GND2
C146
0.1U_0402_16V4Z
1
ACES_85204-02001
CONN@
1
2
TIP
RING
3
4
GND
GND
1
R547
ON/OFF#
2
47_0201_5%
FOX_JM74613-V5-7F
CONN@
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
K SI_D_0
K SI_D_4
K SI_D_2
K SI_D_1
C914
C915
C916
C917
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
K SI_D_3
KSO3
KSO8
KSO4
C918
C919
C920
C921
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C922
C923
C924
C925
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
C926
C927
C928
C929
1
1
1
1
2
2
2
2
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
K SI_D_5
K SI_D_6
K SI7
KSI_D_13
K SI0 1
KSI_D_11 C930 1
K SI_D_9 C931 1
KSO9
C932 1
K SI_D_0
2 100P_0402_50V8J
2 100P_0402_50V8J
2 100P_0402_50V8J
D25
K SI_D_8
Add C146 close to D34 pin 1.
3
R546
100K_0201_5%
K SI2 1
ON /OFFBTN_KBC#
ON/OFFBTN_KBC#
C538
1U_0603_10V4Z
K SI4 1
K SI_D_3
KSI_D_11
KSI_D_12
DAP202UGT106_SC-70
D30
2 K SI_D_5
K SI5 1
K SI_D_9
DAP202UGT106_SC-70
D31
2 K SI_D_2
K SI6 1
KSI_D_10
KSI_D_13
DAP202UGT106_SC-70
D32
2 K SI_D_6
DAP202UGT106_SC-70
30
DAP202UGT106_SC-70
D27
2 K SI_D_4
DAP202UGT106_SC-70
D28
2 K SI_D_1
3
29
C910
C911
C912
C913
D26
MOD_TIP
MOD _RING
KSI_D_14
K SI_D_8
KSI_D_12
KSI_D_10
ON /OFFBTN_KBC#
JP26
MOD _RING
MOD_TIP
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
100P_0402_50V8J
KSO7
KSO6
KSO10
KSO1
K SI1 1
1
2
3
4
2
2
2
2
K SI3 1
+3VL
1
2
G1
G2
1
1
1
1
HRS_FH28-60(30)SB-1SH(86)
CONN@
CONN@ ACES_88025-120N-CP
JP25
C906
C907
C908
C909
KSI_D_14
DAP202UGT106_SC-70
07/22 update
R550
1
2
100K_0402_5%
D34
+3VALW
ON/OFFBTN#
14,30
@ CH751H-40PT_SOD323-2
8/25 Update
11/14 Update
C742
@ 680P_0402_50V7K
STB_LED#
2 0_0201_5%
3
CAP_DAT
GND1
GND2
C AP_INT
L ID_SW #
D53
PJDLC05 3P_SOT23
+3VL
5.1K_0402_5%
R695 1
2
R694 1
2
5.1K_0402_5%
+5VS
C535
PJSOT05C_SOT23
+5VS
E&T_6701-E08N-00R
1
2
3
4
G1
G2
ACES_50504-0040N-001
CONN@
C532
0.1U_0402_16V4Z
PJDLC05_SOT23-3
D29
ON/OF F#
6/17 Correct JP27 connection from currently

Pin1:+5VS,Pin2:RIGHT,Pin7:GND,Pin8:GND to
Pin1:RIGHT,Pin2:NC,Pin7:NC,Pin8:+5VS.
2
D
C753
@ 330P_0402_50V7K
1
11/11 update for ESD.
C AP_CLK
CAP_DAT
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
1
2
3
4
5
6
TP_CLK
TP_DATA
Place C670 close to JP20.2's via.
C670
+3VL
JP29
30
30
1
2
3
4
5
6
7
8
PESD24VS2UT_SOT23-3~D
0.1U_0402_16V4Z
C627
220P_0402_25V
SP_CLK
SP_DATA
0.1U_0402_16V4Z
R438
10K_0201_5%
30
30
D48
ACES_87213-1200G
C752
@ 330P_0402_50V7K
1
1
2
3
4
5
6
7
8
LEFT
ACES_85205-04001
CONN@
D45
2
13
14
RIGHT
1
2
3
4
G5
G6
C AP_CLK
+3VS
C744
330P_0402_50V7K
1
2
3
4
5
6
ON/OF F#
STB_LED#
PJSOT05C_SOT23
R612 1
LID_SW #
PJSOT05C_SOT23
CONN@
JP27
JP20
20,30
CAP_CLK
CAP_DAT
CAP_INT
+5VS
+5VALW
D49
13,30
13,30
30
STB_LED#
D47
W L/BT_LED#
1
2
3
4
5
6
7
8
9
10
11
12
W L_LED#
CONN@
JP28
1
2
3
4
5
6
7
8
9
10
11
12
C AP_INT
+VREG3_51125
+3VS
Title

MDC/KBD/ON_OFF/LID
Size
Document Number
R ev
0.9
LA-5251P
Date:
T uesday, January 05, 2010

5
Sheet
28
of
47
VA
VIN
VA
R6 98
0.1U_0603_50V4Z
0.1U_0603_50V4Z
1
2
0_0805_5%
VA
15 USB20_N11
15 USB20_P11
28
15
15
ON/O FF#
VA_ON#
ON/ OFF#
DOC K_ID0
DOC K_ID1
26 LINE_IN_SENSE
26 LINE_OUT_SENSE
DLI NE_IN_L
DLINE _IN_R
26 DO CK_LINE_IN_L
26 DOCK _LINE_IN_R
DLINE_OUT_L
DL INE_OUT_R
26 DLINE_OUT_L
26 D LINE_OUT_R
DOCK_DETECT#
18 DOCK _RED
18 DOCK _GRN
18 DO CK_BLU
DOCK _RED 0_0402_5% 2

DOCK _GRN 0_0402_5% 2
DO CK_BLU 0_0402_5% 2
R5 55 1
R5 56 1
R5 57 1
R_DOC K_RED
R_DOC K_GRN
R_D OCK_BLU
+3VALW
SATA_LED#_Q
R49
10K_0402_5%
VA
41
42
43
44
RJ45_LINKLED#
RJ45_ACTLED#
PWRLED
DETECT1#
DOCK_ADP_SIGNAL
PREP#
5VS(0.5A)
5VS(0.5A)
GND
GND
USB1DP_ML0+
USB1+
DP_ML0GND
GND
NBSWON#
DP_ML1+
VA_ON#
DP_ML1DOCK_ID0
GND
DOCK_ID1
DP_ML2+
AUDIO AGND
DP_ML2LINE_IN_SENSE
GND
LINE_OUT_SENSE
DP_ML3+
AUDIO AGND
DP_ML3LINE_IN_L
GND
LINE_IN_R
DP_AUX+
AUDIO AGND
DP_AUXLINE_OUT_L
GND
LINE_OUT_R
DCAD
AUDIO AGND
HCED
DETECT2#
HPD
GND
GND
CRT_R
CRT_DDC_DATA
CRT_G
CRT_DDC_CLK
CRT_B
GND
GND
CRT_VSYNC
RESERVED(USB3_RX+)
CRT_HSYNC
RESERVED(USB3_RX-)
GND
GND
RESERVED(SATA_RXP)
RESERVED(USB3_TX+) RESERVED(SATA_RXN)
RESERVED(USB3_TX-)
GND
GND
RESERVED(SATA_TXP)
RESERVED(SATA_LED#) RESERVED(SATA_TXN)
GND
GND
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
SATA_LED#
MDO3+ 21
MDO3- 21
MDO2+ 21
MDO2- 21
04/22 Change JP30 Pin 46 and 27 connection from GND to DOCK_DETECT#

LAN_ACT#
DOCK_DETECT#
PRE P#
21
PREP# 15,18,21
SLP_S4# 14,24,33,39
04/20 JP30.8 become NC, JP30.48 connect to SLP_S4# from HP
DPB_TXP0
DPB_TXN0
14
14
DPB_TXP1
DPB_TXN1
14
14
DPB_TXP2
DPB_TXN2
14
14
DPB_TXP3
DPB_TXN3
14
14
DPB_AUX 14
DPB_AUX# 14
DPB_CTRLCLK 14
DPB_CTRLDATA 14
DP B_HPD 14
D_D DCDATA
D_DDCC LK
4/5 update for HP Docking pin define change
D_DD CDATA 18
D_DDCCLK 18
D_V S Y NC 18
D _ HS Y NC 18
SATA_PRX_DTX_P5
SATA_PRX_DTX_N5
12
12
SATA_PTX_DRX_P5
SATA_PTX_DRX_N5
12
12
C
FOX_QL1044L-D261A1-7H
C ONN@
VA_ON#
1
Q79
2N7002H_SOT23-3
2
G
11/05 update
1 2,28
MDO3+
MDO3MDO2+
MDO2-
1
SLP_S3#
82
83
84
85
86
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
RJ45_D+
RJ45_DRJ45_C+
RJ45_C-
RJ45_B+
RJ45_BRJ45_A+
RJ45_A-
R 552
1K_0201_5%
DOCK _RED
DOCK _GRN
DO CK_BLU
SA TA_LED#
DOCK _RED
DOCK _GRN
DO CK_BLU
C5 47 1
C5 48 1
C5 49 1
R5 64 1
R5 68 1
R5 70 1
C 540
0.1U_0402_16V4Z
ADP_SIGNAL
SLP_S3#
1
2
3
4
GND
GND
GND
GND
GND
21 LANLINK_STATUS#
28 STB_LED#
ADP_SIGNAL
14,23,30,32,33,35,37,38 SLP_S3#
08/28 update
D35
@ PJDLC05_SOT23-3
JP30
MDO1+
MDO1MDO0+
MDO0-
21 MDO1+
21 MDO121 MDO0+
21 MDO0-
81
1
3
C5 42
C5 41
2 @ 0.1U_0402_16V4Z
2 @ 0.1U_0402_16V4Z
2 @ 0.1U_0402_16V4Z
2 @ 150_0402_1%
2 @ 150_0402_1%
2 @ 150_0402_1%
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2010/12/31
Title

DOCK CONN

Cus tom LA -5251P
Dat e:
7
Rev
0.9
Sheet
29
8
of
47
+3VL
R5 90
+3VL
1
R P7
8
7
6
5
KSI3
KSI2
KSI1
KSI0
R 521
@ 100K_0402_5%
ROM_CS #0
1
C 554
C 553
0.1U_0402_16V4Z
1
2
3
4
0.1U_0402_16V4Z
1
C 555
2
1
C5 56
C5 57
2
1
R5 73
0.1U_0402_16V4Z
0_0603_5%
07/01 update
+3VL
C 565
0.1U_0402_16V4Z
2
0_0402_5%
+3VS
C 558
0.1U_0402_16V4Z
A
12
10K_0804_8P4R_5%
28
ROM_DATOUT
2
0_0402_5%
ROM_CS #0
2
0_0402_5%
1
R5 78
ROM_DATIN
2
0_0402_5%
KSO[0..11]
ROM_CLK
1 C6 54
@ 4.7P_0402_50V8C
2
+5VS
R P9
8
7
6
5
K SI[0..7]
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
10K_0804_8P4R_5%
R P10
8
7
6
5
SP_CLK
SP _DATA
TP _CLK
TP_DATA
SP_CLK
SP _DATA
28 TP_CLK
28 TP_DATA
28 SP_CLK
28 SP_DATA
10K_0804_8P4R_5%
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12/GPIO00/KBRST
KSO13/GPIO18
29
28
27
26
25
24
23
22
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
35
36
61
62
66
67
IMCLK
IMDAT
KCLK
KDAT
EMCLK
EMDAT
LAD[3]
LAD[2]
LAD[1]
LAD[0]
LPC_LFRAME#
15 N PCI_RST#
52
53
LFRAME#
LRESET#
CRY1
CRY2
4
OUT
NC
49
GPIO07/PWM3
GPIO08/RXD
GPIO09/TXD
85
86
87
P M_RSMRST#
CRACK_BGA
B D_ ID
GPIO11/AB2A_DATA
GPIO12/AB2A_CLK
GPIO13/AB2B_DATA
GPIO14/AB2B_CLK
GPIO15/FAN_TACH1
GPIO16/FAN_TACH2
GPIO17/A20M
88
89
90
91
92
101
102
AB 2A_DATA R5 82
AB2A _CLK R5 83
R5 84
R5 85
GPIO20/PS2CLK
GPIO21/PS2DAT
GPIO24/KSO16
ADP_PRES[CKT#2]/GPIO27/WK_SE05
103
105
4
74
PWRBTN_OUT#
1
R6 08
AB1A_DATA
AB1A_CLK
111
112
AB 1A_DATA
AB1A _CLK
AB1B_DATA
AB1B_CLK
109
110
AB 1B_DATA
AB1B _CLK
BAT_ALARM
12 KBC_SPI_CLK_R
31 SPI_CLK
22 MC2_DISABLE
12 KBC_SPI_CS1#_R
31 SPI_CS1#
23 MC1_DISABLE
14,33,39 PM_SLP_LAN#
35 PMC
41 O CP_A_IN
O CP_A_IN
1
R6 03
2ROM_CLK
0_0402_5%
1
R6 04
R 1101
1
1
R 1102
2
0_0402_5%
300_0402_5%
2 A DC1
2 ADC
300_0402_5%
LPC
Bus
70
71
XTAL1
XTAL2
68
VCC0
1
2
3
30
31
32
33
34
43
44
Alarm [CKT#2]/GPIO36
HSTCLK/GPIO41
FLCLK
GPIO39
HSTCS1#/GPIO42
FLCS1#
GPIO38
GPIO37
ADC1/GPIO46
ADC_TO_PWM_IN
KBC1098-NU_VTQFP128_14X14
TEST PIN
108
59
75
60
78
77
38
32K_CLK
P GD _IN
P W R_ GD
69
TEST
R6 09
28
PM_RSMRST# 14
CRACK_BGA 8,17
1
1
1
1
2
2
2
2
0_0201_5%
0_0201_5%
0_0201_5%
0_0402_5%
CAP_DAT 13,28
CAP_CLK 13,28
CELLS 35
A_SD# 26
ADP_DET# 41
THM_MAIN# 34
GATEA20 15
2 0_0402_5%
O N/OFFBTN#
2 LA NLINK_R#
@ 0_0402_5%
L ANLINK_R# 15,21
ADP_PRES 33,35
14,28
AB1A_DATA 34
AB1A_CLK 34
AB1B_DATA
AB1B_CLK
R5 88 1
2 0_0201_5%
CAP_INT
28
R5 92 1
2 0_0201_5%
ADP_EN
41
07/03 update
R5 95 1
2 0_0201_5%
R5 96 1
2 1K_0201_5%
07/22 update
116
113
115
114
AC[CKT#2]/GPIO23
ADC2/GPIO40
Q/GPIO33
GPIO34
GPIO35
AVCC
41
42
65
64
63
40
36,41
AMBER_BATLED#
8051TX 22,31
8051RX 22,31
A DC2
R 1100 1
2 100K_0201_5% +3VL
AC_ADP_PRES
2 300_0402_5%
ADP_A_ID 41
LI D_SW#
+3VL
LI D_SW#
R5 51 1
2 100K_0402_5%
R5 53 1
2@ 100K_0402_5%
CPU Type Detect : High-->SV , Low-->LV (No use)
28
+3VL
07/02 update
35
CAP_CLK
11/06 update
LI D_SW#
+3VL
CPU_SV_ID_DET
P W R _GD 32
V CC1 _PWRGD
O CP 41
CFETB/GPIO10
BAT_LED#
PWR_LED#/8051TX
FDD_LED#/8051RX
20,28
11/14 update
1 R3 63
2
100K_0402_5%
07/02 update
2200P_0402_25V7K 2
1 C9 70
ADC
2200P_0402_25V7K 2
1 C9 71
A DC1
2200P_0402_25V7K 2
1 C9 72
A DC2
SPI_CLK
KB RST#
R 589 1
2@ 10K_0201_5%
V CC1_ PWRGD R 591 1
2 10K_0201_5%
CRACK_BGA
R 593 1
2 10K_0201_5%
R 586 1
2 10K_0201_5%
K B C_PWR_ON R 597 1
2 10K_0201_5%
B D_ ID
07/01 update
+3VL
R P11
0_0402_5%
2
14,40
P GD _IN
P GD _IN
@ R6 06 1
P M_RSMRST# R6 07 1
2
D
35
SLP_S3# 14,23,29,32,33,35,37,38
8051_RECOVER# 22,31
R6 01 1
+R TCVCC
R6 10
0_0402_5%
GPIO26/KSO17
NC_CLOCKI
32KHZ_OUT/GPIO22/WK_SE01
RESET_OUT#/GPIO06
PWRGD
VCC1_RST#
ADC_TO_PWM_OUT/GPIO19
12,28
KB_RST# 15
FAN_PWM 4
BAT_PWM_OUT
CHG CTRL 35
ON/OFFBTN_KBC#
R7 06 1
73
GPIO25
32.768KHZ QTFM28-32768K125P20L
IN
CPU_SV_ID_DET
SLP_S3#
C 634
NC
GPIO01
GPIO02
GPIO03
GPIO04/KSO14
GPIO05/KSO15
107
79
80
81
83
KB RST#
D36 1
K B C_PWR_ON 36
AQUAWHITE_BATLED#
4.7P_0402_50V8C
123
122
121
120
118
2 0_0402_5%
C 622
C5 62
22P_0402_50V8J
C5 61
22P_0402_50V8J
CFETA/OUT7/nSMI
OUT8/KBRST
OUT9/PWM2
OUT10/PWM0
PWM_CHRGCTL
R5 79 1
01/04 update (Cancel Board ID Detect reserve

circuit (Del U8,Q37,R571,R572,R574,R575)).
PM_SLP_M# 14,32,33
SUS_PWR_ACK 14
AC_PRESENT 14
MUTE_LED_CNTL 26
P C I_SERR# 15,22,25,31
4.7P_0402_50V8C
+ VCC0
124
125
Miscellaneous
12,22,31
Y5
OUT0/(SCI)
OUT1/IRQ8#
AVSS
51
50
48
46
2 4.7U_0805_10V6K
93
98
99
100
126
Power Mgmt/SIRQ
AGND
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
12,22,31
12,22,31
12,22,31
12,22,31
CLK_PCI_KBC
RUNS CI _EC#
72
4.7P_0402_50V8C
10_0402_5%
C5 60
R5 87
CLKRUN#
SER_IRQ
PCI_CLK
EC_SCI#
14,25,31 P M_CLKRUN#
12,22,25,31 S I RQ
15 C LK_PCI_KBC
15 RUNS CI _EC#
55
57
54
76
C5 59 1
GPIO28
GPIO29
GPIO30
GPIO31
GPIO32
Access Bus Interface
CLK_PCI_KBC
07/01 update
15
CAP
45
1
2
3
4
21
20
19
18
17
16
13
12
10
9
8
7
6
5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1
2
3
4
28
TP _CLK
TP_DATA
FLDATAOUT
HSTDATAOUT/GPIO45
FLCS0#
HSTCS0#/GPIO44
FLDATAIN
HSTDATAIN/GPIO43
Keyboard/Mouse Interface
KS O0
KS O1
KS O2
KS O3
KS O4
KS O5
KS O6
KS O7
KS O8
KS O9
KS O10
KS O11
128
127
97
96
95
94
VCC2
1
R5 76
1
R5 77
119
U 32
31 SPI_SI
KBC_SPI_SI_R
31 SPI_CS0#
KBC_SPI_CS0#_R
31 SPI_SO
12 KBC_SPI_SO
12
VCC1
VCC1
VCC1
VCC1
VCC1
KSI7
KSI6
KSI5
KSI4
SMSC_1098-NU_TQFP-128P
8
7
6
5
11
37
47
56
104
82
117
1
2
3
4
VCC1
R P8
4.7U_0805_10V4Z
General Purpose I/O Interface
0.1U_0402_16V4Z
39
58
84
106
14
10K_0804_8P4R_5%
2 10K_0201_5%
4.7K_0804_8P4R_5%
AB1A _CLK
1
8
AB 1A_DATA
2
7
AB1B _CLK
3
6
AB 1B_DATA
4
5
2 100K_0201_5%
07/02 update
+V CC0
R6 11
C5 63
@ 0_0402_5%
C5 64
0.1U_0402_16V4Z
Compal Secret Data
1U_0603_10V4Z
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

KBC1098
Size
D ocument Number
Rev
0.9
L A-5251P
Dat e:

5
Sheet
30
of
47
TPM1.2 on board
Finger Printer
1
2
1
CH1
VN
CH2
VP
USB20_P10
2
@
14,25,30
+5VALW
CM1213-02SR_SOT143-4
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
LPC_LFRAME#
P LT_RST#
L PC_PD#
S I RQ
CLK_P CI_TPM
26
23
20
17
22
16
28
27
21
LAD0
LAD1
LAD2
LAD3
LFRAME#
LRESET#
LPCPD#
SERIRQ
LCLK
2
10_0201_5%
15
CLKRUN#
@
1
R 621
C5 80
PM_CLKRUN#
SLB 9635 TT 1.2

TEST1
TESTB1/BADD
NC
NC
NC
TPM_XTALO
14
XTALO
TPM_XTALI
13
XTALI/32K IN
ACES_87216-2404_24P
C ONN@
TPM_GPIO
TPM_GPIO2
6
2
R6 19
4.7K_0201_5%
R6 22
0_0201_5%
1
2
8
9
+3VS
T109 P AD
T110 P AD
Base I/O Address

0 = 02Eh
1 =* 04Eh
1
2
R 623
@
4.7K_0201_5%
PP
+3VS
07/02 update
3
12
1
SLB 9635 TT 1.2_TSSOP28

B
25
18
11
4
R 624
@ 4.7K_0201_5%
B
GPIO
GPIO2
2 4.7K_0402_5%
12,22,25,30 S I RQ
15 CLK_PCI_TPM
1
10P_0402_50V8K
R3 67 1
08/25 update
U34
12,22,30 LPC_LAD0
12,22,30 LPC_LAD1
12,22,30 LPC_LAD2
12,22,30 LPC_LAD3
12,22,30 LPC_LFRAME#
+3VS
TPM_XTALO
2
22P_0402_50V8J
ACES_85201-0405N
1
C 577
R 618
10M_0402_5%
VSB
24
19
10
OUT
32.768KHZ QTFM28-32768K125P20L
D39
USB20_N10
IN
NC
GND
GND
GND
GND
1
R6 25
220K_0402_1%
1
2
FP R _OFF
NC
USB20_N10
USB20_P10
15
15
0.1U_0402_16V4Z
CONN@
JP32
1 1
2 2
3 3
4 4
5 G1
6 G2
C5 76
15
10U_0805_10V4Z
SPI_CS1#
R6 20
10K_0201_5%
0.1U_0402_16V4Z
SPI_CLK _JP
SPI_CS0#_JP
SPI_SI_JP
SPI_S O_JP
SPI_HOLD#_0
C5 79
30
8051_RECOV ER#
U SB20_N1_PWR
1
C5 78
8051TX
8051RX
8051_RECOVER#
DEBUG_KBCRST
D
S I RQ
22,30
22,30
22,30
22,36
LPC_LFRAME#
S I RQ
PLT_RST#
P C I_SERR#
LPC_LAD0
LPC_LAD1
LPC_LAD2
LPC_LAD3
Ground
LPC_PCI_CLK
Ground
LPC_FRAME#
+V3S
LPC_RESET#
+V3S
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
VCC_3VA
PWR_LED#
CAPS_LED#
NUM_LED#
VCC1_PWRGD
SPI_CLK
SPI_CS#
SPI_SI
SPI_SO
SPI_HOLD#
Reserved
Reserved
Reserved
12,22,30
12,22,25,30
4,12,15,21,22,23
15,22,25,30
12,22,30
12,22,30
12,22,30
12,22,30
C LK_PCI_DB
C LK_PCI_DB
Q38
0.1U_0402_16V4Z
+3VALW
JP31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
C5 75
B+_DEBUG
2
0.1U_0402_16V4Z
Y6
15,22
TPM_XTALI
2
22P_0402_50V8J
reserve it for WWAN noise
C5 74
@ C 655
12P_0402_50V8J
1
C 572
2 100K_0201_5%
0.1U_0402_16V4Z
R 628 1
C5 73
8051_RECOV ER#
VDD
VDD
VDD
+3VL
C LK_PCI_DB
LPC Debug Port
+3VS +3VALW
07/02 update
2
R 626
@ 0_0201_5%
SD/MMC socket
+3VL
SPI ROM SOCKET
2
SPI_W P#
+SD_MMC_3VCC
HOLD
30
SPI_CS0#
SPI_CS 0#
30
SPI_CLK
SPI_CLK
30
SPI_SI
SPI_SI
25
25
25
25
25
25
25
25
SPI_SO_R0
1
2
R6 30 33_0402_5%
SPI_SO
@
1
2
C6 30
22P_0402_50V8J
30
C ONN@ ACES-91960-0084L
1
1
1
1
2
0_0201_5%
2
0_0201_5%
2
0_0201_5%
2
0_0201_5%
2
0_0201_5%
25
SPI_HOLD#_1
SPI_CLK
+3VL
20mils R6 31 1
3.3K_0201_5%
SPI_SI
14
15
6
3
16
17
S D _WP 25
S D_CARD_DET#
S D_CARD_DET#
CMD
TAI_PSDBT0-16GNBS7N14N0_15P
C ONN@
R6 27
25
+SD_MMC_3VCC
+3VS
25
C5 82
SDPWR0_MSPWR_XDPWR
SDPWR0_MSPWR_XDPWR
1
5
RT9701-GB SOT23 5P
R5 66
150K_0402_5%
GND
C6 32
VIN
VOUT
VIN/CE VOUT
1U_0402_6.3V4Z
@ SST25VF064B-66_SO8
C6 31
@ 4.7P_0402_50V8C
3
4
10U_0805_10V4Z
C6 33
40mil
U 46
0.1U_0402_16V4Z
SPI ROM
WP
CD
VSS2
VSS1
VSS3
VSS4
@10_0201_5%
SPI_SO_R0
SOIC 8P
CLK
SDCLK_MMCCLK
& U1
45@ W25Q64BVSSIG
SD_MMC_CMD
SPI_CLK
1 R 632
2
@ 0_0201_5%
SPI_CS 0#
8MB SPI ROM

& U2
SPI_W P#
SD_MMC_CMD
VDD
25
SDCLK_MM CCLK
D0
D1
D2
D3
D4
D5
D6
D7
SPI_HOLD#_0
R6 33
SPI_CLK _JP
R6 34
SPI_SI_JP
R6 35
SPI_CS0#_JP
R6 36
SPI_S O_JP
R6 37
1 R5 65
2
@
10_0201_5%
7
8
9
1
10
11
12
13
C4 14
05/06 update R630 from @33_0402 become install.
SDDA TA0_MSDATA0
SDDA TA1_MSDATA1
SDDA TA2_MSDATA2
SDDA TA3_MSDATA3
MMC_D4
MMC_D5
MMC_D6
MMC_D7
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
MMC_D4
MMC_D5
MMC_D6
MMC_D7
Near to JP33
JP33
0.1U_0402_16V4Z
C4 12
VSS
R5 63
150K_0402_5%
2 3.3K_0201_5%SPI_HOLD#_1
VCC
100P_0402_50V8J
R 629 1
4.7U_0603_6.3V6K
C4 13
20mils
+3VL
Layout note: U46 close to JP33 within 2"
U35
25mA
C 581
0.1U_0402_16V4Z
8MB SPI ROM
20mils
BIOS ROM(8MB)
01/04 update (Cancel 16pin BIOS reserve (Del U36 and R696)).
D
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title
TCG/BIOS ROM/PS2/SW LPC DEBUG

Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

5
Sheet
31
of
47
R6 38
1
2
1M_0201_1%
3300P_0402_25V7K
37
5
6
+
-
IN1
IN2
MC74VHC1G08DFT2G_SC70-5
OUT
VCC
R6 52
2.49K_0402_1%
LM393DG_SO8
10/19 Delete H13 (H_3P0);

change H2 from H_4P7 to
H_4P4; H28 from H_4P9 to
H_4P8.
R6 57
1
2
1M_0201_1%
+5VALW
3.3K_0201_1%
1
2
R6 55
11.5K_0402_1%
1
2
R6 56
2VREF_51125 1
H25
HOLEA
H 31
H12
HOLEA
H20
HOLEA
7/15 update for HOLEA

M/E, del H31
8/18 update for
M/E, add back H31
H9
HOLEA
H21
HOLEA
R6 61
41.2K_0402_1%
2
H11
HOLEA
11/13 Change H2 from

H_4P4 to H_4P7; H28 from
H_4P8 to H_4P9.
1/4 Cancel H17 for

M/Emodify.
H24
HOLEA
H3
HOLEA
H10
HOLEA
LM393DG_SO8
2 3300P_0402_25V7K
4/23 Cancel H16 for

M/E PCB edge
modify.
H7
HOLEA
C 586
4/9 update for M/E, Change

H3 H_3P3-->H_3P0, H10
H_2P5-->H_2P3
H1
HOLEA
R6 59
78.7K_0402_1%~D
H28
HOLEA
H2
HOLEA
U 39A
8
3
2VREF_393
+1.5VS
10K_0201_5%
R 660
1
2
1.8VS_POK
2VREF_51125
30
VTTPWRGOOD
2
38
V CCP_1.5VSPWRGD
R6 48
4.99K_0402_1%
56.2K_0402_1%
P W R_ GD
U 37B
O
2VREF_393
MC74VHC1G08DFT2G_SC70-5
8
2
10K_0201_5%
2VREF_393
C5 85
IN2
U77
OUT
R6 58
R6 51
2
16.2K_0402_1%
VCCP_POK
+5VALW
2
49.9K_0402_1%
1
R6 54
1
U38
1
2
1M_0201_1%
1
R6 53
C5 83
1000P_0402_50V7K
2
3.3K_0201_5%
+3VS
+1.05VS
IN1
+3VALW
C5 84
3300P_0402_25V7K
1
R6 50
LM393DG_SO8
R4
8.2K_0402_5%
@ 0_0402_5%
37
SHORT PADS
R6 49
GFXVR_PWRGD
V C CP_EN
42
GND
R6
10K_0201_5%
J1
1
U 37A
1
R 647
2
49.9K_0402_1%
SLP_S3#
1
R6 45
+3VALW
SLP_S3#
1
R 646
2
10K_0201_5%
2 2VREF_393
34.8K_0402_1%
VCC
14,23,29,30,33,35,37,38
M_PWROK
2
11.5K_0402_1%
D40
2
1
2
3.3K_0201_5%
D41
2
1
2
3.3K_0201_5%
1
R6 43
R 642
2VREF_51125
1
R6 44
+0.75VS
14
2
76.8K_0402_1%
1
R6 41
+5VS

14,23,29,30,33,35,37,38
R 639
2
3.3K_0201_5%
1
R6 40
1.5V_POK
+3VS
+5VALW
39
GND
U 39B
O
M_PWROK
LM393DG_SO8
H5
HOLEA
08/28 update
H30
HOLEA
D43
1N4148WS-7-F_SOD323-2
R6 72
86.6K_0402_1%
R6 71 1
H14
HOLEA
2 1M_0201_1%
H8
HOLEA
C 589
2
0.047U_0402_16V7K
C5 88
1
3.3K_0201_5%
H4
HOLEA
14
R6 69
1K_0201_5%
D42
R6 70 1
M_PWROK
2 14.7K_0402_1%
1 10K_0201_5%
R 666 2
PM_SLP_M#
2 46.4K_0402_1%
R6 68 1
+1.05VM
14,30,33
2 3.3K_0201_5%
R6 67 1
H22
HOLEA
8
+3VM
R6 65 1
H23
HOLEA
1.05VM_LAN_POK
39
R6 64
3.3K_0201_5%
+5VALW
H29
HOLEA
1 1M_0201_1%
R6 63 2
H26
HOLEA
4/8 update for

M/E, del H6
+3VALW
C5 87
1000P_0402_25V8J
R 662
71.5K_0402_1%
3300P_0402_50V7K
Z ZZ1
FM1
1
FM2
1
FM3
1
FM4
D
PCB-MB
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2010/12/31
Title

POK CKT
Size
D ocument Number
Rev
0.9
L A-5251P
Dat e:
7
32
Sheet
8
of
47
Q39
330U_B2_2VM_R15M
R6 75
470_0201_5%
2
A
Q40A
L AN_EN
Q40B
PM_SLP_M
L AN_EN
2N7002DWH 2N SOT363-6
Q50A
2N7002DWH 2N SOT363-6
2N7002DWH 2N SOT363-6
PM_SLP_LAN#
14,30,39
1
R6 74
470_0201_5%
C5 91
10U_0805_10V4Z
1
2
2
R6 77
1
2
4.7K_0402_5%
0.1U_0402_16V4Z
C5 90
R 673
47K_0402_5%
+3VM
+1.05VM
C39
0.1U_0402_16V4Z
3
C 592
R U N ON
10U_0805_10V4Z
C5 96
R 676
1
2
0_0402_5%
0.1U_0402_16V4Z
C5 95
0.1U_0402_16V4Z
C5 94
10U_0805_10V4Z
C5 93
05/06 update to install C39

(330U_2V_B2_R15M) by HP
request.
SI7326DN-T1-E3_PAK1212-8
U40
1
2
5
3
A
+3VM
+1.05VS
+3VALW
+1.05VM_LAN
4
2
1
2
3
R U N ON
+1.5V
Add C626,C664 close to JDIMA1;

C656,C657 close to JDIMB1.
PM_SLP_M
2N7002DWH 2N SOT363-6
+3VL
1
1
Q50B
14,30,32
PM_SLP_M# 5
PM_SLP_M#
2N7002DWH 2N SOT363-6
Q43A
Q43B
2N7002DWH 2N SOT363-6
14,23,29,30,32,35,37,38
SLP_S3#
2 0.1U_0402_16V4Z
C 656 1
2 0.1U_0402_16V4Z
C 657 1
2 0.1U_0402_16V4Z
3
C6 10
10U_0805_10V4Z
2N7002DWH 2N SOT363-6
14,24,29,39
SLP_S4#
C 664 1
+5VS
2 0.1U_0402_16V4Z
Add C666,C667,C671 close to JP11.
SLP_S4
SLP_S4
+1.5VS_CPU_VDDQ
C 626 1
R6 84
100K_0201_5%
SLP_S3
C 609
C6 11
10U_0805_10V4Z
PM_SLP_M
0.1U_0402_16V4Z
R 685
100K_0201_5%
R6 86
100K_0201_5%
+5VS
1
2
1
62
1
07/17 update
+3VL
SI7326DN-T1-E3_PAK1212-8
U43
1
2
5
3
@ 0.01U_0402_16V7K
+3VL
+5VALW
10U_0805_10V4K
ADP_PRES
R U N ON
Q44B
30,35
2N7002DWH 2N SOT363-6
C6 07
R6 81
1
2
0_0402_5%
1
2
3
0.1U_0402_10V6K
Q42
AO4430L 1N SOIC-8
8
7
6
5
C6 06
R6 83
1
2
820K_0402_5%
+1.5VS
0.1U_0402_10V6K
0_0402_5%
2
C5 05
C6 05
R 1104
10U_0805_10V4K
C6 04
330U_B2_2VM_R15M
0.1U_0402_16V4Z
C6 25
ADP_PRES
C40
0.1U_0402_16V4Z
Q45B
3 0,35
C6 24
C6 08
0.01U_0402_16V7K
+1.5V
+1.5VS_CPU_VDDQ
SI7326DN-T1-E3_PAK1212-8
U45
1
2
5
3
Q44A
2N7002DWH 2N SOT363-6
R6 82 330K_0402_5%
1
2
10U_0805_10V4Z
C6 03
B+
0.1U_0402_16V4Z
R6 80
470_0402_5%
2N7002DWH 2N SOT363-6
+1.5V
05/06 update to install C40

(330U_2V_B2_R15M) by HP
request.
C6 02
R 679
820K_0402_5%
0.1U_0402_16V4Z
C6 01
Q45A
SLP_S3
10U_0805_10V4Z
C6 00
R U N ON
J2
SHORT PADS
C5 99
+1.05VM
SI7326DN-T1-E3_PAK1212-8
U42
1
2
5
3
10U_0805_10V4Z
C5 98
2 10U_0805_10V4Z
0.1U_0402_16V4Z
R6 78
330K_0402_5%
+3VALW
+3VS
SI7326DN-T1-E3_PAK1212-8
U41
1
2
5
3
1
1
C5 97
+1.05VM_LAN
B+
C 666 1
2 0.1U_0402_16V4Z
C 667 1
2 0.1U_0402_16V4Z
C 671 1
2 0.1U_0402_16V4Z
1/5 update for EMI PCI Issue.

R U N ON
07/01 update
R 688
470_0201_5%
R 691
470_0201_5%
+GFX_CORE
R6 92
470_0201_5%
+1.5VS_CPU_VDDQ
R6 99
470_0201_5%
07/17 update BOM.
+ VCCP
1
R6 87
470_0201_5%
+1.5V
+1.8VS
+3VS
+1.05VS
R 702
470_0201_5%
R 1103
SLP_S4
2N7002DWH 2N SOT363-6
3 2
6 2
Q41A
Q41B
SLP_S3
2
1
3 2
Q49A
2N7002DWH 2N SOT363-6
Q49B
SLP_S3
Q52B
SLP_S4
2N7002DWH 2N SOT363-6
SLP_S3
2N7002DWH 2N SOT363-6
2N7002DWH 2N SOT363-6
4
Q47A
2N7002DWH 2N SOT363-6
SLP_S3 2
2N7002DWH 2N SOT363-6
Q47B
SLP_S3
6 2
3 2
6 2
32
220_0402_5%

+1.5VS
SLP_S3 2
2
SLP_S3
Issued Date
Compal Secret Data
2
G
2N7002DWH 2N SOT363-6
Q48A
2N7002DWH 2N SOT363-6
Q48B
SLP_S3 5
05/06 Update R693 and Q53 become no

install to avoid the +0.75VS leakage from
DDR slot on S3 Mode for power saving.
07/09 Update
22_0402_5%
R 693
09/10 update.
6 2
R 690
470_0201_5%
3 2
R6 89
470_0201_5%
+0.75VS
+5VS
S Q53
2N7002_SOT23-3
2008/09/15
Deciphered Date
2010/12/31
3
Title

DC/DC Circuits
Size
D ocument Number
Rev
0 .9
L A-5251P
Dat e:

5
Sheet
33
of
47
ADP_SIGNAL
PJP1
ADPIN
PC3
100P_0402_50V8J
PC2
1000P_0402_50V7K
VMB
PJP2
1
2
3
4
5
6
7
PR23
100_0805_5%
1
2
PD2
BATT
PL2
HCB2012KF-121T50_0805
1
2
CH751H_SOD323-2
B+_DEBUG
B+_DEBUG
PC15
0.1U_0603_50V7K
1SS355_SOD323-2
PC6
0.01U_0402_50V4Z
PR6
100_0402_5%
2
1
PR5
100_0402_5%
2
1
PC7
100P_0402_50V8J
2
1
PD8
RLZ27V
2
PL4
HCB2012KF-121T50_0805
51125_PWR
PC9
100P_0402_50V8J
PR3
1K_0402_5%
2
1
+3VL
PC8
100P_0402_50V8J
2
1
PD7
PJSOT24CW _SOT323-3
PD6
PJSOT24CW _SOT323-3
PD22
1SS355_SOD323-2
PD12
BATT
PC5
1000P_0402_50V7K
@SUYIN_200275MR005G15UZL_5P
B
PR1
@15K_0402_5%
1
2
3
4
5
GND
GND
Vin
PR37
0_0402_5%
1
2
PD1
@PJSOT24C_SOT23
@FOX_JPD1131-DB371-7F
PL3
HCB2012KF-121T50_0805
V+
GND_4
GND_3
B++
2
A DPIN
PC4
1000P_0402_50V7K
2
1
GND_2
VIN
PL1
HCB2012KF-121T50_0805
1
2
29,41
V+
ADP_SIGNAL
GND_1
6
7
ID
V-
PC1
100P_0402_50V8J
V-
PR4
100K_0402_5%
30
AB1A_DATA
30
THM_MAIN#
PD5
BAV99W T1G_SC70-3 PD3
BAV99W T1G_SC70-3
AB1A_CLK
30
PD4
BAV99W T1G_SC70-3
+3VL
+3VL
PH1 under CPU botten side :

CPU thermal protection at 93 +-3 degree C
(Need to be checked)
C
2VREF_51125
EN0 36
VCC+
OUT
GND
PQ1
SSM3K7002FU_SC70-3
2
G
INLMV331IDCKRG4_SC70-5
PC13
1000P_0402_50V7K
PR17
150K_0402_1%
IN+
1
1
1
2
2VREF_51125 PR13
75K_0402_1%
PR10
100K_0402_5%
PU1
PR16
19.1K_0402_1%
PC12
0.1U_0603_25V7K
VL
VL
PR12
53.6K_0603_1%
1
2
Close to CPU
PR8
470K_0402_1%
1
2
PH1
100K_0603_1%_TSM1A104F4361RZ
0.9
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
1
Title

DC-IN/ BATTERY CONN

C ustom LA-4902P
D ate:
R ev

4
Sheet
34
of
47
B+
P4
PR120
22K_0402_5%
4
2
1
2
PC104
4.7U_0805_25V6-K
1
2
1
5
4.7U_0805_25V6-K
2
1
4.7U_0805_25V6-K
2
1
4.7U_0805_25V6-K
2
1
PC115
PC128
4.7U_0805_25V6-K
PC129
1 1
PC114
3
2
1
3
2
1
1
2
19
30
PR117
100K_0402_5%
1
41
CHGCTRL
PC120
0.1U_0603_50V7K
PR126
100K_0402_5%
S PQ107
SSM3K7002FU_SC70-3
2
B
-IN
V+
OUT
PMC 30
PR143
39.2K_0402_1%
PR144
49.9K_0402_1%
470K_0402_5%
Compal Secret Data

2008/09/15
Deciphered Date
2010/12/31
A
PR133
300K_0402_5%
Issued Date
V-
Note: X7R type
LMV321AS5X_SOT23-5
PR134
4
+IN
PR146
47K_0402_5%
1
2 ACDET
1
1
PC123
0.047U_0402_16V7K
2VREF_51125
CHG EN#
PC127
1U_0603_6.3V6M
2
G
CH GCTRL
PR130
PD102
1K_0402_5% 1SS355_SOD323-2
1
2 2
1
+5VALW
PU104
AC_ADP_PRES 30
PR129
220K_0402_5%
PU103A
LM393DG_SO8
PR142
11K_0402_1%
1
2
MMBT3906H_SOT23-3
2
P
PQ108
2
PR132
22K_0402_5%
PC124
0.1U_0402_10V7K
IADAPT
B
+3VL
Charge Detector
High 17.588
Low 17.292
PC121
@0.1U_0603_25V7K
PC122
1U_0603_6.3V6M
+3VL
+3VL
30
1
PR122
210K_0402_1%
PU103B
LM393DG_SO8
VL
CELLS
1
2
PC117
0.1U_0402_10V7K
P2
@76.8K_0402_1%
PC126
@680P_0603_50V8J
DPMDET
SRP
PC118
1U_0603_10V6K
BATT
1
PC119
100P_0402_50V8J
18
17
16
15
IADAPT
41 IADAPT
BAT
PR116
22.6K_0402_1%
4.7U_0805_25V6-K
2
1
22
ADP_PRES 30,33
2
PR125
604K_0402_1%
PR141
@4.7_1206_5%
DL_ CHG
PC113
PGND
PR127
PQ106
AON7406L
ISYNSET
CELLS
LODRV
14
SRN
EXTPWR
23
13
2VREF_51125
4.7U_0805_25V6-K
2
1
24
BATT
PR112
0.01_1206_1%
1
2
PC112
REGN
PL102
10UH_MMD-10DZ-100M-X1_6A_20%
1
2
VADJ
PR124
147K_0402_1%
PR131
10K_0603_0.1%
PC103
4.7U_0805_25V6-K
ACN
1
2
2
1
CHGEN
2
ACN
PH
12
ACP
RE GN
VDAC
25
SRSET
O
G
PR123
41.2K_0402_1%
2
1
PR128
76.8K_0402_1%
ACP
26
PQ105
SIS412DN-T1_POW ERPAK8-5
V IN
PC108
0.1U_0603_50V7K
HIDRV
11
27
AC Detector
High 11.85
Low 10.55
LPMD
BTST
+3VL
PR119
200K_0402_1%
AGND
2
PR118
1
2
255K_0402_1%
ACDET
1
2
PC110
PC109
0.1U_0402_10V7K
1U_0805_25V6K
BST_CHG 1
2
1
2
PR121
0_0402_5%
DH_CHG 1
2
PR145
0_0402_5%
LX_CHG
SRSET
2
PR115
1M_0402_1%
PC116
1U_0603_6.3V6M
P2
PR110
10_0805_1%
1
2
28
PU101
BQ24740RHDR_QFN28_5X5
P2
RLS4148_LL34-2
1
2
PR114
422K_0402_1%
BAT_PW M_OUT
30
29
PD101
VA DJ
PR113
453K_0402_1%
TP
PVCC
VREF
PR106
0_0402_5%
CHG_B+
IADSLP
10
PC106
@0.1U_0603_25V7K
CHG EN#
PU105A
LM393DG_SO8
CHG_B+
BQ24740VREF
1
2
PC111
1U_0603_6.3V6M +3VL
1
PR137
24.3K_0603_1%
1
2
1M_0402_5%
2
1
2
PR136
100K_0402_1%
PR140
23.7K_0402_1%
PR135
100K_0402_1%
1
2
PC105
1U_0603_6.3V6M
1
2
PQ103
AO4407AL 1P SO8
8
7
6
5
1
2
3
14,23,29,30,32,33,37,38 SLP_S3#
PR139
PR138
1
2
100K_0402_5%
P2
LPREF
PR109
0_0402_5%
1
2
IADAPT
2
G
PQ104
SSM3K7002FU_SC70-3
+3VL
ACSET
PC107
0.01U_0402_16V7K
1 2
VL
BATT
PR104
1
2
56K_0402_1%
ADP_EN#
2
PR103
47K_0402_5%
PR105
15K_0402_5%
PR111
150K_0402_5%
41
ACDET
+3VL
PC101
0.1U_0603_50V7K
1
2
PR101
200K_0402_5%
PL101
HCB2012KF-121T50_0805
1
2
PR102
0.01_2512_1%
1
4
1
2
3
21
8
7
6
5
4
8
7
6
5
4
1
2
3
P4
PQ102
AO4407AL 1P SO8
PC102
4.7U_0805_25V6-K
P2
PQ101
AO4407L_SO8
20
V IN
Title

Charger
Size
Document Number
R ev
0.9
LA-4902P
D ate:

D
Sheet
35
of
47
2VREF_51125
PC302
1U_0603_10V6K
1
PR304
20K_0402_1%
1
2
LG_5V
14
B++
PC315
22U_0805_6.3V6M
+3VEXTLP
+5VLP
+3VALW P
VL
+3VALW
(3A,120mils ,Via NO.= 6)
PAD-OPEN 4x4m
VL
PC321
1U_0603_10V6K
1
PD305
1SS355_SOD323-2
DEBUG_KBCRST 22,31
PJP305
+3VEXTLP
PAD-OPEN 2x2m
2
G
S
+3VL
11.5K_0402_1%
+5VLP
PJP304
+VREG3_51125
V-
-IN
2.2U_0805_10V6K
PR323
20K_0402_1%
APL5317
PR324
16.5K_0402_1%
5
PR331
OUT
PR326
470K_0402_5%
+IN
V+
FB
PR322
64.9K_0402_1%
EN
PR320
255K_0402_1%
PR321
2
+3VLP
PJP302
PAD-OPEN 2x2m
PR318
100K_0402_5%
+5VLP
PU302
KBC_PWR_ON 30
3
1
PR316
100K_0402_5%
1
2
PR317
330K_0402_5%
2
1
22,31 DEBUG_KBCRST
P2
PAD-OPEN 4x4m
PJP303
GND
VOUT
(4.5A,180mils ,Via NO.= 9)
VIN
PC320
4 1
680K_0402_5%
PD304
1
+5VALW
PR325
220K_0402_5%
2
1
PC319
10U_0805_10V6K
PJP301
PU303
+5VALW P
PQ307
SSM3K7002FU_SC70-3
PC314
0.1U_0603_50V7K
PC313
1000P_0603_50V7K
PQ303
IRFH3707TRPBF_PQFN8-3
2VREF_51125
2
PR319
@0_0402_5%
PC311
2 150U 6.3V M B2 LESR45M
1
2
PR315
@620K_0402_5%
PQ305B
2N7002KDW H-2N_SOT363-6
3
2
1
1
2
3
PR314
@100K_0402_5%
RPGOOD
PC316
10U_0805_10V6K
PU301
TPS51125RGER_QFN24_4X4
+5VLP
3 ENTRIP2
6 ENTRIP1
PQ305A
2N7002KDW H-2N_SOT363-6
PR312
2.2_1206_5%
+3VL
51125_PW R
PC306
4.7U_0805_25V6-K
PC305
4.7U_0805_25V6-K
2
1
PL303
4.7UH 20% FDVE0630-H-4R7M=P3 5.5A
1
2
+5VALWP
VIN
VCLK
18
17
EN0
13
16
DRVL2
19
12
BST_5V
3
2
1
DRVL1
LG_3V
PQ302
PR308
PC309
0_0402_5% 0.1U_0402_10V7K
PR310
1
2 1
2
0_0402_5%
1
2
LX_5V
LL2
PC304
2200P_0402_50V7K
2
1
1
2
UG_5V
20
DRVH2
11
VREG5
21
LL1
10
2
1
PC318
0.1U_0402_25V6
2
1
ENTRIP1
1
ENTRIP1
VFB1
VREF
VFB2
TONSEL
DRVH1
UG_3V
22
VL
VBST1
4
PC312
1000P_0603_50V7K
23
VBST2
24
PR311
2.2_1206_5%
1
PC310
150U 6.3V M B2 LESR45M
VO1
PGOOD
BST_3V
LX_3V
PQ304
AON7406L
VREG3
GND
PL302
4.7UH 20% FDVE0630-H-4R7M=P3 5.5A
2
1
+3VALWP
VO2
SKIPSEL
1
2
3
PR307
PR309
1
2 1
2
0_0402_5%
PC308
0_0402_5%
1
2 0.1U_0402_10V7K
15
PQ301
6
ENTRIP2
P PAD
25
4UG1_3V
2
B++
PC307
2.2U_0805_10V6K
+5VALWP
PR306
100K_0402_1%
1
2
14
PC303
4.7U_0805_25V6-K
0.1U_0402_25V6
2
1
1
2
PC301
2200P_0402_50V7K
PR305
110K_0402_1%
1
2
+3VLP
PC317
2
1
PR303
20K_0402_1%
1
2
PL301
HCB2012KF-121T50_0805
ENTRIP2
B++
B+
PR302
30.9K_0402_1%
1
2
+3VALWP
PR301
13.7K_0402_1%
1
2
1SS355_SOD323-2
LMV321AS5X_SOT23-5
PAD-OPEN 2x2m
1
PD301
1SS355_SOD323-2
VCC1_PWRGD 30,41
Compal Secret Data
EN0 34
2008/09/15
Issued Date
Deciphered Date
2010/12/31
A
Title

3.3VALWP/5VALWP

C ustom
LA-4902P
D ate:
R ev
0.9
Sheet
E
36
of
47
+VCCP
EN
1
2
BOOT
5
6
7
8
BST_VCCP
13
DH_VC CP
14
LX_VCCP
15
UG
+6269_VCC
PQ401
AO4474L_SO8
4
PVCC
12
LG
11
PGND
10
ISEN
PC406
2.2U_0805_10V6K
DL _VCCP
VO
FSET
2
PR407
8.06K_0402_1%
1
+
PC412
1000P_0603_50V7K
2
1
PC413
0.01U_0402_16V7K
PR410
49.9K_0402_1%
2
1
FB_ VCCP
PQ402
AON6718L 1N DFN
3
2
1
ISL6269ACRZ-T_QFN16
+VCCP
1
1
PC414
22P_0402_50V8J
5
PC411
@10K_0402_5%
PR409
22.6K_0402_1%
2
1
2
1
PC415
6800P_0603_50V7K
PR428
0_0402_5%
+VCCP
1
PR408
2.2_1206_5%
SE_VCCP 1
COMP
PR406
@0_0402_5%
FB
32 VCCP_EN
14,23,29,30,32,33,35,38 SLP_S3#
(18A,720mils ,Via NO.= 36)
PL402
0.47U 20% FDVE0630-H-R47M=P3 17.7A
1
2
PC410
330U_V_2VM_R6M
FCCM
PR404
2.2_0603_5%
1
2
PC409
330U_V_2VM_R6M
PR403
0_0402_5%
PC408
330U_V_2VM_R6M
VCC
PC405
0.22U_0603_10V7K
+5VALW
1
2
PR417
2 0_0603_5%
PR405
0_0402_5%
1
2
PC407
2.2U_0805_10V6K
2
PR402
0_0603_5%
3
2
1
VIN
PHASE
1
+6269_VCC
PGOOD
GND
PU401
16
VCCP_POK
17
32
PR427
PR401
10K_0402_5% @10K_0402_5%
DH_V CCP1
+3VS
2
1
PC402
4.7U_0805_25V6-K
VCCP_B+
PC401
2200P_0402_50V7K
1
2
PC416
0.1U_0402_25V6
2
1
PL401
HCB2012KF-121T50_0805
1
2
2
1
PC404
4.7U_0805_25V6-K
B+
2
1
PC403
4.7U_0805_25V6-K
2
PR411
1.5K_0402_1%
1
2
PC417
@0.1U_0402_25V6
PR412
1.96K_0402_1%
2+VCCP
PR413
10_0402_5%
2
PR414
0_0402_5%
2
PR415
0_0402_5%
VTT_SENSE 7
VSS_SENSE_VTT 7
Need to close CPU chipset
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
A
Title

1.05V_VCCP
Size
Document Number
R ev
0.9
LA-4902P
D ate:

D
Sheet
37
of
47
PJP604
+1.5V
PAD-OPEN 3x3m
PJP605
VCNTL
GND
NC
VREF
NC
VOUT
NC
TP
+5VALW
PC603
1U_0603_10V6K
PQ601A
2N7002KDW H-2N_SOT363-6
2
+0.75VSP
PC605
10U_0805_6.3V6M
PQ601B
2N7002KDW H-2N_SOT363-6
PR603
1K_0402_1%
PC606
.1U_0402_16V7K
VIN
G2992F1U_SO8
PR602
10K_0402_5%
PD601
1SS355_SOD323-2
1
2
PR601
1K_0402_1%
2
1
PC604
0.1U_0402_10V7K
PR604
20K_0402_5%
1
2
14,23,29,30,32,33,35,37 SLP_S3#
+5VALW
To resolve +0.75VS to +1.5V_CPU_VDDQ timing issue
@10U_0805_10V4Z
PC602
2
1
PU601
10U_0805_6.3V6M
PC601
2
1
PAD-OPEN 3x3m
+1.5VS_CPU_VDDQ
PJP601
+0.75VSP
+0.75VS
PAD-OPEN 3x3m
Change +1.8VS VR
BS
IN
POK
TP
PL602
1.2UH +-30% 1231AS-H-1R2N=P3 2.9A
1
2
1.8VS_POK 32
11
MP2121DQ-LF-Z_QFN10_3X3
PR606
4.7_1206_5%
+1.8VSP
PC614
22U_0805_6.3V6M
IN
PC613
22U_0805_6.3V6M
SW
SW
10
GND
EN/SYNC
2
PR609
0_0402_5%
GND
PC612
680P_0603_50V7K
@B340A_SMA2
FB
PD602
PC610
10U_0805_10V_X5R
1
2
1
2
PC611
0.1U_0402_10v_X7R
2
1
+5VALW
PL601
HCB1608KF-121T30_0603
1
2
PC607
@0.1U_0402_16V7K
14,23,29,30,32,33,35,37
PU602
PC608
0.1U_0402_16V7K
1
PC609
10U_0805_10V_X5R
+1.8VSP
316K_0402_1%
PR607
PR608
402K_0402_1%
2
1
SLP_S3#
PR605
0_0402_5%
1
2
PJP602
+1.8VSP
+1.8VS
(1.5A,60mils ,Via NO.= 3)
PAD-OPEN 3x3m
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
A
Title

0.75VSP/1.8VSP
Size
Document Number
R ev
0.9
LA-4902P
D ate:

D
Sheet
38
of
47
PR516
1
2
PC507
4.7U_0805_25V6-K
PC506
4.7U_0805_25V6-K
1
2
3
2
1
2
14.3K_0402_1%
PR513
2.2_1206_5%
PC521
4.7U_0805_10V6K
1
1
LG_1.05V
PR517
+1.05VMP_LAN
DRVL
+5VALW
V5DRV
10
14
11
4
1
PC514
4.7U_0805_6.3V6K
TPS51117RGYR_QFN14_3.5x3.5
PQ504
AON7702L_DFN8-5
PR504
10K_0402_1%
PC515
2 220U_B2_2.5VM_R25M
PC517
1000P_0603_50V7K
12
B+
PL503
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
3
2
1
PGOOD
VBST
TP
1
EN_PSV
VFB
LX_1.05V
LL
TRIP
HCB1608KF-121T30_0603
1
2
PQ502
SIS412DN-T1-GE3_POW ERPAK8-5
4
UG1_1.05V
1
2
PC526
@10P_0402_50V8J
PC520
1U_0603_10V6K
V5FILT
13
PR509
0_0402_5%
1
2
PR503
1
2
4.12K_0402_1%
+1.05VMP_LAN
VOUT
PR518
316_0402_1%
PGND
2
0_0402_5%
DRVH
UG_1.05V
1
PR519
+1.05VMP_LAN
+5VALW 1
TON
GND
PU501
PR524
255K_0402_1%
1
2 2
15
PR511
PC511
0_0402_5% 0.1U_0402_10V7K
BST_1.05V 1
2
1
2
PC505
0.1U_0402_25V6
PC519
@1000P_0402_50V7K
+5VALW
PL501
+1.05VM_LAN_B+
0_0402_5%
PC504
1000P_0402_50V7K
14,30,33 PM_SLP_LAN#
1.05VM_LAN_POK
32
PJP501
+1.05VMP_LAN
+1.05VM_LAN
PAD-OPEN 4x4m
PR521
LG_1.5V
PR515
1
2
PC509
4.7U_0805_25V6-K
1
2
PC508
4.7U_0805_25V6-K
1
2
14.3K_0402_1%
PR512
2.2_1206_5%
PC523
4.7U_0805_10V6K
PC512
2 330U_2.5V_B2_R15M
PC516
1000P_0603_50V7K
PQ503
AON7702L_DFN8-5
PC513
4.7U_0805_6.3V6K
TPS51117RGYR_QFN14_3.5x3.5
PR502
10K_0603_0.1%
1
1
DRVL
+5VALW
+1.5VP
V5DRV
10
11
B+
PL502
2.2UH_PCMC063T-2R2MN_8A_20%
1
2
TRIP
UG1_1.5V
3
2
1
LX_1.5V
UG_1.5V
12
PGOOD
VBST
TP
EN_PSV
VFB
14
15
V5FILT
13
LL
3
2
1
1
2
PC525
@10P_0402_50V8J
DRVH
HCB1608KF-121T30_0603
1
2
PQ501
SIS412DN-T1-GE3_POW ERPAK8-5
+1.5VP
PC522
1U_0603_10V6K
PR501
1
2
10.2K_0603_0.1%
VOUT
PR522
316_0402_1%
TON
PGND
+5VALW 1
2
0_0402_5%
4
PR508
0_0402_5%
1
2
+5VALW
1
PR520
GND
PR523
255K_0402_1%
1
2 2
PU502
PC502
0.1U_0402_25V6
PC524
@1000P_0402_50V7K
PR510
PC510
0_0402_5% 0.1U_0402_10V7K
BST_1.5V 1
2
1
2
+1.5VP
PL504
1.5V_B+
0_0402_5%
PC501
1000P_0402_50V7K
14,24,29,33 SLP_S4#
1.5V_POK
32
PJP502
+1.5VP
+1.5V
PAD-OPEN 4x4m
Compal Secret Data
Issued Date
2008/09/15
Deciphered Date
2010/12/31
A
Title

1.5VP/1.05VMP
Size
Document Number
R ev
0.9
LA-4902P
D ate:

D
Sheet
39
of
47
+VCCP
1 PR269 @1K_0201_5%
H _VID3
1 PR275 1K_0201_5%
H _VID4
1 PR270 @1K_0201_5%
H _VID4
1 PR276 1K_0201_5%
H _VID0
H _VID0
H _VID5
1 PR271 1K_0201_5%
H _VID5
1 PR277 @1K_0201_5%
H _VID1
H _VID1
H _VID6
1 PR272 @1K_0201_5%
H _VID6
1 PR278 1K_0201_5%
H _VID2
H _VID2
P ROC_DPRSLPVR 2
1 PR273 1K_0201_5%
P ROC_DPRSLPVR 2
H _VID3
H _VID3
H _VID4
H _VID4
H _VID5
H _VID5
H _VID6
H _VID6
1 PR279 @1K_0201_5%
PR208
0_0603_5%
2
1
BOOST_CPU2
VID[5:3]=100 for SV CPU 48A

VID[5:3]=011 for LV CPU 35A
PC209
0.22U_0603_10V7K
PR249
1
2
0_0603_5%
2
1
UGATE_C PU2
PQ201
IRFH7914TRPBF
VGATE
PSI#1
2 PR222
PR225
0_0402_5%
1
2
3
4
5
6
7
8
9
10
@56P_0402_50V8
2
PR227 @4.02K_0402_1%
1
2
1
2
PH202
@470K_0402_5%_TSM0B474J4702RE
2
10K_0402_1%
1
PR214
2
ISEN2
VSUM+
F
AGND
ISL62883HRZ-T_QFN40_5X5
2
11
12
13
14
15
16
17
18
19
20
PR229
41
PC223
1U_0603_10V6K
PC224
PR248
0_0603_5%
2
1
3
2
1
1
2
PC238
4.7U_0805_25V6-K
1
2
PC239
4.7U_0805_25V6-K
2
1
+ CPU_CORE
V 1N
1
PR257
1_0402_5%
PR259
@0_0402_5%
1
2
PH203
10KB_0603_5%_ERTJ1VR103J
1
2
L F1
1
PQ206
TPCA8028_PSO8
@10KB_0603_5%_ERTJ1VR103J
2
1
PC249 @100_0402_1%
1
21
2
PHASE_CPU1
PR252
2.61K_0402_1%
2
1
0.022U_0402_16V7K
0.22U_0603_10V7K
PR260
1.3K_0402_1%
1
2
PQ205
IRFH7914TRPBF
PL204
0.36UH 20% PCMC104T-R36MN1R105 30A
1
4
LGATE_CPU1
PH201
1
2
PR262
11K_0402_1%
2
1
VSSSENSE
0_0402_5%
2
PC247
1000P_0402_50V7K
PR263
1
PC248
330P_0402_50V7K
PC244
330P_0402_50V7K
PC243 2
0_0402_5%
PC242 2
PR251
V CCSENSE
2
1
PR250
PC245
82.5_0402_1%
0.01U_0402_16V7K
10.7K
10K
VSUM+
PC234
4.7U_0805_25V6-K
2
1
PC229
0.22U_0603_25V7K
UGATE1_CPU1
PC240
0.22U_0603_10V7K
1
2
10K_0402_1%
1.1K
PR274
0_0603_5%
2
1
UGATE_C PU1
PR256
2
1.3K
VSSSEN SE
PR255
3.65K +-1% 0603
2
1
PR260
CPU_B+
PC233
4.7U_0805_25V6-K
3.92K
PC236
0.22U_0603_10V7K
1
2.87K
PC237
0.22U_0603_10V7K
2
1
PR238
VSUM-
PR246
10K_0402_1%
BOOST_CPU1
LV
LL=-3
ISEN1
SV
LL=-1.9
PC228
1U_0603_10V6K
2
1
1
ISEN2
PR253
2
1
2.2_1206_5%
1_0402_5%
2
+5VALW
IMVP_IMON
PC246
1000P_0603_50V7K
2
1
2
PR241
412K_0402_1%
PC232
2200P_0402_50V7K
2
1
PR244
0_0402_5%
2
0_0402_5%
2
CPU_B+
PR242
PC231
0.1U_0402_25V6
2
1
PR239
1
PR238
2.87K_0402_1%
VSUM-
+5VALW
V 1N
PR228
0_0402_5%
1
2
PR236
562_0402_1%
1
2
PC225
10P_0402_50V8J
PR246
PR216
1_0402_5%
PR220
@0_0402_5%
1
2
+5VALW
PC230
0.047U_0603_16V7K
390P_0402_50V7K
2
1
2
PC221
22P_0402_50V8J
@0_0402_5%
1
2
PC222
1000P_0402_50V7K
PR235
8.06K_0402_1%
1
30
29
28
27
26
25
24
23
22
21
BOOT2
UGATE2
PHASE2
VSSP2
LGATE2
VCCP
PWM3
LGATE1
VSSP1
PHASE1
PGOOD
PSI#
RBIAS
VR_TT#
NTC
VW
COMP
FB
ISEN3
ISEN2
PC220
1
PC211
1U_0603_10V6K
1
2
CLK_EN#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
PU201
ISEN1
VSEN
RTN
ISUMISUM+
VDD
VIN
IMON
BOOT1
UGATE1
2
PR224
68_0402_5%
2
40
39
38
37
36
35
34
33
32
31
H_PROCHOT#
1
PC227
150P_0402_50V8J
+ CPU_CORE
V 2N
2
PR223 147K_0402_1%
+ VCCP
0_0402_5%
L F2
1 PR283 1K_0402_5%
2
1
3
2
1
1 PR221 @1K_0402_5%
PSI#
PC210
1000P_0603_50V7K
2
1
CLK_EN#
PR219
0_0402_5%
1
2
+VCCP
PR213
3.65K +-1% 0603
2
1
LGATE_CPU2
PR215
47K_0402_1%
1
2
TPCA8028_PSO8
+3VALW
12,14
PR211
PQ202
CLK_EN#
PL202
0.36UH 20% PCMC104T-R36MN1R105 30A
1
4
2.2_1206_5%
P ROC_DPRSLPVR
P ROC_DPRSLPVR
11
3
2
1
P GD_IN
+
2
PHASE_CPU2
5
14,30
PM_PWR OK
2 220_0402_5%
UGATE1_CPU24
PR209
B+
2
1
PL203
HCB2012KF-121T50_0805
H _VID3
PL201
HCB2012KF-121T50_0805
2
1
CPU_B+
PC206
100U_25V_M
1 PR282 @1K_0201_5%
H _VID2
PC204
4.7U_0805_25V6-K
2
1
1 PR268 1K_0201_5%
PC208
4.7U_0805_25V6-K
1 PR281 @1K_0201_5%
H _VID2
1 PR280 @1K_0201_5%
PC203
4.7U_0805_25V6-K
2
1
H _VID1
PC207
4.7U_0805_25V6-K
H _VID0
1 PR267 1K_0201_5%
PC202
2200P_0402_50V7K
2
1
1 PR266 1K_0201_5%
PC201
0.1U_0402_25V6
2
1
H _VID1
3
2
1
H _VID0
V 2N
VSUMB
ISEN1
VSUM+
VSUM-
PC250
0.1U_0402_10V7K
@1200P_0402_50V7K PR265
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2010/12/31
Title
CPU_CORE
Size
Document Number
R ev
0 .9
L A-3942P
Date:
40
Sheet
1
of
47
BQ24740VREF
PR1000
165K_0402_1%
2
+5VS
PU1000
PR1013
10K_0402_1%
+IN
V-
-IN
V+
OUT
LMV321AS5X_SOT23-5
PR1017
2K_0402_5%
PR1018
76.8K_0402_1%
PD1001
1SS355_SOD323-2
SRSET
C
PR1019
10K_0402_5%
OCP_A_IN
30
2OC P_A_IN
PR1032
100_0402_5%
1
PR1033 @0_0402_1%
1
2
OCP
VCC1_PW RGD
OCP#
15
PQ1004
SSM3K7002FU_SC70-3
PR1035
PU1004B
LM393DG_SO8
+3VS
10K_0402_5%
+3VL
PR1027 100K_0402_1%
30,36
O
4
PD1004
1SS355_SOD323-2
AD P_A_ID
PQ1006
MMBT3906H_SOT23-3
3
3
PQ1007B
2N7002KDW H-2N_SOT363-6
PR1046
8.66K_0402_1%
2
1
+3VL
PC1004
0.01U_0402_16V7K
1
2
35
ADP_EN#
100K_0402_1%
2
1
2
1
PR1045
4.7K_0402_5%
PR1042
8.06K_0402_1%
PR1029
PR1040
33K_0402_5%
+5VS
1
PR1031
1
PR1030
68K_0402_5%
2
PR1020
0_0402_5%
2
G
PR1034 200K_0402_1%
1
2
100K_0402_1%
30
V IN
PD1003
GLZ4.7B_LL34-2
PR1026
PQ1005
MMBT3904W H_SOT323-3
1
2 2
B
PR1028
100K_0402_5%
27.4K_0402_1%
PC1003
3900P_0402_50V7K
NDS0610_NL_SOT23-3
3.9K_0402_5%
PR1025
PQ1003
1
2
PR1022
100_0402_5%
+3VS
35
ADP_SIGNAL
PD1000
1SS355_SOD323-2
IADAPT
35
PC1001
0.01U_0402_16V7K
PC1000
0.22U_0603_10V7K
PR1059
45.3K_0402_1%
PU1004A
LM393DG_SO8
PQ1007A
2N7002KDW H-2N_SOT363-6
2VREF_51125
ADP_EN
30
+3VL
2
PR1062
1M_0402_5%
VL
PR1064
22K_0402_5%
O
4
PR1065
10K_0402_1%
ADP_DET#
30
PU105B
LM393DG_SO8
PR1063
130K_0402_1%
2AD P_A_ID
ADP_A_ID
Compal Secret Data
30
2008/09/15
Issued Date
PR1066
10K_0402_5%
Deciphered Date
2010/12/31
4
Title

ADP_OCP

C ustom LA-4902P
D ate:
R ev
Sheet
1
41
of
47
PC708
0.22U_0402_6.3V6K
PC706
1U_0603_10V6K
2
1
PR703
22.6K_0402_1%
1 1
GFXVR_IMON
2
PR715
0_0402_5%
VSS_AXG_SENSE
5
6
7
8
ISUM+
ISUM-
3
2
1
5
1
PQ702
AON6718L 1N DFN
PR709
0_0402_5%
2 1
PH701
PC718
2.2U_0603_10V7K
VID2
21
PR708
3.65K_0603_1%
20
1000P_0603_50V7K
VID0
+GFX_CORE
C
PR707
2.2_1206_5%
PR713
1
2 +5VALW
4
0_0603_5%
3
2
1
19
1
18 DL_GFX
13
12
14
BOOT
IMON
10
11
VDD
9
ISUM
ISUM+
VIN
VID3
17
PR714
10KB_0603_5%_ERTJ1VR103J
2.61K_0402_1%
(15A,600mils ,Via NO.= 30)

PR717
1
2
11K_0402_1%
PC722
1
2
GFXVR_PW RGD
1
2
PC724
0.1U_0402_16V7K
PR723
3.01K_0402_1%
PR729
82.5_0402_1%
1
2
1
2
0_0201_5% 2
0_0201_5% 2
1
1
PR731
PR732
GFXVR_VID_0 7
GFXVR_VID_1 7
GFXVR_VID_2 7
GFXVR_VID_3 7
GFXVR_VID_4 7
GFXVR_VID_5 7
GFXVR_VID_6 7
GFXVR_EN 7
GFXVR_DPRSLPVR
GFXVR_CLKEN#
PC725
0.01U_0402_16V7K
0.1U_0402_16V7K
PR725
@100_0402_1%
ISUM+
32
PL702
0.56UH +-20% PCMC104T-R56MN 25A
1
2
PR734
8.06K_0402_1%
2 DH_GFX1
16 LX_GFX
22
PR735
17.8K_0402_1%
15 DH_GFX
VCCP
VID1
23
PC721
22P_0402_50V8J
1
2
1
PR720
@10K_0402_1%
CLK_EN#
28
1
+GFX_CORE
PGOOD
VID4
LGATE
RBIAS
24
PQ701
AO4474L_SO8
PC710
0.22U_0603_10V7K
PC720
150P_0402_50V8J
VW
VID5
2
1
PR719
@1.91K_0402_1%
1 2
4
1 3
2
2 1
PC716
100P_0402_50V8J
VSSP
25
PR712
47K_0402_1%
COMP
UGATE
VID6
PC717
1000P_0402_50V7K
FB
PR733
0_0603_5%
PU701
ISL62881HRZ-T_QFN28_4X4 PHASE
VR_ON
PR711
825K_0402_1%
VSEN
26
AGND
7
PR710
10.5K_0402_1%
2
1
RTN
PC711
330P_0402_50V7K
DPRSLPVR
PC712
330P_0402_50V7K
27
PR706
10_0402_5%
1
2
+GFX_CORE
PR705
0_0603_5%
29
VCC_AXG_SENSE
BST_GFX 1
1
2
PC709
1000P_0402_50V7K
VSS_AXG_SENSE
PC719
1
2
1
+5VALW 2
1_0402_5%
PC707
0.22U_0603_25V7K
PR702
0_0402_5%
PR704
10_0402_5%
1
2
PR701
PC727
0.1U_0402_25V6
2
1
PC702
4.7U_0805_25V6-K
1
2
2
1
PC705
4.7U_0805_25V6-K
GFX_B+
PL703
HCB2012KF-121T50_0805
1
2
2
1
PC704
4.7U_0805_25V6-K
PL701
HCB2012KF-121T50_0805
1
2
PC701
2200P_0402_50V7K
B+
2
1
PC703
4.7U_0805_25V6-K
PC726
@1200P 50V K X7R 0402
ISUM-
Compal Secret Data
2008/09/15
Issued Date
Deciphered Date
2010/12/31
5
Title

VCCGFX

C ustom LA-3942P
D ate:
R ev
Sheet
1
42
of
47
Version change list (P.I.R. List)
Item
Power section
Reason for change
PG#
For all SMSC1098 platforms, please change

the signal "AC_AND_CHG" to "AC_ADP_PRES".
This is to keep up with AC adapter table changes made

in KBC code.
Page 1 of 1
Modify List
Date
Phase
35
To best solve the issue of +15V combo adapter

(airline adapter) detect, reserve PR127, Add
PR128 76.8K +-1% 0402.
2009/5/4
DB-2
41
PR1042 change the value from 21K +-1% 0402 to 8.06K +-1% 0402.
PR1059 change the value from 24.9K +-1% 0402 to 45.3K +-1% 0402.
PR1046 change the value from 4.12K +-1% 0402 to 8.66K +-1% 0402.
2009/6/29
SI-1
2009/8/28
SI-2
Change PR604 to 15K to resolve +0.75VS to

+1.5V_CPU_VDDQ timing issue seen on Cartier/Dior/Versace.
38
PR604 change the value from 10K to 20K.

PD601 add the component 1SS355.
PC606 add the component 0.1uF_0402_16V7K.
To workaround TPS51125 turn on abnormal issue,

need to make sure total caps on +5VL rail is at least
30uF. Currently only have 20.2uF.
36
Add PC316 10U_0805_10V6K

PC307 change the value from 10U 6.3V M X5R 0805
to 2.2U 10V K X5R 0805.
PC315 change the vlaue from 10U 10V K X5R 0805
H1.25 to 22UF 6.3V M X5R 0805 H1.25.
2009/8/29
SI-2
The +1.8VS power rail is very inefficient and

want to change to a better solution.
36
Change +1.8VS VR schematic.
2009/9/16
SI-2B
For ULV CPU design reserve.
40
Reserve PR229 / 0_0402_5% and

PH203 10KB_0603_5%_ERTJ1VR103J
2010/01/04
MV
Compal Secret Data
Issued Date
2008/09/15
2010/12/31
Deciphered Date
5
Title

Changed-List History
Size
D o c ument Number
R ev
0.9
LA-4902P
Date:
Sheet

1
43
of
47
I tem
<2009.01.12>
Fixed Issue and change item
PA GE
Reduce un-install parts for XDP-CPU
Add test points at XDP-CPU
Reduce eDP lane to meet panel resolution.
Add 1uf Caps to meet Intel design gude at +VCAP0, +VCAP1
Mod ify List
M. B. V er.
Del R4, R6, R8, R11, R40, R41, R43, R48, R49
0.1
Add T112, T113
0.1
Reduce lane1, 2
0.1
add Caps account to 12pcs
0.1
Add 1uf Caps to meet Intel design gude at +Vccp
add Caps account to 24pcs
0.1
Add L31 at +VTT_DDR
add L31
0.1
Add L32 at +VDDQ_CK
add L32
0.1
Change R171 net name at XDP-PCH
12
Change USB_OC#6 to PCH_XDP_GPIO10
0.1
Add R190 at XDP-PCH
12
add R190 & USB_OC#4
0.1
10
Change pull up for Intel Design Guide
13
change pull up to contact to R206 pin1
0.1
11
Remove LVDS for HP request
14
Remove LVDS-A channel
0.1
12
change value for HP request
15
change R270, R274 value to 39ohm
0.1
13
Add Resisters for XDP-PCH
15
Add R351, R265
0.1
14
Change R295 net name at XDP-PCH
15
Change USB_OC#7 to WOW#
0.1
15
Change value
25
Change R451 tolerance to 1% and C441 tolerance
0.1
16
Change value
0.1
<2009.01.14>
<2009.01.15>
B
<2009.01.16>
25
Change C428 value to 1000P
12
Remove SATA-2 channel
24
Remove E-SATA support circuit
0.1
Remove E-SATA for HP request
Change USB group for HP request
15
Change USB-1 from Right side to Rear-1 side
Modify Audio circuit
26
Add FET and support circuit for SENSE.
27
Change Audio jack
0.1
Add R703, C637
0.1
0.1
Add 4.7Kohm pullup to +3V and a 0.01uF capacitor at HDA_RST#
26
Change Audio Gain dB
26
R486 & R491 install ; R485 & R492 un-install.
0.1
Delete channel-C signals of DP
14
Delete channel-C signals of DP
0.1
Change power USB control method
24
change Power USB solution to one chip control solution
0.1
change Audio Dock
26
change R510, R515 value to 100k and R510, R515 pin1 contact to A-GND
0.1
Add Ext-Mic Amp.
27
Add Ext-Mic Amp.
0.1
Change XDP-CPU net
JP4 [28,30] connect to CFG [10:11]. JP4 [34,36] connect to CFG [6:7].
0.1
Change eDP_AUXN contact to CPU pin
MB_C_DP_AUXN should connect to U1A.D19.
Remove CFG7 (No support)
delete R71.
Add pull up for HP request
Add 10K (R705) NI pull-up to +VCCP on GFXVR_EN.
GFX_CORE needs high frequency decoupling.
Add 16x0402 1uF caps.
VTT pins contact wrong power source
Change VTT pin to +VCCP
0.1
CPU_CORE missing high frequency decoupling.
Add 25x0402 1uF caps.
0.1
Change LAN power source control method
21
C330 - C333, C329, R383, R386, Q21uninstall and change "LAN_CTRL_18" to "LAN_CTRL_10"
0.1
Add USBP6 for support WiMax.
22
Add USB channel 6
0.1
Line in / out sense circuit
pin1 &
0.1
0.1
0.1
0.1
15
Compal Secret Data
2006/02/13
Issued Date
2010/12/31
Deciphered Date
5
Title

HW PIR(1)

Custom LA-5251P
Date:
R ev
0.9
Sheet
1
44
of
47
KAT10 from DB-2 to SI-1 LA-5251P REV:0.2 -> 0.3 Modify <2009.06.08.~2009.07.02. >
Rev. Item Date Impact
Page
Change Cause
Modify Description
0.3
6/12
CKT,Layout
29
-To avoid Docking side DP monitor signals back drive PCH during S3/S4/S5 <HP>.
-Change JP30 Pin 8 connection from NC to SLP_S3#
0.3
6/12
CKT,Layout
29
-New add SATA_LED# to monitor stand port <HP>.
-Change JP30 Pin 39 connection from NC to SATA_LED#
0.3
6/14
CKT,BOM,Layout
18,29
0.3
6/16
BOM
19
-Change CRT Switch design from TI/TS5A3157 to MAXIM/MAX4885E

for Layout Quality improve also Components reducing. <Compal>
-Correct the DP design. <HP>
-Make R338 & R344 no install. Make R332 & R337 installed.
0.3
6/16
CKT,Layout
23
-Current placement of C933 is ineffective to limit inrush current.<HP>
-Change net connection and move C933 to in between R1079.2 and R1077.1.
0.3
6/16
CKT,Layout
13
-Reserve back the 25MHz design circuit. (Reserve Y3, R210,C199); Move R1093 to close to Y3 and C199.
0.3
6/16
CKT,BOM,Layout
26
-Add back the 25MHz XTAL_IN circuit for Intel workaround on sighting #400750 3306048 - 96MHz jitter.<HP>
-Audio Amp Int. regulator design concern.<HP>
0.3
6/16
CKT,BOM,Layout
15,20
-To leverage the LDO regulator of the camera modules.<HP>
-1.Change R365 from 0_0201 to 0_0402. Change R569,R613 from 100K_0201 to 100K_0402.Change R377 from 100K_0201_1% to
100K_0402_1%.
2.Rename WEBCAM_OFF to WEBCAM_ON and connect PCH GPIO37(U7.AB13) through WEBCAM_ON_R by R375(0_0402) to JEDP1.18.
3.Connect +5VS_WEBCAM to +5VS through R304 (0_0603) close to JEDP1.24 and move C316~C319 close to JEDP1.24. Del
Q17,C315,C321,R360-R362,R367,R373.
4.Change U7.AB13 and R287.1 connection from PCH_XDP_GPIO37 to WEBCAM_ON. Change R287 from 10K_0201 to
@10K_0402(uninstall).
5.Change U7.F16 connection from WEBCAM_OFF to USB_OC#2 and add pull-high R301(10K_0201) to +3VALW.
-Correct JP27 connection from currently Pin1:+5VS,Pin2:RIGHT,Pin7:GND,Pin8:GND to Pin1:RIGHT,Pin2:NC,Pin7:NC,Pin8:+5VS.
-Add U13,R319 (10K_0402);Remove and Del C550,C551,C552,Q12,U11,U12,U29,U30,U31,R320,R321,R327,R328,R329,R330;Del D5,D6,D7.
-Add R490 (100K_0402) close to U24.25 to connect U24.25 and PLT_RST#.
0.3
6/17
CKT,Layout
28
-Correct the TouchPoint pin connection.<Compal>
0.3
10
6/18
CKT,Layout
16
-Simplify the reserve circuit.<HP>
-Del C277(@10U_0603). Move C276 and related routing to bottom layer 0 mm limit high area without vias.
0.3
11
6/18
CKT,Layout
30
-Design Change for KBC I/F power rail synchronize.<HP>
-Change U8.5 power from +3VALW to +3VL.
0.3
12
6/18
CKT,BOM,Layout
24
-Change JP13,JP14,D18,D19,D20 USB pairs net connection and add or reserve R352,R350,R354,R353,R360,R355,L8,L9,L19,L26. Change
R443,R444 from 0201 to 0402 and also the net connection.
-Change U8.5 power from +3VALW to +3VL.
-Add F2(FUSE) between R349.2 and JDP1.20 for Safty solution.
0.3
13
6/18
CKT,BOM,Layout
30
-Add common mode chokes on all USB walk-up ports to address PCH EMI
issue on full/low speed USB devices.<HP/INTEL>
-Design Change for KBC I/F power rail synchronize.<HP>
0.3
14
6/18
CKT,BOM,Layout
19
-Add fuse (0.5A) for DP Safty solution.<Compal>
0.3
15
6/22
CKT,Layout
16
-Layout Placement Limitation.<Compal>
-Del C277(@10U_0603) and C276, add the test points T126,T127 for the ball pins.
0.3
16
6/25
CKT,Layout
22
-Change 1.8"HDD design from cable to Board to Board connection.<HP>
-Del JHDD1 and JHDD2 Cable design. Add JHDD3 B to B directly connect design.
0.3
17
7/1
CKT,Layout
25
-Need to add ESD protection to SC_DATA, SC_RST, & SC_CLK.<HP>
-Reserve D54,D55,D56 ESD protection design as what Ricoh recommend.
0.3
18
7/1
CKT,BOM,Layout
11
-Reserve Low Power CLK Gen design.<Compal>
0.3
19
7/1
CKT,BOM,Layout
12,20
-Make the LID_SW# design change for leakage issue fix.<HP>
0.3
20
7/1
CKT,BOM,Layout
13
-Fix INTEL Chipset Issue impact DP function. <HP/INTEL>
-Modify U6 Pin1,17,24 connection from +3VS_CK505 to +3VS_CK505_G (+3VS and +1.5VS option for tuture); Add R143(0ohm_0603)
to +3VS and reserve R120(@0ohm_0603) to +1.5VS but place close to U6.
-Change Q56.5 from DISP_OFF# to LID_SW#; Del D10(DAP202U); Add R361(10K_0402) close to U7; Add D57(CH751H); Remove
R356(10K_0402);Change U7.J30 and R135.2 connection from LID_SW# to LID_SW#_ISO#.
-Del T122, Del R1093(0_0402) and replace by add C200 (18P); Install R210,Y3,C199 by Intel finalized DP workaround and need them.
0.3
21
7/1
CKT,BOM,Layout
13,21
-Follow INTEL Design Change. <HP/INTEL>
-Remove R388 (0_0201); Connect U14.48 through add R407 (0_0402) to U7.U4 (R202.2) by INTEL request.
0.3
22
7/1
CKT,BOM,Layout
30
-Follow SMsC KBC Chip Design Change and VCC1 decoupling improve. <HP/SMsC>
-Add C565 (0.1U_0402) on and close to U32.14 for VCC1 decoupling improve by SMsC request; Change C559 from 4.7UF_Y5V to 4.7UF_X5R.
0.3
23
7/1
CKT,BOM,Layout
30,14,22
-Design simplify on both EE and PWR from HP. <HP>
0.3
24
7/1
CKT,BOM,Layout
33
-Add +VCCP and +GFX_CORE discharge circuit. <HP>
-Del D37(@CH751H) and related. Remove R246,R422,and delete PR217.

Add 1K VGATE to PGD_IN resistor at PCH pin M6. Connect PGD_IN through add R408 (1Kohm_0402) to PCH U7.M6.
-Add R699,R702,Q41 for +VCCP and +GFX_CORE discharge
0.3
25
7/1
CKT,BOM,Layout
22
-Half size mini card I/F transfer design reserve for future. <Compal>
0.3
26
7/1
CKT,Layout
22
-Update the Symbol and PCBFootprint for meet. <Compal>
-Del T87, Add R475 (0_0201) and R453 (0_0402); Reserve R433,R437,R432,R421,R431,R441 close to JP6 bottom layer under the module
area for reworkable.
-Update JODD1 PCB Footprint from ALLTO_C18522-11303-L_13P_NR to TYCO_2023233-3_13P_NR
0.3
27
7/2
CKT,BOM
15
-Simplify the design for save power consumption. <HP>
-Change R279 from 10K_0201 to 100K_0201.
0.3
28
7/2
CKT,BOM,Layout
23
-Design change for WWAN Power Rail. <HP>
0.3
29
7/2
CKT,Layout
15
-Design change for LAN_DIS#. <HP>
-Change R1077.1,C933.1,Q77.3,J3.2 connection from +3VS to +3VALW for WWAN power rail. Install C933(1000P_0402) in order to slow
+3V_WWAN bring-up
-LAN_DIS# R298 should be pulled-up to +3VM_LAN instead of +3VALW.
0.3
30
7/2
CKT,BOM,Layout
12
-Design change for LID_SW#. <HP>
-Delete R135 since it is a duplicate. Change R361 to 100K_5%. Add 100K_5% pull-up to +3VL on LID_SW# and close to U32.64.
0.3
31
7/2
CKT,BOM
30
-Update the Board ID setting for SI-1. <HP>
-For SI-1 Board ID detect, make R574 installed & make R575 no install.
0.3
32
7/2
CKT,BOM
30
-Remove R589 on KBRST# pull-high to +3VL. Change R607 on PM_RSMRST# from 10K to 100K to reduce current.
0.3
33
7/2
CKT,Layout
31
-Design change the USB I/F FPR ESD solution. <HP>
-Change the ESD diode (D39.4) power supply from +3VALW to +5VALW.
0.3
34
7/2
CKT,BOM
31
-Remove R626 (0_0201) since there is an internal pull-down in U34.
0.3
35
7/2
CKT,Layout
28
-Reserve Caps solution on STB_LED# for EMI verify. <Compal EMI>
-Reserve C536(1000P_0402) Cap on STB_LED# close to JP22.8 for EMI noise issue verify.
0.3
36
7/3
CKT,Layout
23
-New Card Power Switch design change for portload test improve. <TI>
-Connect U17 pin 12 and 14;pin2 and pin4;pin11 and 13;pin3 and 5 for express card portload test.
0.3
37
7/3
CKT,BOM,Layout
12,13
-GPIO13 has internal pull-down which is source of leakage. <HP>
0.3
38
7/3
CKT,Layout
20
-Current draw on INVPWR_B+ could be very high.<HP>
-Change U7.J30 connection from LID_SW#_ISO# to T122. Change U7.B9 connection from SMBALERT# to LID_SW#_ISO#. Del R193
(10K_0201) +3VALW PH.
-Change JEDP1 pin6 connection from +3VS to INVPWR_B+.
0.3
39
7/3
CKT,BOM,Layout
30
-Save one resistor but also reduce the two long traces.<HP>
-Del R594 (220_0402) (PM_PWROK)
Compal Secret Data
2006/02/13
Issued Date
2010/12/31
Deciphered Date
5
Title

H/W2 EE Dept. PIR SHEET(2)

Custom LA-5251P
Date:
R ev
0.9
Sheet
1
45
of
47
KAT10 from SI1 to SI1-R LA-5251P REV:0.3 -> 0.4 Modify <2009.07.07.~2009.07.14. >
Page
Change Cause
Modify Description
0.4
7/8
CKT,BOM,Layout
32
-To fix INTEL CPL S3 Power Leakage Issue <INTEL>.
--Update U38 Symbol. Add one new signal "VCCP_1.5VSPWRGD" be generated from VCCP_EN through an new add AND gate U77 to R12.2 .
0.4
7/8
CKT,BOM,Layout
4,15
--Change R12.2 connection from +1.5V to VCCP_1.5VSPWRGD. Change R12 from 1.1K_0402_1% to 4.99K_0402_1%; Change R13 from
3K_0402_1% to 2.49K_0402_1%. Change U1.BJ12 connection from DRAMRST# to SM_DRAMRST# by add Q52 which control by
PCH_DDR_RST new connect from U7.F10 (PCH GPIO8)(GPIO8-->PCH_DDR_RST) and with add R1093 (1K_0402) PH to +1.5V, add R1092
from @10K_0402 to 100K_0402.
0.4
7/8
CKT,BOM,Layout
33
--Add new Power from +1.5V to +1.5VS_CPU_VDDQ by add U45,C624,C625,R1104 close to C152; Add +1.5VS_CPU_VDDQ discharge circuit
by add R1103(470_0402) and Q52B (already exist) close to U45.
0.4
7/8
CKT,BOM,Layout
7,10
--Change U1 VDDQ Power source from +1.5V to +1.5VS_CPU_VDDQ but keep C20~C27 at the same place; Del C145,C146,C119,C120
10UF_0603 reserve for U45 and related placement.
0.4
7/9
CKT,BOM,Layout
32
--Change U77.1 connection from VCCP_EN to SLP_S3# reserve through R6(@0_0402) or to +3VALW through R4 (8.2K_0402).
0.4
7/9
CKT,BOM
33
--Install R693 (470_0201) and Q53 (2N7002).
0.4
7/9
CKT,BOM,Layout
4,5
--Change R1092 PD connection from PCH_DDR_RST to SM_DRAMRST# and close to U1.BJ12. Add C6 (470P_0402) close to Q52.2.
0.4
7/10
CKT,Layout
--Change L32.2 connection from +1.5V to +1.5VS_CPU_VDDQ.
0.4
7/10
CKT,BOM,Layout
33
--Add C626,C664 close to JDIMA1;C656,C657 close to JDIMB1.
0.4
10
7/17
CKT,BOM
-To meet Intel electrical requirements <INTEL>.
--Change back R12 from 4.99K_0402_1% to 1.5K_0402_1%; R13 from 2.49K_0402_1% to 750_0402_1%.
0.4
11
7/17
CKT,BOM,Layout
33
-To meet Intel ramp down timing for 1.5V and 0.75VS <INTEL>.
--Change R1103 from 470_0402 to 220_0402; R693 from 470_0201 to 22_0402.
0.4
12
7/17
CKT,BOM
33
--Remove R1092 (100K_0402).
0.4
13
7/17
CKT,BOM,Layout
33
-Toto avoid a glitch while turning on +1.5V_CPU_VDDQ <HP>
--Add C505 (@0.01UF_0402) close to U45.4.
0.4
14
7/17
CKT,BOM
24
-Correct BOM <Compal>
--Change U18 and U20 from SA000027C00 (G548A2P8U MSOP) to SA00002WY00 (G548A1P8U MSOP) for BOM correct.
0.4
15
7/22
CKT,BOM,Layout
28,30
--Disconnect LANLINK_R# from KBC (GPIO24/KSO16) by through R608(@0_0402) reserve; Rename GPIO24 of KBC to PWRBTN_OUT#;
Install R550 (Change R550 from 100K_0201 to 100K_0402); Disconnect the PWRBTN# output from the button switch to the PCH by remove
D34; Connect ON/OFFBTN# from KBC GPIO24 to the PCH let KBC can now control the PWRBTN#.
--Reserve CPU_SV_ID_DET with R551(@100K_0402)PH and R553(@100K_0402)PD.
0.4
16
7/22
CKT,BOM,Layout
30
-Design change ON/OFF# control from PCH directly become through EC. <HP>
<KBC will block the PWRBTN# and hold PWRBTN_OUT# HIGH when it receives a
command from the BIOS indicating BOOT BLOCK reprogramming is in progress.>
-Design reserve for themal fan table switch for SV/LV CPU type detect. <Compal>
0.4
17
7/22
CKT,Layout
15
-Design reserve for themal fan table switch for SV/LV CPU type detect. <Compal>
--Add R302(@10K_0201) PD close to R280 on PCH GPIO15.
0.4
18
7/24
CKT,BOM
26
-Increases attenuation of PC beep to an acceptable loudness level. <HP>
--Change R484 from 100K_0201 to 300K_0201.
0.4
19
7/24
CKT,BOM
26
-Increases line in attenuation from -6dB to -10dB. <HP>
--Change R502, R504 from 4.7K_0402_5% to 6.04K_0402_1% & R503, R505 from 4.7K_0402_5% to 2K_0402_5%.
0.4
20
7/24
CKT,BOM
36
-Per TI's recommendation for 3VLP. <TI>
--Change PC307 from 10U_0805_6.3V6M to 2.2U_0805_10V6K.
KAT10 from SI1-R to SI2 LA-5251P REV:0.4 -> 0.5 Modify <2009.08.11.~2009.08.28. >
Page
Change Cause
Modify Description
0.5
8/18
CKT,Layout
32
-To avoid the thermal module Assy. risk. <Compal DFx>.
0.5
8/25
CKT,Layout
20
-To disconnect LID_SW#_ISO# from LID_SW# function. <HP>.
--Add back H31 and make the DDR routing modify for this.
--Reserve R366 (@0_0402 ohm NI) resistor between Q56-1 and R361-2.
0.5
8/25
CKT,Layout
28
--Change JP28-1 from +3VL to +VREG3_51125 power rail.
0.5
8/25
CKT,BOM,Layout
14,31
-To fix false CBB button triggering on AC insertion due to noise seen on +3VL
power rail. <HP>.
-Disconnect LPC_PD# from TPM U34. <HP/Intel/Infineon>.
0.5
8/25
CKT,BOM,Layout
15,23
-Rename WOW# (U7F-T15) to CPPE# and connect to JEXP1-17 & U17-10. <HP>.
--Change U7.T15 GPIO14 connection through R265(0_0402) from WOW# as NC to CPPE# which connect to ExpressCard JEXP1-17 & U17-10.
0.5
8/25
CKT,BOM
26
-Correct the Audio Amp. Gain setting. <Compal>.
--Remove R485 (0_0201).
0.5
8/28
CKT,BOM
-Prevent glitch on DRAMRST#. <HP>.
--Change C6 from 470P to .1U_0402.
0.5
8/28
CKT,BOM,Layout
26
-Change audio REG_EN pin to +5VALW to prevent pop sound on warm boot. <HP>.
--Change R490.2 connection from PLT_RST# to +5VALW.
0.5
8/28
CKT,BOM
12
-Remove PCH Debug Port related to save power consumption. <Compal>.
--Remove R158,R156,R167,R165.
0.5
10
8/28
CKT,BOM,Layout
29
-Cancelled Docking +5VS Caps design reserve before for design simplify. <Compal>.
--Del C543 (10U_0805), C544~C546 (0.1U_0402).
0.5
11
8/28
CKT,Layout
32
-Cancel Skew Hole because of M/E PCB outline change. <Compal>.
--Del H27 (H_3P0).
0.5
12
8/28
CKT,BOM,Layout
19
--Del L12~L16(@WCM-2012-900T_4P),R331,R333,R334,R335,R336,R339,R340,R341,R345,R347(0_0402) and related Net.
0.5
13
8/28
CKT,Layout
18
--Reserve C315,C320,C321(@10P_0402) close to R316,R317,R318.
0.5
14
8/28
CKT,BOM
23
-Cancel Swatch system side Display Port Common Mode Choke reserve for design
simplify and layout space free. <Compal>.
-Reserve 10PF caps on VGA_RED_R, VGA_GRN_R, VGA_BLUE_R for EMI backup
solution. <Compal>.
-Cancel Braidwood support but keep design reserve. <HP>.
0.5
15
8/31
CKT,BOM,Layout
12
-Add back PCH GPIO13 Ext. Pull-High to +3VALW. <HP>.
--Change U7.J30 connection from T122 to become PCH_GPIO13 and pull-high to +3VLAW through R8(10K_0402).
0.5
16
9/01
CKT,BOM,Layout
28
-WW_LED# Design change for fix WWAN Module LED issue. <HP/Compal>.
--Del Q33,Q35,R542 Change R1097,R1098,R1099 value and connection.
0.5
17
9/01
CKT,BOM,Layout
24
-Stakup USB Connector update fro Compal DFb review. <Compal>.
--Chaneg JP13 PCB Footprint from SUYIN_020122MR008S51CZL_8P to SUYIN_020122GR008S51CZL_8P-T.
0.5
18
9/03
CKT,BOM
15
-Cancel Braidwood support but keep design reserve. <HP>.
--Remove R257 (@32.4_0402_1%).
0.5
19
9/03
CKT,BOM
23
-To resolve slow turn off of +3V_WWAN. <HP>.
--Install R1077 (10K_0402_5%).
--Change U7.P8 connection from LPC_PD# to SUS_STAT# as NC with only T87 test pad only. Add R367 4.7K_0402 with PH +3VS on U34.28.
--Remove R567,R562,C571,C566,JP11.
0.5
20
9/03
CKT,BOM
26
-To fix EQ setting make the changes. <HP>.
--Remove R491 (@100K_0201) ; Add R485,R486 (0_0201_5%).
0.5
21
9/10
CKT,BOM
--
-To correct the symbol inside information to make value match with SMT BOM for
long-term. <Compal>.
--Change U8 from SA000023O00 to SA00003FF00; Q13 Q14 Q15 Q16 Q29 Q30 Q31 Q32 Q36 Q40 Q41 Q43 Q44 Q45 Q46 Q47 Q48
Q49 Q50 Q51 Q52 Q56 from SB570025280 to SB00000AR10; U17 from SA00001SL00 to SA00001SL20; U18,U20 from SA00002WY00
to SA000037P00; Q19, Q22, Q23, Q26, Q38, Q39 from SB923010030 to SB00000H500; U14 from SA00002MO10 to SA00002MO40; U6
from SA00002WX00 to SA00003NM00; U2 from SA000021J00 to SA00002ZT00; Change U46 from SA097010020 to SA097010040;
Correct L31 Value from TDK-MPZ140BS300A 0603 to 0_0603_5% for match; Correct L32 Value from 1UH_SQV322520T-1R0M-N_20% to
0_0603_5% for match; Install R551 (100K_0402) as default setting; Remove R143(@0_0603) and add R120(0_0603) for LP CLK Gen.
power as default setting; Remove &U1 for SMT BOM Match
0.5
22
9/11
CKT,BOM
23
-To reduce power consumption. <HP>.
--Remove R1077 (@10K_0402)

Compal Secret Data
2006/02/13
Issued Date
2010/12/31
Deciphered Date
5
Title


Custom LA-5251P
Date:
R ev
0.9
Sheet
1
46
of
47
KAT10 from SI2 to SI2-R LA-5251P REV:0.5 -> 0.6 Modify <2009.09.11.~2009.09.29. >
Page
Change Cause
Modify Description
0.6
9/21
CKT,BOM,Layout
11,24
-To fix BT turn off time (>250mS spec) <HP>.
0.6
9/22
CKT,BOM
-Move +GFX_CORE Bulk Caps from Power related to EE related. <Compal>.
--Change CLK Gen CK_PWRGD from Q7(2N7002_SOT23-3) to Q55(2N7002DWH 2N SOT363-6); Add Q55B 2N7002 discharge FET on
+3VAUX_BT; Add R135 (470_0402) series resistor between drain of FET and +3VAUX_BT. Reserve C506 (@0.1UF_0402) for tune.
--Change PC713,PC714 location name to C973,C974.
0.6
9/28
CKT,Layout
20
-To prevent inrush current problem seen on some panels. <HP>.
--Reserve Q28(SI2301),C975,C976,R1105,R1106 close to JEDP1.
0.6
9/28
CKT,Layout
20
-To reserve the EMI solution for verify. <Compal-EMC>.
--Reserve Reserve R372,C665 close to JEDP1.
0.6
10/01
CKT,BOM
21
-To fix crystal frequency stability risk. <INTEL>.
--Change C341 and C342 from 27P_0402 to 33P_0402.
KAT10 from SI2-R to PV LA-5251P REV:0.6 -> 0.7 Modify <2009.10.13.~2009.11.4. >
Page
Change Cause
Modify Description
0.7
10/13
CKT,BOM,Layout
24
-Change one of the USB Bulk Cap from 150UF to 220UF. <Compal>.
--Change C406 from 150U_B2_6.3VM_R35M (P/N:SGA00002N80) to 220U_6.3V_M (P/N:SF000002Y00).
0.7
10/13
CKT,Layout
15,22
-Delete USB20_N6/P6 from WLAN slot. WiMAX is dead. <HP>.
--Delete USB20_N6/P6 between WLAN slot JP6.36/38 and PCH U7.M22/N22.
0.7
10/19
CKT,Layout
32
-Delete and modify Skew Hole PCB Footprint for M/E Drawing update. <Compal>.
--Delete H13 (H_3P0); change H2 from H_4P7 to H_4P4; H28 from H_4P9 to H_4P8.
0.7
10/19
CKT,BOM,Layout
15,22,31
0.7
10/21
CKT,Layout
15
-Simplify the CLK_PCI_DB and CLK_PCI_DEBUG design and routing for improve
EE signals quality and EMI Issue. <Compal>.
-Modify RP1 Pin1,2,3 connection for layout routing smoothly. <Compal>.
--Design change and del R270 to simplify that become CLK_PCI_DEBUG; Add R477 0 ohm to separate for JP6.19 option
CLK_PCI_DEBUG connection.
--Modify RP1 Pin1,2,3 connection for layout routing smoothly.
0.7
11/03
CKT,BOM,Layout
21
-M/E Design change the RJ-45 connector. <Compal>.
--M/E Design change JRJ45 DC234003O00(TYCO_2006067-1_13P) to DC020910201(FOX_JM36111-R2225-7H_13P-T).
0.7
11/03
CKT,BOM,Layout
24
--Del R697(0_0201); Add R11(470K_0402) and C7(0.01UF) close to U33 pin3 and pin4.
0.7
11/05
CKT,BOM,Layout
29
--Design in the isolate circuit on SATA_LED# by add Q79 (2N7002) and R49 (10K) PH close to Docking Connector JP30.39.
0.7
11/05
CKT,BOM
29
-Add the RC delay circuit between SLP_S4# and SLP_S4_R to fix dual USB
can not power on issue. <Compal>.
-Add the isolate circuit for Skagen side Monitor Stand HDD LED light on issue fix.
<Compal>.
-Schematic BOM change for actual and common. <Compal>.
0.7
10
11/06
CKT,BOM
30
-Schematic BOM change for CBB Reset function. <HP>.
--BOM change to install R605 (0_0201).
0.7
11
11/06
CKT,BOM,Layout
18
-Add +3VS PH on CRT_DDC_CLK &C RT_DDC_DATA for design change.. <MAXIM>.
--Add R53,R57(2.2K) +3VS pull-high on CRT_DDC_CLK &C RT_DDC_DATA for MAXIM CRT switch design change.
0.7
12
11/06
CKT,BOM,Layout
-Cancel REMOTE thermal sensor reserve. <HP/Compal>.
--Delete REMOTE2+/- traces & Q1. Move C5 close to pins 16/15 of U2.
0.7
13
11/11
CKT,BOM,Layout
14,28
-Add 0.1UF cap for EMI issue fix. <Compal>.
--Add C669 (0.1UF) close to R215; C668 (0.1UF) close to JP22.2.
--BOM change on Q30, Q19, U6.
0.7
14
11/11
CKT,BOM
20
-Install EMI INV_PWM reserve solution for issue fix. <Compal>.
--Install R372 (22_0402) and C665 (220P_0402).
0.7
15
11/11
CKT,BOM,Layout
28
-Add 0.1UF CAP on ON/OFF# for ESD issue fix. <Compal>.
--Add C670 (0.1UF_0402) close to JP20.2's via.
0.7
16
11/12
CKT,BOM,Layout
28
-Add 0 ohm resistor for CBB reset function pin ground to avoid floating. <SMsC/Compal>. --Add R60 (0_0402) close JP28 pin 3 for CBB reset function reserve.
0.7
17
11/12
CKT,BOM,Layout
38
-To resolve glitch seen on +0.75VS power rail during S0->G3 transition. <HP/Compal>.
--Add power jumper options for +1.5VS_CPU_VDDQ(PJP605) & +1.5V(PJP604) to PU601.1. Make PJP605 option installed.
0.7
18
11/12
CKT,Layout
29
-To resolve Docking Connector (JP30) SMT soldering issue. <HP/Compal>.
--Update the symbol and PCB Footprint FOX_QL1044L-D261A1-7H_82P-T for fix.
0.7
19
11/12
CKT,BOM
--
-Schematic BOM change for actual and common. <Compal>.
--BOM change on C68,C69,C70,C71,C72,C92,C93,C94,C113,C114,C115,C140, C63,C64,C65,C66,C67,C85,C86,C87,C88,C89,C90,C91; C29,

C60,C48,C62; C30;
--Change H2 from H_4P4 to H_4P7; H28 from H_4P8 to H_4P9.
0.7
20
11/13
CKT,BOM,Layout
32
-M/E Screw hole size modify. <Compal/HP>.
0.7
21
11/13
CKT,BOM
25
-To fix CBB auto active caused by +3VS leakage issue. <Compal>.
--Change Q28 from AP2301(SB000007H10) to AP2309(SB00000MI00).
0.7
22
11/13
CKT,BOM
13
-To follow INTEL Design Guide requirement. <INTEL>.
--Change C193,C194,C195,C196,C197,C198 from 0.1U_0402_16V4Z(SE070104Z80) to 0.1U_0402_25V4K(SE00000G880).
0.7
23
11/14
CKT,BOM,Layout
28,30
-Cancel CAP_RST related design reserve to avoid the ESD issuet. <HP/SMsC>.
--Del CAP_RST Net and also R60,R605, leave the KBC pin63 (GPIO35) alone as NC.
0.7
24
11/27
CKT,BOM
14,18
-BOM change for CRT EMI and EE SVTP fail issue. <HP/Compal>.
0.7
25
11/27
CKT,BOM
-To fix INTEL Leakage circuit sequence issue. <HP/Compal>.
--Remove R247,R248,R249 (150_0402); Install C232,C233,C234 (18P_0402); Remove C235,C236,C237 (18P_0402); Change L2,L4,L6
from 0805CS-111XJLC_0805 to 0_0603_5%; Change L1,L3,L5 from 0805CS-111XJLC_0805 to HLC0603CSCC33NJT_0603;
Remove R322,R323,R324 (150_0402_1%); Install C321,C320,C315 (75_0402_1%)
--Change C26,C27 from 10UF(SE093106M80) to 22UF(SE000000I10); also change the soldering pad from PJP604 to PJP605.
KAT10 from PV-R to Pre-MV LA-5251P REV:0.8 -> 0.9 Modify <2009.12.29.~2010.01.05. >
Page
Change Cause
0.9
01/04
CKT,BOM,Layout
30,31
Modify Description
-Need rotate the BIOS Socket for new type one implement without repair and SMT
interfere issue. <Compal>.
-To final Foxconn Docking Connector layout footprint. <Compal>.
--1. Cancel 16pin BIOS reserve (Del U36 and R696); 2. Cancel Board ID Detect reserve circuit (Del U8,Q37,R571,R572,R574,R575);
3. Rotate 8 pin BIOS Socket 90 degree.
--Update PCB Footprint (FOX_QL1044L-D261A1-7H_82P-T) from Compal Server --> No change and same as PV phase.
--Cancel H17 Screw Hole for M/E design change.
0.9
01/04
Layout
29
0.9
01/04
CKT,Layout
32
-Cancel H17 Screw Hole for M/E design change. <Compal>.
0.9
01/04
CKT,BOM,Layout
4,14,28
-Add Caps for ESD CBB issue fixed. <Compal>.
--Add C119 between JP4 pin 37 and 41; Add C120 close to R20.1; Add C145 close to R231 pin 1; Add C146 close to D34 pin 1.
0.9
01/04
CKT,BOM,Layout
14
-Reduce L1~L6 package size for fix repair and SMT issue. <Compal>.
0.9
01/05
CKT,BOM,Layout
33
-Add Cut Mode Caps for EMI PCI issue fix. <Compal>.
--1. Change L2,L4,L6 PCB Footprint from TAIYO_LB2012T100MR_L2012_2P to R_0603 for final.
2. Change L1,L3,L5 from TAIYO_LB2012T100MR_L2012_2P to KC_HLC0603CSCCR11JT_2P for final.
--Add 4 pcs 0.1UF Cut Mode Caps (C666,C667,C671) which located around the canceled Braidwood module. for EMI PCI issue fix.
Compal Secret Data
2006/02/13
Issued Date
2010/12/31
Deciphered Date
5
Title


Custom LA-5251P
Date:
R ev
0.9
Sheet
1
47
of
47

Compal Electronics Schematics Document

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Compal Electronics Schematics Document

Uploaded by

Copyright:

Available Formats

A

INTEL Auburndale BGA with IBEX core logic

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Tuesday, January 05, 2010

Display port panel

DDR3 1066/1333MHz 1.5V

USB conn*1(Left side)

FingerPrinter Validity VFS451

Intel Ibex Peak M

USB conn x 3(For I/O)-Rear side, Power USB

Rico R5C835 Controller

AMP & Audio Jack

Smart Card SD/MMC Slot

SATA ODD Connector

NAND Flash Card

1.8" SATA HDD Connector

SMSC KBC 1098

Power On/Off CKT.

Touch Pad CONN.

DC/DC Interface CKT.

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Tuesday, January 05, 2010

: means Digital Ground

: means Analog Ground

@ : means just reserve , no build

S5 S4/ Battery only

S5 S4/AC & Battery

Install below 45 level BOM structure for ver. 0.1

Install below 43 level BOM structure for ver. 0.1

SMBUS Control Table

Compal Secret Data

Compal Electronics, Inc.

Size Document Number

Tuesday, January 05, 2010

Layout rule 10mil width trace

07/09 update for INTEL S3 leakage issue.

2 SYS_AGENT_P WROK AM7

ESD request to add

0112 Remove uninstall parts

Layout Note:Please these

11/06 Cancel REMOTE thermal sensor reserve.

Thermal Sensor EMC2113 with CPU PWM FAN

Add C119 between JP4 pin 37 and 41;

DDR3 Compensation Signals

01/04 update for ESD

CPU XDP Connector

0112 Add test points

07/08 update for INTEL S3 leakage issue.

to power; PU to VCCP at power side also

JTAG & MBP

EMC2113-1-AP-TR QFN 16P

0ohm and 0.1u

Compal Secret Data

Compal Electronics, Inc.

Size D ocument Number

Tuesday, January 05, 2010

PCI EXPRESS -- GRAPHICS

04/20 INTEL #418125 update

CFG Straps for PROCESSOR