SUPPLY SWITHCING WITH GROUND COLLAPSE TECHNIQUE FOR

LOW POWER REGISTER FILE

THIPPESWAMY K H
Asst Prof., ECE Dept, Don Bosco Institute of Technology., Banglore-74
thippeswamykh@gmail.com

SHRINIVAS P GUDI
Asst Prof., ECE Dept, Don Bosco Institute of Technology , Banglore-34
shrinivasgudi@gmail.com

ABSTRACT: Power-gating has been widely used to reduce subthreshold leakage current in
CMOS circuits [1]. However, the extent of leakage saving through power-gating diminishes with
technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-
gating involves substantial increase of total area and wire length of the circuit [2]. A circuit
technique called supply switching with ground collapse (SSGC) has recently been proposed to
overcome the limitation of power-gating. Compared to a register file implemented in conventional
power- gating, leakage current is cut by a factor of 2.2 and it also overcome the area overhead due
to the data-retention circuit elements in the CMOS circuit implemented with the SSGC technique
and demonstrating that SSGC can be a substitute for power-gating in nanometer CMOS[1][3].

KEYWORDS: complementary metal oxide semiconductor (CMOS), supply switching with

ground collapse (SSGC).

INTRODUCTION

A register file is an array of processor registers in a central processing unit (CPU). Modern
integrated circuit-based register files are usually implemented by way of fast static RAMs with
multiple ports. Such RAMs are distinguished by having dedicated read and write ports [4],
whereas ordinary multiported SRAMs will usually read and write through the same.

The instruction set architecture of a CPU will almost always define a set of registers which are
used to storage data between memory and the functional units on the chip. In simpler CPUs,
these
architectural registers correspond one-for-one to the entries in a physical register file within the
CPU. More complicated CPUs use register renaming, so that the mapping of which physical entry
stores a particular architectural register changes dynamically during execution. The register file is
part of the architecture and visible to the programmer, as opposed to the concept of transparent
caches.

The fig (1) shows the Power-gated register file which is used to reduce sub-threshold leakage
current in register files. However, the extent of leakage saving through power-gating diminishes
with technology scaling due to gate leakage of data- retention circuit elements. Furthermore,
power-gating involves substantial increase of area and wirelength because of the data-retention
storage element, output isolation circuits and current switches.
 Fig (1). Power Gated Register File Circuit

Fig (2): SSGC Register File Circuit

A register file circuit with the supply switching with ground collapse (SSGC) is shown in fig (2),
which is proposed to overcome the limitation of power-gating [4][6]. The circuit technique can be
applied to the register file used typically in a microprocessor. A thorough analysis of power,
speed and area will be done between this register file circuit and the traditional register file and
power gated register file.

EXISTING METHOD

This chapter presents some of the recent works on low leakage register file design and supply
switching techniques published in the literature. This chapter enables us to understand how to
implement a ultra low leakage register file using supply switching with ground collapse technique.

i) "Supply switching with ground collapse: Simultaneous control of Subthreshold and gate
leakage current in nanometer-scale CMOS circuits," in June and July 2007 by H. Kim et al. This
paper gives an overview that although the power gating has been widely used to reduce

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subthreshold leakage, but its efficiency degrades very fast with technology scaling, limiting its
application to nanometer-scale technologies, such as 65 and 45 nm. And it also demonstrated by
simulations that this is due to the gate leakage of circuits specific to power gating, such as state-
retention storage elements and output-holding circuits. And also recommends in order to
overcome this limitation of power gating, a new circuit technique called supply switching with
ground collapse. It also gives the experimental results to compare the leakage with SSGC and with
power gating. SSGC outperforms power gating by a factor of 5 to 7 at 65 nm and 6 to 11 at 45 nm
ii) "A Low-Power Register File with Dual-Vt Dynamic Bit-Lines driven by CMOS
Bootstrapped Circuit" SEP, 2009 by Hyoung-Wook Lee et al., gave the overview of the register file
design with two different threshold voltages transistors to overcome the Subthreshold leakage
when the circuit is in sleep mode.

iii) "New MTCMOS flip-flops with simple control circuitry and low leakage data retention
capability," in Proc. Int. Conf. Electron., Circuits, Syst., Dec. 2007, by Z. Liu and V. Kursun
gives an idea how multi threshold transistors can be used in the CMOS circuits in order to reduce
the leakage.
The detail study of the few more research papers such as: "Semicustom design
methodology of power
gated circuits for low leakage applications," and few more papers on the SSGC techniques gives
the knowledge about the power leakage due to the Subthreshold leakage current in conventional
un- power gated circuit and which can be overcome by using power gated circuit but overcome it
by including the overhead of 17% in area and 18 % of wirelength due to the output isolation circuit
and data retention elements in which the designed flipflop can reduce leakage current by a factor
of 300 and 50 when its state is low and high respectively, at the cost of an area increase of 68%
compare to flipflop used in un-power gated circuit.

"A 1-V power supply high-speed digital circuit technology with multithreshold-voltage
CMOS," in Aug. 1995 by S. Mutoh et al., and "A Low-Power Register File with Dual-Vt Dynamic
Bit- Lines driven by CMOS Bootstrapped Circuit" by Hyoung-Wook Lee et al., gives the idea of
how to use the different threshold voltage in row and column circuitry during active and standby
mode in order to reduce the power leakage without altering the performance of the circuit.

"A 65-nm mobile multimedia applications processor with an adaptive power management
scheme to compensate for variations," in June 2007 by H. Mair, A.Wang et al., and "New
MTCMOS flip- flops with simple control circuitry and low leakage data retention capability," in
Proc. Int. Conf. Electron., Circuits, Syst, by Z. Liu and V. Kursun gives idea to design of data
retention flipflop to reduce the power leakage.

STATEMENT OF THE PROBLEM AND REQUIREMENTS

This chapter gives an overview of what this work is comprised of and the objective and the design
tool that required during the course of the work.

Statement of problem
The power leakage is becoming a critical factor in CMOS circuits and it is becoming more
critical with the technology scaling, which must be reduced to obtain good performance in the
Scaled CMOS circuits. Power-gating can be used to reduce sub-threshold leakage current in

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register file which is the one of the important combinational CMOS circuit used in the processors
CPU's to store data, the extent of leakage saving through power-gating diminishes with technology
scaling due to gate leakage of data- retention circuit elements. Furthermore, power-gating involves
substantial increase of area and wirelength also because of the data-retention storage element,
output isolation circuits and current switches. Therefore we need circuit technique to overcome
the limitation of power-gating and which will reduce both Subthreshold leakage and gate leakage
without area overhead.

Fig (3): SSGC Circuit When standby=0

Objective
The objective of this paper is to design register file using supply switching with ground collapse
technique which will provide reduction in leakage current as compare to the register files with
conventional power gating technique, which will also use lesser circuit area and wirelength as
compare to register file with power technique which use data- retention storage elements. And to
simulate and analysis the designed register files for area, critical path and power in comparison in
to register files designed with conventional power gating technique

Tools Requirement
The design of the register file is done using Cadence Virtuoso Layout of all column, row
circuitry and control circuitry will be done using Cadence Virtuoso Critical path analysis
simulations will be run using Synopsys Hspice.

SUPPLY SWITCHING WITH GROUND COLLAPSE TECHNIQUE

This is one novel technique used to overcome the limitation of the power-gating technique.
The implementation of this technique is explained along with figure (3) and (4) as shown. When
the circuit is in active mode (stand by=0), Vdd is supplied through a pMOS switch M1 (M2 being
turned off) and an nMOS switch footer is turned on as shown in the Fig(3). The amount of
voltage drop that can be tolerated by the circuit determines the size of M1 and footer, i.e., larger
size of M1 and footer if smaller voltage drop is allowed. High-Vt is used for both switches to
reduce their Subthreshold leakage in standby mode when they are turned off. Low-Vt(or regular-Vt
or multiple-Vt) is used for implementing the circuit itself for high performance.

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When the circuit is in active mode (stand by=0), Vdd is supplied through a pMOS switch M1
(M2 being turned off) and an nMOS switch footer is turned on as shown in the Fig(3). The mount
of voltage drop that can be tolerated by the circuit determines the size of M1 and footer, i.e.,
larger size of M1 and footer if smaller voltage drop is allowed. High-Vt is used for both switches
to reduce their Subthreshold leakage in standby mode when they are turned off. Low-Vt(or
regular-Vt or multiple-Vt) is used for implementing the circuit itself for high performance.

Fig (4): SSGC Circuit When standby=1.

When the circuit goes to standby mode (Stand by=1), an nMOS switch M2 is turned on
(whileM1and footer are turned off) and standby voltage Vsv is supplied to the circuit. The
voltage Vsv is considerably lower than Vdd thereby suppressing gate leakage as well as
Subthreshold leakage of flip-flops, but still high enough to guarantee the data of the flip-flops to
be preserved since they are directly connected to Vss (part of it is connected to Vssv ) as opposed
to VSV in power-gating
shown in Fig (1).
DESIGN, SIMULATION AND ANALYSIS
Analysis of Reister file circuit is done in following steps.

DESIGN OF REGISTER FILE with SSGC Technique.

In the design of the ultralow leakage register file ,the register file consists of the 30 registers each
of 32 bit and which are multiported registers with 3 read ports and 2 write ports ie., 3R2W register
file bit cell is used as basic component for the register file implementation . The complete register
file with SSGC header and footer arrangement is shown in the below fig(5). The 3R2W bit cell is
similar to ordinary SRAM bit cell, which consist of two back to back connected inverters but with
1 more pair access transistors to write into bit cell and to overcome the read disturbance of
SRAM, the register file read operation is done with separate read ports.

The design of the Register file is done in Cadence virtuoso. Layout of all column, row circuitry and
control circuitry is also done using Cadence Virtuoso

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 Fig (5): Header and Footer Switches For Register File.

SIMULATION

The designed SSGC register file is simulated in comparison to power-gated register file to measure
the leakage reduction and the improvement in the performance for the novel technique. The
Critical path analysis simulations are run using Synopsys Hspice tool.

In the simulation the during the standby=0 the time for WL to DOUT ie., writing data into
register file cell is calculated and in the standby mode the leakage current measurement is done to
analyze the improvement in performance of the designed CMOS circuit.

ANALYSIS

From the simulation results the analysis is made to calculate the improvement in performance and
reduction in leakage of the register file designed with the SSGC method which shows that the
leakage current is cut by a factor of greater than 2 as compare to the same register file designed
with the power-gating method. And it also require lesser wire length and no area overhead due to
data retention flipflops as in power-gated circuit. But only requirement is simple modification in
the layout of the of ordinary flipflops

There are two factors that contribute to leakage saving of SSGC: switching to lower supply
voltage VSV and power gating through footer. The amount of contribution from each factor
depends on Vsv

CONCLUSION

Supply switching with ground collapse is a novel technique has been proposed as a substitute for
power-gating in nanometer CMOS technology. The novel circuit technique will provide the less
leakage current by a factor of about greater than 2 compared to the same register file implemented
in conventional power-gating. This will achieve with smaller area and shorter wire length.

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REFERENCES

H. Kim and Y. Shin, "Semicustom design methodology of power gated circuits for low leakage
applications," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 54, no. 6, pp. 512-516, Jun. 2007.
Y. Shin, S. Heo, H. Kim, and J. Choi, "Supply switching with ground collapse: Simultaneous control
of subthreshold and gate leakage current in nanometer-scale CMOS circuits," IEEE Trans. Very
Large Scale Integr. (VLSI) Syst., vol. 15, no. 7, pp. 758-766, Jul. 2007.
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "A 1-V power supply
high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State
Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
Hyoung-Wook Lee, Hyunjoong Lee, Jong-Kwan Woo, Woo-Yeol Shin, and Suhwan Kim, "A Low-
Power Register File with Dual-Vt Dynamic Bit-Lines driven by CMOS Bootstrapped Circuit" in
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.3,
SEPTEMBER, 2009.
H. Mair, A.Wang, G. Gammie, D. Scott, P. Royannez, S. Gururajarao, M. Chau, R. agerquist,
L. Ho, M. Basude, N. Culp, A. Sadate, D. Wilson, F. Dahan, J. Song, B. Carlson, and U. Ko, "A 65-
nm mobile multimedia applications processor with an adaptive power management scheme to
compensate
for variations," in Proc. Symp. VLSI Circuits, Jun. 2007, pp. 224-225.
Z. Liu and V. Kursun, "New MTCMOS flip-flops with simple control circuitry and low leakage data
retention capability," in Proc. Int. Conf. Electron., Circuits, Syst., Dec. 2007, pp. 1276-1279.

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