TM TT BI GING VERILOG 1.

Khong trng
Khong trng ngn nhng t v c th cha khong cch, khong
CHNG I - TNG QUAN di, dng mi v dng ng dn. Do , mt lnh c th a ra nhiu
dng phc tp hn m khng c nhng c tnh c bit.
I. Gii thiu
Verilog HDL l mt trong hai ngn ng m phng phn cng thng 2. Ch gii
dng nht, c dng trong thit k IC, ngn ng kia l VHDL. HDL cho Nhng ch gii c th ch nh bng hai cch: (ging trong C/C++).
php m phng cc thit k d dng, sa cha li, hoc thc nghim bng Ch gii c vit sau hai du gch xin (//). c vit trn cng
nhng cu trc khc nhau. Cc thit k c m t trong HDL l nhng k mt dng.
thut c lp, d thit k, d tho g, v thng d c hn dng biu , c vit gia /* */, khi vit nhiu dng ch gii.
c bit l cc mch in ln.
Verilog thng c dng m t thit k bn dng: 3. Ch s
Thut ton (mt s lnh ging ngn ng C nh: if, case, for,while). Lu tr s c nh ngha nh l mt con s ca cc bit, gi tr c
Chuyn i thanh ghi (kt ni bng cc biu thc Boolean). th l: s nh phn, bt phn, thp phn, hoc thp lc phn.
Cc cng kt ni( cng: OR, AND, NOT). V d: 3b001, 5d30 = 5b11110,
Chuyn mch (BJT, MOSFET) 16h5ED4 = 16d24276 = 16b0101111011010100
Ngn ng ny cng ch r cch thc kt ni, iu khin vo/ra trong m
phng. 4. T nh danh
Cu trc chng trnh dng ngn ng Verilog T nh danh do ngi dng quy nh cho bin s, tn hm, tn
mun, tn khi v tn trng hp. T nh danh bt u bng mt mu t
// Khai bo module hoc ng gch di _ ( khng bt u bng mt con s hoc $ ) v k
Module tn chng trnh (tn bin I/O); // tn chng trnh c mi ch s ca mu t, nhng con s v ng gch di, t nh danh
trng tn file.v. trong Verilog phn bit dng ch.
Input [msb:lsb] bin;
5. C php
Output [msb:lsb] bin;
K hiu cho php:
Reg [msb:lsb] bin reg; ABDCEabcdef1234567890_$
Wire [msb: lsb] bin wire; Khng cho php: cc k hiu khc -, &, #, @
// Khai bo khi always, hoc khi initial. 6. Ton t
cc lnh
Ton t l mt, hai, hoc ba k t dng thc hin cc ton hng trn bin.
Endmodule Cc ton t bao gm >, +, &, !=.
7. T khaVerilog
C nhiu t m c ngha c bit trong Verilog. V d: assign,
.II. ngha cc thut ng trong VERILOG case, while, wire, reg, and, or, nand, v module. Chng khng c dng
Cc tp tin vn bn ngun Verilog bao gm nhng biu hin thuc
nh t nh danh. T kha Verilog cng bao gm c ch dn chng trnh
tnh t vng sau y:
bin dch v System Task (h thng son tho) v cc hm.
 Chng II - CC DNG D LIU nhiu bit, data c lu tr bng cc ch s khng du v khng c k hiu
I. t gi tr ui m rng, c thc hin m ngi s dng c ch yu l s b hai.
Verilog bao gm 4 gi tr c bn. Hu ht cc dng d liu Verilog 1. C php:
cha cc gi tr sau: Reg [msb:lsb] tn bin reg.
0: mc logic 0, hoc iu kin sai. 2. V d:
1: mc logic 1, hoc iu kin ng. Reg a; // bin thanh ghi n gin 1 bit.
X: mc logic tu nh Reg [7:0] A; // mt vect 8 bit; mt bank ca 8 thanh ghi.
Z: trng thi tng tr cao. Reg [5:0]b, c; // hai bin thanh ghi 6 bit.
X v Z dng c gii hn trong tng hp (synthesis) IV. Input, Output, Inout
II. Wire Nhng t kho ny biu th u vo, u ra, v port hai chiu ca
M t vt liu ng dy dn trong mt mch in v c dng mt module hoc task. Mt port u ra c th c cu h?nh t cc dng:
kt ni cc cng hay cc module. Gi tr ca Wire c th c, nhng khng wire, reg, wand, wor, hoc tri. Mc nh l wire.
c gn trong hm (function) hoc khi (block). Wire khng lu tr gi tr 1. C php:
ca n nhng va?n phi c thc thi bi 1 lnh gn k tip hay bi s kt Input [msb:lsb] port u vo.
ni Wire vi u ra ca 1 cng hoc 1 module. Nhng dng c bit khc Output [msb:lsb] port u ra.
ca Wire: Inout [msb:lsb] port u vo,ra hai chiu.
Wand(wired_and): gi tr ph thuc vo mc logic And ton b b iu 2. V d:
khin kt ni n Wire. Module sample (b, e, c, a);
Wor (wired_or): gi tr ph thuc vo mc logic Or ton b b iu Input a; // mt u vo mc nh l kiu wire.
khin kt ni n Wire. Output b, e; // hai u ra mc nh l kiu wire.
Tri(three_state): tt c b iu khin kt ni n 1 tri phi trng Output [1:0] c; /* u ra hai bit, phi c khai botrong mt lnh
thi tng tr cao. ring*/
1. C php Reg [1:0] c; // u c c khai bo nh mt reg.
Wire [msb:lsb] tn bin wire. V. Integer (S nguyn)
Wand [msb:lsb] tn bin wand. Integer l mt bin a nng. Trong tng hp chng c dng ch
Wor [msb:lsb] tn bin wor. yu cho vng lp, tham s, v hng s. Chng hon ton l reg. Tuy nhiu
Tri [msb:lsb] tn bin tri. chng cha d liu bng nhng s c du, trong khi khai bo dng reg
2. V d cha chung bng s khng du. Nu chng cha nhng s m khng nh
Wire c; ngha thi gian bin dch th kch thc mc nh l 32 bit. Nu chng cha
Wand d; hng, s tng hp iu chnh cc s c kch thc nh nht cn thit cho s
Assign d= a; bin dch.
Assign d= b;// gi tr d l mc logic ca php And a v b. 1. C php:
Wire [9:0] A; // vect A c 10 wire. Integer tn bin nguyn;
III. Reg tn hng nguyn;
Reg (register) l i tng d liu m n cha c gi tr t mt th 2. V d:
tc gn k tip. Reg ch c dng trong hm v khi th tc. Reg l mt Integer a; // s nguyn n gin 32bit.
loi bin Verilog v khng nht thit l thanh ghi t nhin. Trong thanh ghi Assign b= 63; // mc nh l mt bin 7 bit.
VI. Supply 0, Supply1 Chng III - CC CNG C BN TRONG VERILOG
Xc nh ch ng dn ln mc logic 0 ( t), logic 1( ngun) theo Cc cng logic c s l mt b phn ca ngn ng Verilog. C hai
th t nh sn. c tnh c ch r l: drive_strenght v delay.
VII. Time Drive_strenght ch sc bn ca cng. bn u ra l s kt ni mt
Time l mt lng 64 bit m c s dng cng vi $time, h thng chiu n ngun, k to nn s kt ni trong sut trans dn, kt thc l
thao tc cha lng thi gian m phng. Time khng c h tr tng hp tng tr ko ln hoc xung. Drive_strenght thng khng c ch r,
v v th ch c dng trong mc ch m phng. trong trng hp ny bn mc nh l strong1 v strong0 .
1. C php: Delay: nu delay khng c ch r, th khi cng khng c tr hon
Time bin time; truyn ti; nu c hai delay c ch nh, th trc tin l miu t tr hon
2. V d: ln, th hai l tr hon xung. Nu ch c mt delay c ch nh, th khi
Time c; tr hon ln xung l nh nhau. Delay c b qua trong tng hp.
c = $time; // c = thi gian m phng dng in. Phng php ca s tr hon ch nh ny l mt trng hp c bit ca
VIII. Parameter (Tham s) Parameterized Modules. Cc tham s cho cc cng c s phi c nh
Mt Parameter xc nh 1 hng s m c t khi bn cho v d c ngha trc nh delay.
th l mt module. Cc ny cho php ta c th sa cha. I. Cc cng c bn
1. C php: Cc cng c bn c mt u ra, v c mt hoc nhiu u vo.
Parameter par_1= gi tr, par_2= gi tr, ; Trong cc cng, c php c th biu din bn di, cc t kho ca cc
Parameter [gii hn] par_3 = gi tr?; cng: and, or, nand, nor.
2. V d: 1. C php
Parameter add = 2b00, sub = 3b111; GATE (drive_strength)#(delays)
Parameter n = 4; Tn t kha cng _tn (output, input_1, input_2, , input_N);
Parameter [3:0] par_2 = 4b1010; Delay: #( ln, xung) hoc #ln_v_xung hoc #( ln_v_xung)
2. V d
reg [n-1:0] harry; /* mt thanh ghi 4 bt m rng c t bi And c1 (o, a, b, c. d); // c 4 u vo cng And gi l c1
tham s n trn */. c2 (p, f, g); // v 2 u vo cng and gi l c2
Or #(4,3) ig ( o, b, c); // cng Or c gi l ig, rise time = 4, fall time = 3
always @(x) Xor #(5) xor1 (a, b, c); // sau 5 n v thi gian th a = b xor c
y = {{(add - sub) {x}}} II. Cng buf, not
if (x) begin Cc cng ny thc thi m v o theo theo th t nh sn. Chng
state = par_2[1]; c mt u vo, hai hay nhiu u ra. C php c th biu din xem bn
else di; t kho buf, not.
state =par_2[2]; 1. C php
end. Tn t kha cng _tn (output_1, output_2, , output_N, input);
2. V d
Not #(5) not_1( a,c); // sau 5 n v thi gian th a = o c
Buf c1 (o, p, q, r, in); // b m 5 u ra v 2 u ra
c2 (p, f, g);
 ChngV- TON T Assign c = a & b;
Endmodule
I. Ton t s hc
IV. Ton t logic
Nhng ton t ny thc hin cc php tnh s hc. Du + v - c th
c s dng mt trong hai ton t n (-z) hoc kp (x - y). Ton t logic tr v 1 bit n 0 hoc 1. chng ging nh ton t
1. Ton t: bitwire ch l nhng ton hng n bit. Chng c th lm vic trn biu
+, -, *, /, %. thc, s nguyn hoc nhm bit, v coi nhu tt c cc gi tr khng bng 0 l
2. V d: 1. Ton t logic c dng nhiu trong lnh iu kin (if else), khi
parameter n = 4; chng lm vic trn biu thc.
Reg[3:0] a, c, f, g, count;
f= a +c; 1. Ton t:
g= c n; !(NOT), && (AND), || (OR)
count = (count +1) % 16; // c th m t 0 n 15. 2. V d:
Wire [7:0] x, y, z;
II. Ton t quan h Reg a;
Ton t quan h so snh hai ton hng v tr v mt n bit l 0
hoc 1. Nhng ton t ny tng hp vo dng c so snh. Bin Wire v Reg if ((x= = y)&&(z)) a=1;
l nhng bin dng. V th, (-3b001) = (3b111) v (-3b001) > ( 3b110) else a=! x;
nhng nu l s nguyn th -1< 6. V. Ton t bin i
1. Cc ton t quan h:
<, <=, >, >=, = =, !=. C tc dng trn tt c cc bit ca mt vect ton hng v tr v gi
2. V d: tr n bit. Nhng ton t ny l h?nh thc t i s ca cc ton t bitwire
If (x= =y) e =1; trn.
Else e= 0; 1. Cc ton t:
// so snh hai vector a, b ~ (bin i NOT), & (bin i AND), ~&( bin i NAND), | (bin i
reg [3:0] a, b; OR), ~| (bin i NOR), ^ (bin i XOR), ~^ hoc ^~ (bin i XNOR).
if (a[3] = =b [3]) a[2:0] >b[2:0]; 2. V d:
else b[3]; Module chk_zero (a,z);
Input [2:0] a;
III. Ton t bit_wire Output z;
So snh tng bit hai ton ton hng. Assign z = ~| a;
1. Cc ton t: Endmodule
~ (bitwire NOT), & (bitwire AND), | (bitwire OR), ^ (bitwire XOR), ~^ VI. Ton t ghp
hoc, ^~ (bitwire XNOR).
2. V d: Dch ton t u bng ch s ca cc bit c nh ngha bi ton
Module and2(a, b, c); t th hai. V tr cn trng s c in vo vi nhng s 0 cho c hai
Input [1:0] a, b; trng hp dch tri hoc phi.
Output [1:0] c;
1. Ton t Ton t Tn
<< ( dch tri), >> (dch phi). [] Chn bit, chn phn
2. V d: () Phn trong ngoc n
assign c = a<<2; c = a dch tri 2 bit cc ch trng c in vi !, ~ Mc logic v bit_wire NOT
nhng s 0. &, |, ~&, ~|, ^, Bin i: AND, OR, NAND, NOT, XOR,
~^ XNOR.
VII. Ton t dch +, - Du ch s m s dng.
{} Ghp ni { 3b101,3b110} = 6b101110
Ghp hai hoc nhiu ton hng thnh mt vect ln. {{ }} Th bn {3{3b101 }}=9b101101101
1. Ton t:
*, /, % Nhn, chia, phn trm.
{} (concatenation)
+, - Cng tr nh phn.
2. V d:
<<, >> Dch tri, phi.
Wire [1:0] a, b;
<, <=, >, >= Du so snh. Bin Reg v wire c ly bng
Wire [2:0] x;
nhng s dng.
Wire [3:0] y, Z;
Assign x = {1b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0]. = =, != Bng v khng bng trong ton t logic.
Assign y = {a, b}; // y[3]= a[1], y[2] = a[0], y[1] = b[1], y[0] = b[0]. & Bit_wire AND, and tt c cc bit vi nhau.
^, ~^ Bit_wire XOR, Bit_wire XNOR.
VIII. Ton t th bn | Bit_wire OR.
To ra nhiu bn sao ca mt mc chn. &&, || Ton t logic AND, OR.
1. Ton t: ?: x = ( iu kin ) T:F
{n{ mc chn }} n nhm th bn trong mt mc chn.
2. V d:
Wire [1:0] a, b;
Wire [3:0] x;
Assign x = {2{1b0},a}; // x= {0, 0, a}.
IX. Ton t iu kin
Ging nh C/C++. Chng nh gi mt trong hai biu thc c bn
trong mt iu kin. N s tng hp thnh b a cng (MUX).
1. Ton t :
(iu kin)? kt qu khi iu kin ng : kt qu khi iu kin sai.
2. V d:
assign a = (g) ? x : y;
Assign a = ( inc = =2) ? a+1: a-1;
X. Th t ton t
Nhng ton t trong mc ging nhau nh gi t tri sang phi
 Chng VI- TON HNG nh l mt trong nhng ton hng. Chiu rng bt ca gi tr tr v chc
chn c bit trc.
1. C php:
I. Literals (dng k t) Tn hm(danh sch bin).
L ton hng c gi tr khng i m c dng trong biu thc 2. V d:
Verilog. C hai dng k t l: Assign a = b & c & chk_bc(b, c);
Chui: l mt mng c nhiu k t c t trong du . Function chk_bc;
Ch s: l nhng s khng i, nh phn, bt phn, thp phn, hoc s hex. Input c, b;
1. C php cc ch s: Chk_bc = b^ c;
nF dddd Endfunction
Trong : IV. Wire, reg, v tham s
n : s nguyn miu t s bit.
Wire, reg, v tham s c th c dng nh l cc ton hng trong
F: mt trong bn nh dng sau: b( s nh phn), o( s bt phn), d(
biu thc Verilog.
s thp phn), h( s hex).
2. V d:
time is // chui k t.
267 // mc nh 32 bit s thp phn.
2b01 // 2 bit nh phn.
20h B36E // 20 bit s hex.
o62 // 32 bit bt phn.
II. Chn 1 phn t bit v chn 1 phn cc bit
y l s la chn mt bt n hoc mt nhm bit theo th t, t mt wire,
reg hoc t tham s t trong ngoc [ ]. Chn 1 phn t bit v chn 1 phn
cc bit c th c dng nh l cc ton hng trong biu thc bng nhiu
cch thc ging nhau m cc i tng d liu gc c dng.
1. C php:
Tn bin [ th t bit].
Tn bin [ msb: lsb].
2. V d:
Reg [7:0] a, b;
Reg [3:0] ls;
c = a[7] & b[7];
ls = a[7:4] + b[3:0];
III. Gi hm chc nng
Gi tr tr v ca mt hm c th c dng trc tip trong biu
thc m khng cn gn trc cho bin reg hoc wire. Gi hm chc nng
 Chng VII - MODULES 2. V d:
I. Khai bo modules: Wire [ 1:0 ] a = 2b 01;
Mt module l bn thit k ch yu tn ti trong Verilog. Dng u Assign b = c &d;
tin ca khai bo module ch r danh sch tn v port (cc i s). Cc Assign d = x | y;
dng k tip ch r dng I/O (input/output, hoc inout) v chiu rng ca III. Module instantiations:
mi port. Mc nh rng port l 1 bit. Sau , cc bin port phi c Cc khai bo module phi theo mu t cc i tng thc t
khai bo wire, wand, , reg (mc nh l wire). Cc u vo l dng wire (instantiation). Cc module n bn trong cc module khc, v mi dn
khi d liu c cht bn ngoi module. Cc u ra l dng reg nu cc chng to mt i tng c nht t khun mu. Ngoi tr l module
t/hiu ca chng c cha trong khi always hoc initial. mc trn l nhng dn chng t chnh chng.
1. C php: Cc port ca module v d phi tha nhng nh ngha trong khun
Module tn module (danh sch port); mu. y l mt l thuyt: bng tn, s dng du chm(.) .tn port khun
Input [msb:lsb] danh sch port u vo; mu (tn ca wire kt ni n port). Bng v tr, t nhng port nhng
Output [msb:lsb] danh sch port u ra; v tr ging nhau trong danh sch port ca c khun mu ln instance.
Inout [ msb:lsb ] danh sch port vo_ ra; 1. C php:
cc lnh Tn instance1 (danh sch kt ni port );
endmodule Tn instance2(danh sch kt ni port);
2. V d:
Module add_sub(add, in1, in2, out); 2. V d:
Wire, reg, v tham s: // nh ngha module
Input[7:0 ] in1, in2; module and4(a,b,c);
Wire in1, in2; input [3:0]a,b;
Output [7:0] out; output [3:0]c;
Reg out; assign c = a&b;
cc lnh khc endmodule
Endmodule // module instantiations
II. Ch nh lin tip: wire [3:0] in1, in2;
Cc ch nh lin tip c dng gn mt gi tr ln trn mt wire wire [3:0] o1, o2;
trong mt module; bn ngoi khi always hoc khi initial. Cc ch nh // t v tr
lin tip c thc hin vi mt lnh gn (assign) r rng hoc bng s ch and4 C1(in1, in2,o1);
nh mt gi tr n mt wire trong lc khai bo. Lu , cc lnh ch nh // tn
lin tip th tn ti v c chy lin tc trong sut qu trnh m phng. and4 C2(.c(o2), .a(in1), .b(in2));
Th t cc lnh gn khng quan trng. Mi thayi bn phi ca bt c u vo s
lp tc thayi bn tri ca ccu ra.

1. C php:
Wire bin wire = gi tr?;
Assign bin wire = biu thc;
 Chng VIII - KHUN MU HNH VI (BEHAVIORAL) Ch nh khi (=) thc hin lin tc trong th t lnh c vit.
Ch nh th hai khng c thc thi nu nh ch nh u cho hon thnh.
Verilog c 4 mc khun mu:
1. C php:
Chuyn mch. (Khng xt gio trnh ny). Bin = biu thc;
Cng. Bin = #t biu thc;
Mc trn d liu. #t bin = biu thc;
Hnh vi hoc th tc c cp bn di. 2. V d:
Cc lnh th tc Verilog c dng to mt mu thit k mc cao Initial
hn. Chng ch ra nhng cch thc mnh ca vc lm ra nhng thit k Begin
phc tp. Tuy nhin, nhng thay i nh n phng php m ha c th gy a = 1; b = 2; c = 3;
ra bin i ln trong phn cng. Cc lnh th tc ch c th c dng #5 a = b + c; // sau 5 n v thi gian thc hin a = b + c = 5.
trong nhng th tc. d = a; // d = a = 5.
I. Nhng ch nh theo th tc Always @(posedge clk)
L nhng ch nh dng trong phm vi th tc Verilog (khi always v Begin
initial). Ch bin reg v integers (v chn n bit/ nhm bit ca chng, v Z = Y; Y = X; // thanh ghi dch.
kt ni thng tin) c th c t bn tri du = trong th tc. Bn phi y = x; z = y; // flip flop song song.
ca ch nh l mt biu thc m c th dng bt c dng ton t no. IV. Begin end
II. Delay trong ch nh Lnh khi begin end c dng nhm mt vi lnh m mt
Trong ch nh tr t l khong thi gian tri qua trc khi mt lnh c lnh c php c cho php. Bao gm function, khi always v khi initial.
thc thi v bn tri lnh gn c to ra. Vi nhiu ch nh tr (intra- Nhng khi ny c th c ty gi tn. V bao gm khai bo reg,
assignment delay), bn phi c nh gi tr trc tip nhng c mt delay integer, tham s.
ca t trc khi kt qu c t bn tri lnh gn. Nu thm mt qu trnh 1. C php:
thay i na cnh bn phi tn hiu trong khong thi gian t, th khng Begin: tn khi
cho kt qu u ra. Delay khng c h tr bi cc cng c. Reg[msb:lsb] danh sch bin reg;
1. C php ch nh th tc: Integer [msb:lsb] danh sch integer;
Bin = biu thc; Parameter [msb:lsb] danh sch tham s;
Ch nh tr: cc lnh
#t bin = biu thc; End
intra_assignment delay: 2. V d:
bin = #t biu thc. function trivial_one;// tn khi l: trivial_one
2. V d: input a;
Reg [6:0] sum; reg h, zilch; begin: adder_blk
Sum[7] = b[7]^c[7]; // thc thi tc thi; integer i;
Ziltch = #15 ckz & h; // ckz & h nh gi tr tc thi; lnh
//ziltch thay i sau 15 n v thi gian. end
#10 hat = b & c; /* 10 n v thi gian sau khi ziltch thay i, V. Vng lp for
b & c c nh gi v hat thay i*/ Ging nh c/c++ c dng thc hin nhiu ln mt lnh hoc khi lnh.
III. Ch nh khi Nu trong vng lp ch cha mt lnh th khi begin end c th b qua.
1. C php: Begin
For (bin m = gi tr 1; bin m </ <=/ >/ >= gi tr 2; cc lnh
bin m = bin m +/- gi tr?) end
begin VIII. Case
lnh Lnh case cho php la chn trng hp. Cc lng trong khi default thc
end thi khi khng c trng hp la chn so snh ging nhau. Nu khng c s
2. V d: so snh, bao gm c default, l ng, s tng hp s to ra cht khng
For (j = 0; j<=7; j = j+1) mong mun.
Begin 1. C php:
c[j] = a[j] & b[j]; Case (biu thc)
d[j] = a[j] | b[j]; Case 1:
end Begin
VI. Vng lp while cc lnh
Vng lp while thc hin nhiu ln mt lnh hoc khi lnh cho n khi end
biu thc trong lnh while nh gi l sai. Case 2:
1. C php: Begin
While (biu thc) cc lnh
Begin end
cc lnh Case 3:
end Begin
2. V d: cc lnh
While (!overflow) end
@(posedge clk);
a = a +1; default:
end begin
VII. Khi lnh if else if else cc lnh
Thc hin mt lnh hoc mt khi lnh ph thuc vo kt qu ca end
biu thc theo sau mnh if. endcase
C php 2. V d:
If (biu thc) Case (alu_clk)
Begin 2b00: aluout = a + b;
cc lnh 2b01: aluout = a - b;
end 2b10: aluout = a & b;
else if (biu thc) default:
Begin aluout = 1bx;
cc lnh endcase
end
else
 Chng IX KHI ALWAYS V KHI INITIAL Chng X- HM
I. Khi always: Hm c khai bo trong phm vi mt module, v c th c gi
L cu trc chnh trong khun mu RTL (Register Transfer Level). t cc lnh lin tc, khi always, hoc cc hm khc. Trong lnh ch nh
Khi always c th c dng trong cht, flip flop hay cc kt ni logic. lin tc, cng c ch nh lin tc khi bt k cc hm khai bo u vo
Tt c cc khi always trong mt module thc thi mt cch lin tc. Nu thay i. Trong chng trinh chng c ch nh ti khi cn gi.
cc lnh ca khi always nm trong phm vi khi begin end th c Cc hm m t s kt ni logic, v khng to ra cht. Do mt
thc thi lin tc, nu nm trong khi fork join, chng c thc thi ng lnh if m khng else s m phng , mc d n c cht d liu nhng m
thi (ch trong m phng). Khi always thc hin bng mc, cnh ln/xung phng th khng c. y l trng hp d ca tng hp khng c m
ca mt or nhiu tn hiu (cc tn hiu cch nhau bi t kha OR). phng theo sau. y l khi nim tt m ha hm, v vy chng s
C php: khng to ra cht nu m hm c dng trong mt chng trnh.
Always @(s kin 1 or s kin 2 or) I. Khai bo hm:
Begin Khai bo hm l ch ra tn hm, chiu rng ca hm gi tr tr v,
cc lnh i s hm d liu vo, cc bin (reg) dng trong hm, v tham s cc b
end ca hm, s nguyn ca hm.
Always @(s kin 1 or s kin 2 or) 1. C php:
Begin: tn khi Function [msb:lsb] tn hm;
cc lnh Input [msb:lsb]bin vo;
end Reg [msb:lsb]bin reg;
II. Khi initial Parameter [msb:lsb] tham s;
Tng t khi always nhng khi initial ch thc thi mt ln t lc Integer [msb:lsb] s nguyn;
bt u ca qu trnh m phng. Khi ny l tiu biu bin khi chy v cc lnh
ch nh dng sng tn hiu trong lc m phng. endfunction
1. C php: 2. V d
Initial Function [7:0] my_func; // hm tr v gi tr 8 bit
Begin Input [7:0] i;
cc lnh Reg [4:0] temp;
end Integer n;
2. V d: temp = i[7:4]| (i[3:0]);
Initial my_func = temp,i[1:0] ;
Begin endfunction
Clr = 0; II. V d:
Clk = 1; Mt hm ch c cha mt d liu ra. Nu c nhiu hn mt gi tr
End tr v c yu cu, u ra s phi kt ni to thnh mt vector trc khi
Initial t gi tr cho hm gi tn hm. Gi tn chng trnh module c th trch
Begin ra sau , ring i vi u ra t cc biu mu ni vo nhau. V d di y
a = 2b00; minh ha tng qut cch dng v c php hm trong verilog.
#50 a = 2b01; 1. C php:
#50 a = 2b10; end Tn hm = biu thc.
2. V d: {func, opr2, opr1}= decode_add (intruction);
Module simple_processor (instruction, outp); if (func= =1)
Input [31:0] instruction; outp = opr1+ opr2;
Output [7:0] outp; else
Reg [7:0] outp;// c th c gn trong khi always. outp = opr1 opr2;
Reg func; end
Reg [7:0] opr1, opr2; endmodule
Function[16:0] decode add(instr)
Input [31:0] instr; Chng XI
Reg add_func;
Reg [7:0] opcode, opr1, opr2;
CHC NNG LINH KIN
Cht d liu (latches): c suy nu mt bin, mt trong cc bit
Begin
khng c gn trong cc nhnh ca mt lnh if. Cht d liu cng c
Opcode = instr[31:24];
suy ra t lnh case nu mt bin c gn ch trong mt vi nhnh.
Opr1 = instr[7:0];
C php:
Case (opcode)
If else if else v case.
8b 10001000:
I. Thanh ghi Edge_triggered, flip_flop, b m:
begin
Mt thanh ghi (flip_flop) c suy lun bng vic dng xung kch
add_func = 1;
cnh ln hoc xung trong danh sch s kin ca lnh khi always.
opr2 = instr[15:8];
C php:
end
Always @(posedge clk or posedge reset1 or nesedge reset2)
8b 10001001:
Begin
begin
If (reset1) begin
add_func = 0;
Cc ch nh reset
opr2 = instr[15:8];
end
end
else if (reset2) begin
8b 10001010: begin
Cc ch nh reset
add_func = 1;
End
opr2 = 8b 00000001;
Else begin
end
Cc ch nh reset
default: begin
End
add_func = 0;
opr2 = 8b00000001;
II. B a cng:
end
c suy ra bi vic gn mt bin m gi tr mi bin khc nhau
endcase
trong mi nhnh ca lnh if hoc case. C th trnh cc ch nh v mi
decode_add = add_func, opr2, opr1 ;
nhnh c th tn ti bng vic s dng ngoi nhng nhnh mc nh. Ch
end
rng cht s c to ra nu mt bin khng c gn cho cc iu kin
endfunction
nhnh c th tn ti.
always @(intruction) begin
 hon thin m c th c c, dng lnh case to mu a cng ln. Chng XII - MT S V D
I. Cu trc mt chng trnh dng ngn ng Verilog:
III. B cng, tr: // Khai bo module
Ton t cng tr trong b cng tr m c chiu rng ph thuc vo Module tn chng trnh (tn bin I/O); // tn chng trnh trng tn
chiu rng ca ton t ln hn. file.v.
Input [msb:lsb] bin;
IV. B m 3 trng thi: Output [msb:lsb] bin;
B m ba trng thi c suy ra nu bin c gn theo iu kin Reg [msb:lsb] bin reg;
gi tr tng tr cao Z dng mt trong cc ton t: if, case, Wire [msb: lsb] bin wire;
// Khai bo khi always, hoc khi initial.
V. Cc linh kin khc: cc lnh
Hu ht cc cng logic c suy ra t vic dng nhng ton hng Endmodule
tng ng ca chng. Nh mt s la chn mt cng hoc mt thnh phn II. Mt s v d:
c th c gii thch r rng bng v d c th v s dng cc cng c s Phn mn h tr: MAX+plusII 10.0 BASELINE
(and, or, nor, inv) min l bng ngn ng Verilog. 1. V d 1:
a. Chng trnh tnh NOR cc bit ca bin vo
module vdcong(in,out);
input[3:0] in;
output out;

assign out= ~|in;

endmodule

b. M phng

2. V d 2:
a. Chng trnh cng hai bin bn bit
module adder (sum_out, carry_out, carry_in, ina, inb);
 output [3:0]sum_out; wire en;
input [3:0]ina, inb;
output carry_out; always @(w or en)
input carry_in;
begin
wire carry_out, carry_in; if(en==1'b1)
wire[3:0] sum_out, ina, inb; begin

assign case(w)
{ carry_out, sum_out } = ina + inb + carry_in; 2'b00: y<=4'b1000;
2'b01: y<=4'b0100;
Endmodule 2'b10: y<=4'b0010;
default:y<=4'b0001;
b. M phng endcase
end

else
y<= 4'b0000;
end

endmodule

b. M phng

3. V d 3:
a. Chng trnh gii m 2 sang 4

module dec2to4 (w, en, y);

input [1:0] w;
input en;
output[3:0] y;

wire[1:0]w;
reg[3:0]y;
 input w0, w1, w2, w3;
4. V d 4: input[1:0] s;
a. B dn knh 2 sang 1 output y;
module mux12(w0, w1, s, y);
input w0, w1; wire w0, w1,w2,w3;
input s; reg y;
output y; always @(w0 or w1 or s)
begin
wire w0, w1, s; case (s)
reg y; 2'b00: y=w0;
always @(w0 or w1 or s) 2'b01: y=w1;
2'b10: y=w2;
begin default: y = w3;
if(s==1)
y = w0; endcase
else
y = w1; end
end
endmodule
endmodule
b. M phng
b. M phng

6. V d 6:
a. Chng trnh i BCD sang by on
5. V d 5: Module mp_led(bcd,led);
a. Chng trnh dn knh 4 sang 1 input [3:0] bcd;
module mux14(w0, w1, w2, w3, s, y); output [7:0] led;

wire [3:0] bcd;
reg [7:0] led;
always @(bcd)
begin
case(bcd)
4'b0000: led = 8'b00000011;
4'b0001: led = 8'b10011111;
4'b0010: led = 8'b00100101;
4'b0011: led = 8'b00001101;
4'b0100: led = 8'b10011001;
4'b0101: led = 8'b01001001;
4'b0110: led = 8'b01000001;
4'b0111: led = 8'b00011111;
4'b1000: led = 8'b00000001;
4'b1001: led = 8'b00001001;
default: led = 8'b00000000;
endcase
end
endmodule
b. M phng
7. V d 7:
a. Chng trnh gim t 9 xung 0, hin th ra led 7 on
module bcd (clock, rst, s1, led, digit1);
input clock, s1, rst;
output [7:0] led;
output digit1;
reg [7:0] led;
reg [3:0] bcd;
wire digit1;
assign digit1 = 1'b1;
always @(posedge clock )
begin
if (rst == 1'b1) bcd <= 4'b1001;
else if (s1 == 1'b1) bcd <= bcd - 1'b1;
if (bcd == 4'b0) bcd <= 4'b1001;
end
always @(posedge clock)
begin
case(bcd)
4'b0000: led = 8'b11111100;
4'b0001: led = 8'b01100000;
4'b0010: led = 8'b11011010;
4'b0011: led = 8'b11110010;
4'b0100: led = 8'b01100110;
4'b0101: led = 8'b10110110;
4'b0110: led = 8'b10111110;
4'b0111: led = 8'b11100000;
4'b1000: led = 8'b11111110;
4'b1001: led = 8'b11100110;
default: led = 8'b11111111;
endcase
end
endmodule
b. M phng 4'b0010: led = 8'b11011010;
4'b0011: led = 8'b11110010;
4'b0100: led = 8'b01100110;
4'b0101: led = 8'b10110110;
4'b0110: led = 8'b10111110;
4'b0111: led = 8'b11100000;
4'b1000: led = 8'b11111110;
4'b1001: led = 8'b11100110;
default: led = 8'b11111111;
endcase

end

endmodule
8. V d 8: b. M phng
a. Chng trnh tng t 0 n 9, hin th ra led 7 on
module bcdtang (clock, rst, s1, led, digit1);
input clock, s1, rst;
output [7:0] led;
output digit1;

reg [7:0] led;

reg [3:0] bcd;
wire digit1;
assign digit1 = 1'b1;

always @(posedge clock )

begin
if (rst == 1'b1) bcd <= 4'b0;
else if (s1 == 1'b1) bcd <= bcd + 1'b1;
if (bcd == 4'b1001) bcd <= 4'b0000; TI LIU THAM KHO
end
1. Verilog Digital System Design
always @(posedge clock) 2. Introduction of Verilog Peter M. Nyasulu
begin 3. Cadence Verilog XL Reference Manual
case(bcd) 4. Synopsys HDL Compiler for Verilog Reference Manual
4'b0000: led = 8'b11111100;
4'b0001: led = 8'b01100000;