Stick Diagrams and Tutorial PDF

Stick Diagrams
Stick Diagrams
by
Rita Jain
Professor and Head
Department of Electronics and Communication Engineering
Lakshmi Narain College of Technology, Bhopal
ritajain_bpl@yahoo.com
1
Rita Jain, Faculty, Department of Electronics & Communication Engineering, LNCT, Bhopal
Stick Diagrams
Layout
The Design Rules describe:
Minimum width to avoid breaks in a line
Minimum spacing to avoid shorts between lines
Minimum overlap to ensure two layers completely overlap
Unit Transistor
Transistor dimensions are specified by their W/L ratio
For 0.6 m process, W = 1.2 m and L = 0.6 m
Such a minimum width contacted transistor is called UNIT
TRANSISTOR
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Stick Diagrams
Inverter Layout
Transistor dimensions specified as Width / Length
Minimum size is 4 / 2, sometimes called 1 unit
For 0.6 mm process, W=1.2 m, L=0.6 m
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Stick Diagrams
Layout
A conservative but easy to use Design Rules for n-
well process is as follows:
Metal and diffusion have minimum width spacing of 4
Contacts are 2 X 2 and must be surrounded by 1
on the layers above and below
Polysilicon uses a width of 2
Polysilicon overlaps diffusion by 2 where a transistor
is desired and has a spacing of 1 away where no
transistor is desired
Polysilicon and contacts have a spacing of 3 from
other polysilicon or contacts
N-well surrounds PMOS transistors by 6 and avoids
NMOS transistors by 6
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Stick Diagrams
Simplified Design Rules
Conservative rules to get you started
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Stick Diagrams
Stick Diagrams
Stick diagrams help plan layout quickly

Need not be to scale
Draw with color pencils or dry-erase markers
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Stick Diagrams
Stick Diagrams
VLSI design aims to translate circuit concepts

onto silicon.
stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic circuit
and the actual layout.
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Stick Diagrams
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
Does not show

Exact placement of components
Transistor sizes
Wire lengths, wire widths, tub boundaries.
Any other low level details such as parasitics.
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Stick Diagrams
Wiring Tracks
A wiring track is the space required for a wire

4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track
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Stick Diagrams
Well Spacing
Wells must surround transistors by 6

Implies 12 between opposite transistor flavors
Leaves room for one wire track
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Stick Diagrams
Area Estimation
Estimate area by counting wiring tracks

Multiply by 8 to express in
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Stick Diagrams
Example: Inverter
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Stick Diagrams
Example: NAND3
Horizontal N-diffusion and p-diffusion strips

Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
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Stick Diagrams
Stick Diagrams Some rules

Rule 1.
When two or more sticks of the same type cross
or touch each other that represents electrical
contact.
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Stick Diagrams

Rule 2.
When two or more sticks of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).
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Stick Diagrams

Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.

16
Stick Diagrams

Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.
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Stick Diagrams
Stick Diagrams
N+ N+
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Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x Stick x x
x Diagram X
Gnd Gnd
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Stick Diagrams
Stick Diagrams
VDD
VDD
X
X
x x x
x X
Gnd Gnd
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Stick Diagrams
Stick Diagrams Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Similarly for contacts, via, tub etc..
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Stick Diagrams
How to draw Stick Diagrams
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Stick Diagrams
NOR Gate
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Stick Diagrams
Stacked Layout
Power
A Out
Ground
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Stick Diagrams
Methods for generating Stick Diagrams
Construct a Logic Graph of the Schematics

Identify each transistor by a unique name of its gate signal (A, B, C, D
..)
Identify each connection to the transistor by a unique name
(1,2,3,4,5,..)
Construct an Euler Path for both pull-up and pull-down network
Euler Path is defined by a path that traverses each node in the path,
such that each edge is visited only once
Path is defined by the order of each transistor name
Euler Path for the pull-up network must be same as the path of pull-
down network
Euler paths are not necessarily unique
It may be necessary to redefined the function to find a Euler path
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Stick Diagrams
Methods for generating Stick Diagrams

Once the Euler path is found it is time to layout the stick
diagram
Trace two lines horizontally to represent PMOS and NMOS
Trace the number of Inputs vertically across each strip.
These represent the gate contacts to the devices that are
made of poly
Surround NMOS and PMOS by P-well and N-well
Trace a blue line horizontally above and below the PMOS
and NMOS lines to represent the metal of VDD and VSS
Label each poly line with the Euler path label, in order from
left to right
Place the connection label upon NMOS and PMOS
devices
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Stick Diagrams
Stick Diagrams
Sketch a stick diagram for O3AI and estimate

area
Y = ((A+B+C).D)
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Stick Diagrams
Stick Diagrams
VDD VDD
A A
Y
B D
B D D
C
Y C A B C
D
Y VSS
Pull-up Network Pull-down Network

A B C
VSS
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Stick Diagrams
Stick Diagrams
29
Stick Diagrams
Area Estimation
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Stick Diagrams
OAI21 Logic Graph

A
j C X
B
C
X = !(C (A + B)) B
C i X j
i C
A
B A
A B
GND VDD
A PDN PUN
B
C
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Stick Diagrams
Home Work
1. Draw the stick diagram for two input CMOS NAND gate.
2. Draw the stick diagram for two input NAND gate using NMOS
Logic.
3. Draw the stick diagram for 2:1 MUX using
a) Pass transistors
b) Transmission gates.
4. Draw Stick Diagrams for the following equations Y = ( A + B + C ).D
: Y = A + ( B + C ).D
5. For a process technology with L = 5 micron meter give the size of the
layout for the following : (a) 4-input NOR gate and 4-Input NAND gate
6. Draw Stick Diagram for the circuits given below and estimate its area
(circuits given in next few slides)
7. Identify the logic functions (stick diagrams given in next few slides)
Drawing stick diagram is truly Fun !!!

Enjoy it !!!
32
Stick Diagrams
Draw Stick Diagram for the circuit given below and

estimate its area
B
A
C
D
OUT = !(D + A (B + C))
A
D
B C
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Stick Diagrams
Draw Stick Diagram for the circuits given below and estimate its
area
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Stick Diagrams
Draw Stick Diagram for the circuits given below and

estimate its area
A C
A
B D B
C
D
X = !((A+B)(C+D))
C D
A B
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Stick Diagrams
What logic function is this?
Routing
channel
VDD
signals
GND

36
Stick Diagrams
A C B A B C
VDD VDD
X X
GND GND
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Stick Diagrams

A B D C
VDD
GND
38

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Stick Diagrams

Simplified Design Rules

Conservative rules to get you started

Stick diagrams help plan layout quickly

VLSI design aims to translate circuit concepts

Does not show

A wiring track is the space required for a wire

Wells must surround transistors by 6

Estimate area by counting wiring tracks

Horizontal N-diffusion and p-diffusion strips

Stick Diagrams Some rules

Stick Diagrams Some rules

Stick Diagrams Some rules

Note: If a contact is shown then it is not a transistor.

Stick Diagrams Some rules

Stick Diagrams Notations

Similarly for contacts, via, tub etc..

How to draw Stick Diagrams

Methods for generating Stick Diagrams

Construct a Logic Graph of the Schematics

Methods for generating Stick Diagrams

Sketch a stick diagram for O3AI and estimate

Pull-up Network Pull-down Network

OAI21 Logic Graph

Drawing stick diagram is truly Fun !!!

Draw Stick Diagram for the circuit given below and

Draw Stick Diagram for the circuits given below and

What logic function is this?

What logic function is this?

What logic function is this?

What logic function is this?

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