TASK – 3

VLSI LAB

Name- Saurabh Priyadarshi

Reg. No- 15BEC0631
Slot- L53+L54

3. (I). a. Plot the DC characteristics / 5 regions of a CMOS inverter

AIM:
To create schematic for CMOS inverter and plot DC characteristics for 5 regions of the
CMOS inverter.

Circuit:
Output Waveform:
3. (I). b. Determine NML and NMH for CMOS inverter

AIM:
Calculate noise margin for CMOS inverter

Procedure:
1. Using the circuit made for 3 input NAND gate.
2. Open ADE L
3. Choose DC analysis>component parameter
4. Choose the input ‘C’ as the component parameter.
5. Set start value as 0v and stop value as 1.2v
6. Go to output>to be plotted>select on design> select the output
7. Run simulation to attain DC analysis.
8. Go to tools in ADE L window and select calculator.
9. Clear buffer and stack in calculator and select wave option.
10. Click on the DC analysis wave attained by the simulation.
11. Select derive option given in the tab at the below of the calculator tab.
12. Simulate to obtain graph for calculation of NML NMH.

Output waveform for calculations of NMH and NML:

From the above graphs, we get the following values:
VOH=1.065v
VOL=84.725mv
VIL=480.57mv
VIH=768.34mv

Calculations for NMH and NML:

NMH=VOH-VIH
=1.065-0.768
=0.297

NML=VIL-VOL
=0.48-.084
=0.396

Results:
For a CMOS inverter proper sizing was done and was verified.
For the properly sized inverter NML was found to be 0.396v and NMH was found to be
0.297v.
3. (II). a. Design a 3 input NAND gate with proper sizing

AIM:
To design a 3 input NAND gate with proper sizing

Procedure:
1. Draw thee schematic of a 3 input NAND by placing the required NMOS and PMOS
2. Change the total width of each PMOS to 360 nm.
3. Open ADE L
4. Do a transient analysis or 20n to verify the output of the NAND gate.

Circuit Diagram:
3. (II). b. Determine NML and NMH for CMOS inverter

AIM:
Calculate the noise margin for 3 input NAND gate.

Procedure:
1. Using the circuit made for 3 input NAND gate.
2. Open ADE L
3. Choose DC analysis>component parameter
4. Choose the input ‘C’ as the component parameter.
5. Set start value as 0v and stop value as 1.2v
6. Go to output>to be plotted>select on design> select the output
7. Run simulation to attain DC analysis.
8. Go to tools in ADE L window and select calculator.
9. Clear buffer and stack in calculator and select wave option.
10. Click on the DC analysis wave attained by the simulation.
11. Select derive option given in the tab at the below of the calculator tab.
12. Simulate to obtain graph for calculation of NML NMH.

Output waveforms for calculations of NMH and NML:

From the above graphs, we get the following values:
VOH=1.0293v
VOL=55.097mv
VIL=616.139mv
VIH=856.81mv

Calculations for NML and NMH:

NMH=VOH-VIH
=1.0293v - 0.856v
=0.173mv

NML=VIL-VOL
=616.139mv - 55.097mv
=0.561mv

Results:
From the properly sized inverter NML was found to be 0.561mv and NMH was found to be
0.173mv.