2023 EE5215 Image Sensor IC Design Final Project

Due date:2023/06/16

Fig.1. The whole block diagram of SAR ADC

⚫ This Final Project is for you to design a 25MS/s 10-bit successive approximation
register (SAR) ADC circuit that uses a Vcm-based switching procedure.
The results should include HSPICE simulations. The SPICE model is cic018.l.
⚫ Please use VDD = Vrefp = 1.8 V, Vss = Vrefn = 0 V, Vcm = 0.9V
⚫ Set the temperature at 25 ﾟ C
⚫ The loading capacitor is CDACP = CDACN = 1024C = 1pF
⚫ In the previous two assignments, the sample and hold circuit and comparator have
been designed.
⚫ The first step of this final project is to design the SAR Logic, which includes the
Asynchronous Clock Control Logic and DAC Control Logic. Following that, the
subsequent step is to simulate the whole SAR ADC circuit.
⚫ The sampling clock frequency is 25MS/s and the duty cycle of Clks signal is 20%
of whole clock period. The rise time and fall time of Clks is 0.1ns.
⚫ The input signals Vip and Vin are sine wave signals with a common mode
voltage of 0.9V and differential voltage range of ±0.9V. You can also adjust the
input range to meet the specifications.
⚫ Coherent sampling is needed. Set input frequency Fin = ( Nfin /Nsamp *Fs =
Nyquist frequency. Nsamp = 1024, Nfin = 511, Fs = 25MHz
⚫ The following should be included in your report (a schematic (b waveform with
Cursor values (c comments
⚫ Please generate your report with pdf format. At first page please add your student
ID and name. Try to make the information “readable”.
(Note: Don’t use black color in background for your screen capture figures.
1. Design the SAR Logic circuits
(1) Design the Asynchronous Clock Control Logic. The circuit architecture and
timing diagram are shown in Fig.2. The DFF architecture is free for you. To
avoid using a high frequency clock generator, this SAR ADC uses an
asynchronous control circuit to internally generate the clock control signal. Clks
is the only external voltage signal.

(Note: Clks is the control signal of bootstrapped switches. Clkc is the control
signal of the two-stage dynamic comparator. Clk0 to Clk9 serve as control
signals for the capacitor arrays to perform the Vcm-based switching procedure
and sample the digital output codes of the comparator.

(Note: In order to reduce the conversion time, alternative comparator

architecture can be used. However, it is necessary for you to ensure that the
comparator noise sigma voltage is less than 0.25LSB.

Fig.2(a Asynchronous clock control logic architecture

Fig.2(b Timing diagram

(2) Design the DAC control logic. The DAC control logic and Latch circuit
architecture are shown below. The simplest logic circuit is for you as a reference.
You can design the circuit by yourself. Considering different sizes of capacitor
array, you can design different DAC control analog switches sizes to optimize
the power consumption and DAC settling time.

(Note : Outp and Outn are output signal of the comparator. Clk<i> is the control
signal generated by asynchronous clock control logic. P<i> and N<i> are the
nodes of CDAC bottom plate.

(Note : The purpose of the DAC control logic is to sample the digital output
codes of comparator to corresponding Bit<i> and use analog switches to switch
the bottom plate of the CDAC from Vcm to either Vrefp or Vrefn, allowing the
generation of the desired analog output voltage based on the digital input code

Fig.3. DAC Control Logic circuit architecture (i=0~9

 Fig.4. Latch circuit Architecture

2. Design the entire SAR ADC architecture

(1) As in Fig.1, connect all the blocks you have designed together. Please use
composer to construct the whole diagram.
(Note : Including bootstrapped switches, comparator circuit, asynchronous
clock control logic, DAC control logic and CDAC

(2) Please run the transient simulation and plot the timing diagram of the entire
SAR ADC architecture. Try to explain the operational timing sequence.
(Note : Including Clks, Clkc, Vip, Vin, DACP, DACN, Outp, Outn, Valid,
Clk0~Clk9, Bit0~Bit9, P0~P9, N0~N9 or some important nodes
(Note : In order to facilitate waveform observation, multiple screenshots can be
used to display the waveforms of the required nodes separately, instead of all
nodes in one screen, which may cause difficulty in reading.

(3) Please export the digital codes Bit0 to Bit9 at the end of every cycle, which
consists of 1024 points, to a .csv file and run the MATLAB code provided by
TA. For all corners at Nyquist frequency, your ENOB of the FFT result should
be > 9.9 bits. Plot your fft spectrum for five corners and record your result in
𝑃𝑜𝑤𝑒𝑟
the blank. (Note : FoM =
2𝐸𝑁𝑂𝐵 ∗𝑓𝑠

TT FF SS SF FS
ENOB (bits
Power (µW
FOM (fJ/conversion step

(4) List power breakdown of your SAR ADC (S/H circuit, Comparator circuit,
Reference voltage, Digital circuits . And discuss how to achieve better FOM.