ADVD Analog Assignment - 2023ss

Analog Design Assignment
Analog & Digital VLSI Design EEE/ INSTR F 313

Oct. 20, 2023
Abstract
Please read through this entire document carefully before embarking on your assignment or asking any
queries.
Introduction
For this assignment, you are required to design a simple operational amplifier. You will be given a few
classes of circuits along with the specifications. You are required to meet all the given specifications.
You need to make the choice and then decide numerical values for each of the system specs that will be
enumerated for you. For this job, you might need to refer to journals and other publications. The library
IEEE site is a good place to start. The Internet is of course an excellent place to scrounge around for
information.
In real life, the specifications would be provided to you by a "customer". As a designer your job is to meet
those specifications. The ability to look at system specifications and translate them to specs for individual
building blocks is an important aspect of design. This assignment will help you get a feel for this.
Assignment Requirement
The instructions given here will need to be followed by all students. Please note that failure to do the
same will result in a penalty of marks. You have to work on this assignment in groups of three only. Each
group is required to submit one copy of the assignment report,
 You have to use Cadence/ LTSPICE Schematic editor to draw your circuit.
 For simulation you have to use SPICE simulators.
 Your design should meet all the specifications, at Schematic level.
 If you are not able to meet your specs, you can go ahead, but you need to explain why it has
happened at the time of demonstration and in report.
 Validate your design for all process corners ( SS, FF, TT) and temperatures 0, 27 and 100 ⁰C.
 Min. channel length that can be used is 0.36um.
 ‘Current sink’ means that one of the nodes is connected to ground and ‘current source’ means that
one of the nodes is connected to the supply.
 Your Design Should have only one ideal current Source/Sink .
 The suggested topologies are to be used unless there is a valid reason not to do the same.
 Make sure that all the transistors are working in saturation region.
 ‘OTA’ stands for Operational Transconductance Amplifier, which is basically an OPAMP with
high output resistance.
 All OPAMPs/OTAs used feedback must be compensated for a phase margin of about 50⁰ to 60⁰,
unless your application requires it to be some other value.
 Discussing with your friends is highly encouraged (but not copying). Plagiarism will be
penalized.
 There will be no deadline extensions or other considerations based on server or software issues.
You are being given ample time and it is expected that you partition your work well into that time
to avoid last minute rush.
For students using cadence---
 Library for circuit simulation is with Sections TT_3V, FF_3V, SS_3V

 Use Model names pch3 for PMOS and nch3 for NMOS, unless otherwise specified. Connect the
body of PMOS to Vdd and NMOS to Ground.
Report Submission---
A detailed report should be submitted with following sections—
 Problem statement and specifications

 Schematic of your design
 Table containing (W/L) of each transistor
 Results – ( each result with snapshot e.g 3dB bandwidth result with its labelled
simulation snapshot)
 Conclusion--- (all results obtained in Tabular format along with a column giving
specification values)
 Problems faced during the design
 Innovation in the design ( some design innovation, you have thought on your own)
First page of report should contain name/ id of all team members
SAVE YOUR REPORT AS (PROBLEM_XX. PDF ) (EXAMPLE--- PROBLEM_55.PDF)
Suggested Design Procedure

Based on the specification given, you will need to decide which OPAMP architecture will help you meet
the specs most easily. For example, if a large bandwidth is required it might be inadvisable to use a two-
stage OPAMP since the compensation capacitance reduces the bandwidth heavily. At the same time
trying to use a large bandwidth OPAMP architecture when a moderate or small bandwidth is required is
considered overkill and will result in penalization in terms of marks.
Specifications
There will be some common specifications which all of the assignment have to meet or follow.
Parameters Specifications
Technology 180nm technology*
VDD 2.5V
CL ≤2 pF
Current mirror ratios ≤ 50
Reference Current Single ideal current source of arbitrary value, with the positive
node tied to VDD or negative node tied to ground
Power Dissipation ≤ 2.5mW unless stated
* Although the technology is 180nm, you are to use the 360nm transistors which are in the design kit for
analog design. The 180nm transistors specifically refer to the digital transistors and will not be able to
sustain the power supply of 2.5V. You will be given a zero in your assignment if you fail to follow this
particular directive.
Q1. Design a two-stage CMOS OPAMP as shown in figure (a) below, for designing a precision peak detector
circuit for 2.2 V , 1 MHz sinusoid input
a) Analysis of all equations of your design, with a systematic derivation of all transistors W/L
ratios and spectre simulation of circuit for the following specifications.
i) Open loop gain(DC gain) ≥ 80 dB
ii) Phase margin ≈ 600
iii) power dissipation ≤ 0.1mW
b) Show a biasing circuitry to bias all the voltages in your
design (except the input).
c) Calculate and plot the following parameters for your
OPAMP: DC gain, Bode plot for AC gain and phase,
ICMR plot, slew rate, Differential Output voltage swing
(dc + Transient), power consumption, and input and (a)
output offset voltage.
Q2. Design a Folded-Cascode CMOS OPAMP for designing precision half wave rectifier shown in figure (a)
below for 0 to 2V, 1 MHz sinusoidal input.
(a)
a) Analysis of all equations of your design, with a systematic derivation of all transistors W/L ratios
and spectre simulation of circuit for the following specifications.
iv) Open loop gain(DC gain) ≥ 80 dB

v) UGB ≥ 500 MHz
vi) Phase margin ≈ 500
vii) ICMR ≥ 1.8 V
b) Show a biasing circuitry to bias all the voltages in your design (except the input).
c) Use STB analysis to measure the closed loop gain and phase margin.
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain
and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc
+ Transient), power consumption, and input and output offset voltage.
Q3. Design a two stage differential output OPAMP (Telescopic + CGA gain stage) for the following
specification
i) Gain ≥ 90 dB
ii) UGB ≥ 100 MHz
iii) Phase margin ≈ 600
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power
consumption, and input and output offset voltage.
Q4. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage) for the
following specification
i) -3dB Frequency ≥ 100 KHz
ii) Power Dissipation ≤ 1.5mW
c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +
transient), power consumption, and input and output offset voltage.
Q5. Design a CMOS OPAMP.
a) Analog schematic for the above model

b) Analysis of all equations of your design, with a systematic derivation of all transistors W/L ratios
i) Gain ≥ 100 dB
ii) Settling time ≤ 20ns
iii) UGB ≥ 200 MHz
iv) Slew rate ≤ 20 V/µs
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +
Transient), power consumption, and input and output offset voltage.
Q6. Design a two-stage single-ended output CMOS OPAMP with a UGB of 600MHz and a phase margin
of 600.
(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.
(Do not use hit-an-trial method)
(c) What is the closed loop gain and phase margin for your OPAMP using STB analysis?
(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
Q7. Design a Two Stage Single-ended output CMOS OPAMP with a -3dB bandwidth of 1MHz, a phase
margin of 600, a gain of 100000 V/V.

(c) Use ( in cadence-) STB Analysis to find the closed loop gain and phase margin for your OPAMP.
Q8. Design a two stage single-ended output CMOS OPAMP with a UGB of 100MHz, a phase margin of
600, a gain of 15000 V/V.

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.
Q9. Design a two stage single-ended output CMOS OPAMP having PSRR and CMRR ≥ 120dB.

Q10. Design a two stage single-ended output CMOS OPAMP having slew rate greater than 20 V/us,
settling time less than 1us, a phase margin of 600 and a gain of 5000 V/V.

Q11. Design a two stage single-ended output CMOS OPAMP having power dissipation ≤ 0.1mW and a
gain of 1500V/V.


i) UGB ≥ 400 MHz
iii) Slew rate >= 50 V/µs
c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

i) DC Gain ≥ 120 dB
iii) Power dissipation ≤ 2mW

i) CMRR ≥ 140 dB
ii) PSRR ≥ 120dB
iii) Output Swing ≥ 1.6V

i) 3dB Frequency ≈ 100 KHz
iii) Output swing ≥ 1V
Q16. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a
transistor)
i) -3dB Bandwidth ≥ 10 KHz
ii) Slew rate ≥ 50 V/µs
iii) Output offset voltage ≤ 40mV
b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.
c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
Q17. Design a Single-ended output Folded Cascode OTA.
a) Analog schematic for OTA

b) Analysis of all equations for OTA, with a systematic derivation of all transistors W/L ratios and
spectre simulation of circuit for the following specifications.
c) Show a biasing circuitry to bias all the voltages in your design (except the input).
d) Use STB analysis to measure the closed loop gain and phase margin.
e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
Q18. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage] OTA.
Use PMOS as the input transistor.

i) ICMR ≥ 1.8 V
ii) CMRR ≥120dB
iii) output Swing ≥ 2V
Q19. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following
specification
i) DC gain ≥ 100 dB
ii) Output voltage swing ≥1.5V
iii) ICMR ≥ 1.5V
iv) Slew rate ≤ 100V/µs
v) Settling time ≤ 50ns
.
Q20. Design a two stage single-ended output CMOS OPAMP with a UGB of 500KHz, a phase margin of
600, a gain of 120dB.

transistor)
i) Open loop gain (DC gain) ≥ 80 dB
ii) CMRR ≥ 100 dB
iii) power dissipation ≤ 1mW
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +
transistor)
i) Open loop gain (DC gain) ≥ 80 dB
ii) Settling time ≤ 20 us
iii) power dissipation ≤ 0.5mW
phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +
transistor)
i) PSSR ≥ 100 dB
ii) DC Gain (open loop) ≥ 100dB
iii) Power Dissipation ≤ 1mW
transistor)
i) UGB ≥ 100 MHz
ii) Output swing ≥ 1.5 V
Q25. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following
specification
i) -3dB Frequency ≥ 100 KHz
iii) ICMR ≈ 0.9V to 2.2V
specification
i) Gain ≥ 90 dB
ii) UGB ≥ 100 MHz
Q27. Design a Two stage single-ended output CMOS OPAMP with a -3dB bandwidth of 5MHz.

(c) What is the settling time for your OPAMP?
(d) What is the closed loop gain and phase margin for your OPAMP using STB analysis?
(e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and
Q28. Design a fully differential two stage OPAMP (Differential + gain stage) for the following
specification
ii) Differential Output voltage swing ≥ 3.5V
phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power
Q29. Design a fully differential two stage OPAMP (Differential + gain stage) for the following
specification
ii) Power Dissipation ≤ 1mW
phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power
Q30. Design a folded Cascode OPAMP as shown in figure;
a) Analysis of all equations of your design, with a

systematic derivation of all transistors W/L ratios and
spectre simulation of circuit for the following
specifications.
viii) Open loop gain(DC gain) ≥ 80 dB
ix) UGB ≥ 100 MHz
x) Phase margin ≈ 600
phase, ICMR plot, slew rate, Output voltage swing
differential (dc + Transient), power consumption, and
input and output offset voltage.

i) UGB ≥ 300 MHz
phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

specifications.
i) DC gain ≥ 120dB
ii) Differential Voltage Swing ≥ 4V
iii) ICMR ≥ 2.2V
b) Show a biasing circuitry to bias all the voltages in
your design (except the input).
phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption,
and input and output offset voltage.

specifications.
ii) 3dB Frequency ≥ 10 KHz
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR
plot, slew rate, Output voltage swing differential (dc + Transient), power consumption, and input
and output offset voltage.
Q34. Design a folded Cascode OPAMP as shown in

figure;

specifications.
i) DC Gain ≥ 100dB
iii) 3dB Frequency ≥ 1 KHz
phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption,
Q35. Design a folded Cascode OPAMP as shown in

figure;

specifications.
i) Differential Voltage Swing ≥ 4V
ii) ICMR ≥ 2.2V
iii) power dissipation ≤ .1mW
phase, ICMR plot, Slew rate, Output voltage swing differential (dc + Transient), power consumption,

i) DC Gain ≥ 90dB
ii) Power dissipation ≤ .5mW
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, Slew rate, Output voltage swing
differential (dc + Transient), power consumption, and input and output offset voltage.
d) Analysis of all equations of your design, with a

specifications.
iii) DC Gain ≥ 80dB
iv) Power Dissipation ≤ 0.4mW
e) Show a biasing circuitry to bias all the voltages in your
f) Calculate and plot the following parameters for your
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing
Q38. Design a telescopic OPAMP as shown in figure;
a) Analysis of all equations of your design, with a systematic

derivation of all transistors W/L ratios and spectre
simulation of circuit for the following specifications.
ii) UGB ≥ 200 MHz
iii) Differential Output voltage swing ≥ 4V
c) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
margin, slew rate, ICMR, Differential Output Swing (dc + Transient), Offset voltage and power
consumption.

specifications.
ii) power dissipation ≤ 0.1 mW
margin, slew rate, ICMR, Differential output swing (dc + Transient), input offset voltage and
power consumption.

c) Also calculate the following parameters for your OPAMP:
Bode plot for AC gain and phase margin, slew rate, ICMR,
Differential output swing (dc + Transient), input offset
voltage and power consumption.
Q41. To achieve high swing in telescopic OPAMP a student removed the tail current source but at cost
of common-mode rejection and power-supply rejection.
a) Design a high swing telescopic OPAMP.

ii) Output voltage swing ≥ 4V

ii) UGB ≥ 400 MHz
iii) Output voltage swing ≥ 4V
Q43. Design a two-stage fully-differential OPAMP (Telescopic + gain stage) for the following
specification
ii) Output voltage swing ≥ 4V
iii) -3 dB frequency ≥ 5 KHz
specification
i) UGB ≥ 600 MHz
iii) Settling time ≤ 20ns
specification
i) Gain ≥ 90 dB
ii) UGB ≥ 100 MHz
iv) Differential output Swing ≥ 3.5 V
Q46. Design a two-stage Fully-Differential OTA (Folded Cascode [Differential amplifier + common gate
stage] + gain stage).
a) Analog schematic for OTA.

i) UGB ≥ 400 MHz
ii) Phase margin ≈ 550 - 650
iii) Output voltage swing differential ≈ 3V
c) Show the biasing circuitry to bias all the voltages in your design (except the input).
phase, ICMR plot, slew rate, Differential Output Swing (dc + Transient), power consumption,
Q47. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common gate

i) Gain ≥ 80 dB
iii) Power dissipation ≤ 0.5mA

i) DC Gain (Open Loop) ≥ 100 dB
ii) UGB ≥ 100MHz
iii) Phase margin ≈ 550 - 650
stage] + gain stage) for the following specifications;
i) DC gain (Open Loop) ≥ 120 dB
ii) Differential Output swing ≥ 2.5V
Q50. Design a instrumentation amplifier for the following specifications;
ii) CMRR>= 120dB
ii) input resolution =< 1uV
c) Calculate and plot the following parameters for your amplifier : DC gain, Bode plot for AC gain
and phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power
Q51. Design an instrumentation amplifier for the following specifications;
ii) CMRR>= 140dB
ii) input resolution =< 0.1V
c) Calculate and plot the following parameters for your amplifier : DC gain, Bode plot for AC gain
and phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power
Q52. Design a folded cascode operational amplifier for the following specifications;
ii) slew rate 20V/ µsec
c) Calculate and plot the following parameters for your amplifier : slew rate plot for step input of 1
V, DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing
Q53. Design a 2 stage cmos operational amplifier with frequency compensation using common gate
amplifier for the following specifications;
ii) -3dB frequency >= 50MHz.
Q54. Design a 2 stage cmos operational amplifier , in series shunt feedback, with R-C frequency
compensation for the following specifications;
i) DC gain (closed Loop) ≥ 50
ii) -3dB frequency >= 100MHz.
Q55. Design a 2 stage cmos operational amplifier , in series-series feedback, with R-C frequency
i) gain 'Gm' (closed Loop) ≥ 20 mho
ii) -3dB frequency >= 70 MHz.

i) Open loop gain(DC gain) ≥ 90 dB with slew rate>= 1V/usec
power consumption.
and spectre simulation of circuit for the following specifications. i) Open loop gain(DC gain) ≥ 95
dB ii) Output voltage swing ≥ 3V
phase, CMRR PLOT, PSRR PLOT, ICMR plot, slew rate, Output voltage swing differential (dc +
Q58. Design a two-stage CMOS OPAMP as shown in figure shown ;

derivation of all transistors W/L ratios and spectre simulation of
circuit for the following specifications.
iv) slew rate >= 10V/usec
b) Show a biasing circuitry to bias all the voltages in your design
(except the input).
c) Calculate and plot the following parameters for your OPAMP: DC
gain, Bode plot for AC gain and phase, ICMR plot, slew rate,
Differential Output voltage swing (dc + Transient), power consumption, and input and output
offset voltage.
Q59. Design a 2 stage cmos operational amplifier , in shunt-shunt feedback, with R-C frequency
i) current gain (closed Loop) ≥ 25
Q60. Design a folded cascode operational amplifier , in series-shunt feedback, with R-C frequency
i) voltage gain (closed Loop) ≥ 50
Q61. Design a folded cascode operational amplifier , in series-series feedback, with R-C frequency
i) trans conductance gain (closed Loop) ≥ 30
Q62. Design a two-stage Fully-Differential [ Differential amplifier + Differential amplifier ] for the
following specifications;
i) DC voltage gain (Open Loop) ≥ 90 dB
ii) Differential Output swing ≥ 2V
Q63.
specification
i) Gain ≥ 120 dB
iii) Output swing ≥ 1.5V
d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC
gain and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc +
Q65. Design a programmable variable gain amplifier (VGA) using a Single-ended output Folded Cascode
OTA. The voltage gain should vary from 20 to 100
a) Analog schematic for OTA and VGA

---DC Gain ≥ 100 dB
----Phase margin ≈ 600
---- UGB>= 40 MHz
d) Use POLE ZERO analysis to measure the closed loop gain and phase margin.
Q66. Design a (low power) integrator using telescopic OPAMP as shown in figure in subthreshold
region;

b) Open loop gain(DC gain) ≥ 800 dB with slew rate>=
80V/usec
c) UGB>= 50MHz
d) Power consumption=< 3uW
e) Show a biasing circuitry to bias all the voltages in your
f) Also, calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
power consumption.
Q67. Design a differentiator circuit using telescopic OPAMP as shown in figure;

i) Open loop gain(DC gain) ≥ 80 dB with slew rate>=
20V/usec
c) Also, calculate the following parameters for your OPAMP:
Bode plot for AC gain and phase margin, slew rate, ICMR,
Differential output swing (dc + Transient), input offset
voltage and power consumption.
Q68. Design a first order low pass filter (for frequency fo= 20kHz) using two stage single-ended output
OPAMP (Folded Cascode [Differential amplifier + common gate stage] + gain stage) for the following
specification
ratios and simulation of circuit for the following specifications.
i) Gain ≥ 100 dB
ii) UGB ≥ 50 MHz
c) Use POLE ZERO analysis to measure the closed loop gain and phase margin.
d) Calculate the following parameters for your OPAMP: DC gain, Bode plot for AC gain and phase,
CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power
Q69. Design a unity gain buffer using folded Cascode
OPAMP as shown in figure;

i) DC Gain ≥ 100dB
ii) 3dB frequency---- 30MHz
iii) slew rate—50V/usec
Show a biasing circuitry to bias all the voltages in your design
(except the input).
specification
i) Gain ≥ 80 dB
ii) power dissipation ≤ .2mW
specification
i) Gain ≥ 100 dB
ii) PSRR ≤ 120 dB
iii) Output swing ≥ 1.5V
specification
i) CMRR ≥ 150 dB
ii) PSRR ≤ 150 dB
Q73. Design a two stage single-ended output OPAMP (Folded Cascode[Differential amplifier +
common gate stage] + gain stage) for the following specification
i) Gain ≥ 90 dB
ii) UGB ≥ 100 MHz
i) Gain ≥ 120 dB
i) Gain ≥ 80 dB
ii) power dissipation ≤ .2mW
Q76. Design a two-stage CMOS OPAMP as shown in figure;

ii) UGB ≥ 200 MHz
iv) Differential Output Swing ≥ 4.5V
OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Differential Output
voltage swing (dc + Transient), power consumption, and input and output offset voltage.
Q77. Design a two-stage CMOS OPAMP as shown in figure;

specifications.
c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain
and phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

ii) UGB ≥ 200 MHz
iv) Slew rate ≈ 100 V/µs

i) CMRR ≥ 120dB
ii) PSRR ≥ 120dB

ii) UGB ≥ 600 MHz
Q81. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;
and spectre simulation of circuit for the
following specifications.

ii) UGB ≥ 200 MHz
iv) ICMR ≥ 2 V

systematic derivation of all transistors W/L ratios
and spectre simulation of circuit for the following
specifications.

ii) UGB ≥ 100 MHz
iv) CMRR ≥ 150dB
b) Show a biasing circuitry to bias all the voltages
in your design (except the input).

specifications.

iii) output swing ≥ 1.4V
iv) power consumption ≤ 700 µW
c) Use STB analysis to measure the closed loop gain
and phase margin.
Q84. Design a wide Swing Folded-Cascode CMOS OTA as

shown in figure below;

iii) PSRR ≥ 120 dB
iv) ICMR ≥ 150dB
Q85. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure below;

specifications.

ii) slew rate ≤ 100V/µs
iii) settling time ≤ 50ns
iv) Phase margin ≈ 600
v) ICMR ≥ 2.2 V

specifications.

ii) UGB ≥ 100MHz
iii) slew rate ≤ 50V/µs
iv) Phase margin ≈ 600
v) settling time ≤ 10ns

specifications.

iv) Output Offset ≤ 100mV
b) Show a biasing circuitry to bias all the voltages
in your design (except the input).
+ Transient), power consumption, and input and output offset voltage
Q88. Design a two stage single-ended output OPAMP(differential +gain stage) for the following
specification
ii) UGB ≥ 400MHz
iv) PSRR ≥ 120dB
v) Output offset voltage ≤ 40mV
Q89. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following
specification
ii) Power dissipation ≤ 0.5mW
iii) Settling time ≤ 60ns
Q90. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage) for
the following specification.
ii) Output voltage swing ≥ 1.5V
Q91. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage) for
the following specification
ii) UGB ≥ 300MHz
Q92. a two stage single-ended output OPAMP (Differential stage + a cascode second stage) for the
following specification
i) CMRR ≥ 150 dB
ii) PSRR ≥ 140 dB
Q93. Design a non inverting amplifier with a voltage gain of 20. Use two-stage Fully-Differential OTA
(Folded Cascode [Differential amplifier + common gate stage] + gain stage) for implementation
c) Analog schematic for OTA.

d) Analysis of all equations for OTA, with a systematic derivation of all transistors W/L ratios and
iv) Open loop gain 100 dB
v) UGB ≥ 500 MHz
vi) Phase margin ≈ 550 - 650
vii) Output voltage swing differential ≈ 2V
phase, ICMR plot, slew rate, Differential Output Swing (dc + Transient), power consumption,
Q94. Design low pass filter with cut off frequency of 1M Hz. Use a CMOS OPAMP as shown in Ques
77 ;
viii) Open loop gain(DC gain) ≥ 100 dB
ix) Phase margin ≈ 450
x) power dissipation ≤ 1mW
xi) slew rate >= 40 V/usec
Q95. Design Wein bridge oscillator to generate a square wave of frequency of 1MHz. Use a CMOS
OPAMP as shown in Ques 58 ;
-- Open loop gain(DC gain) ≥ 120 dB
--Phase margin ≈ 450
--power dissipation ≤ 1mW
--slew rate >= 40 V/usec
-- UGB >= 100MHz
Q96. Design a Gm-C low pass filter to generate a cut off frequency of 10MHz. Use a CMOS OPAMP
as shown in Ques 60 ;
-- Open loop gain(DC gain) ≥ 120 dB
--Phase margin ≈ 450
--power dissipation ≤ 1mW
--slew rate >= 40 V/usec
-- UGB >= 100MHz
d) Analysis of all equations of your design, with a systematic derivation of all transistors W/L
ii) power dissipation ≤ 10 uW. You may use some transistors operating in subthreshold region.
e) Show a biasing circuitry to bias all the voltages in your design (except the input).
f) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
power consumption.
Q97. Design a low power sum/ difference amplifier using telescopic OPAMP as shown in figure in
subthreshold region;
g) Analysis of all equations of your design, with a

specifications.
h) Open loop gain(DC gain) ≥ 100 dB with slew rate>=
100V/usec
i) UGB>= 60MHz
j) Power consumption=< 1uW
k) Show a biasing circuitry to bias all the voltages in your design (except the input).
l) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase
power consumption.
Q98. Design an integrator using a two-stage OTA (Folded Cascode[Differential amplifier + common
gate stage] + gain stage) for the following specifications;
ii) Differential Output swing ≥ 3V
iii) UGB >= 50 MHz
Q99. Design a low power comparator using two stage differential output OPAMP (Telescopic + gain
stage) for the following specification
i) open loop gain ≥ 120 dB
ii) UGB >= 100 M Hz
xi) input offset =< 1uV
xii) power dissipation =< 10uW
Q100. Design a low noise fully differential operational amplifier using a folded cascade OPAMP.
Compare the SNR value of your design with / without the tail current source

Analysis of all equations of your design, with a systematic derivation of all transistors W/L ratios and
ii) CMRR>=150 dB,
iii) PSRR >= 100dB
ii) UGB ≥ 100 MHz
phase, ICMR plot, output noise, SNR, slew rate, Output voltage swing differential (dc +
Transient), power consumption, and input and output offset voltage
Q101. Design an astable multivibrator at 10 KHz frequency using folded Cascode OPAMP as shown in
figure;

specifications.
i) open loop voltage gain >= 80 dB
ii)Differential Voltage Swing ≥ 3V
iii) ICMR ≥ 2.5V
iv) power dissipation ≤0.01mW
b) plot the multivibrator output waveform
phase, ICMR plot, Slew rate, Output voltage swing differential (dc + Transient), power consumption,
Q102. Design a programmable variable gain amplifier (VGA) using a Single-ended output Folded
Cascode OTA. The voltage gain should vary from 10 to 50
a) Analog schematic for OTA and VGA

---DC Gain ≥ 100 dB
----Phase margin ≈ 550
---- UGB>= 50 MHz
Q103. Design a folded Cascode OPAMP as shown in figure

(b) for design of precision full wave rectifier shown in (a)
to convert 2V , 10 KHz Hz ac input sinusoid into dc
voltage.
(b
)
(a)
a) Analysis of all equations of your design, with a systematic derivation of all transistors
W/L ratios and spectre simulation of circuit for the following specifications.
iii) ICMR ≥ 2.5V
phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption, and
input and output offset voltage
Go to next page
Common Simulations
The following simulations need to be done for all classes of circuits:
1. Performance Evaluation at:
VDD+10%, FF Corner, Minimum Resistance Corner, 00C

VDD-10%, SS Corner, Maximum Resistance Corner, 1000C
Submission Dates
Assignment / Detailed Report Submission 15th November, 2022

Evaluation of the Assignment Shall be notified
Late assignment submission penalty ---5 marks
No submission through email
Kindly prepare your report as per following format----------------
Report Submission---
First page of report should contain name/ id of all team members
A detailed report should be submitted with following sections—
 Problem statement and specifications
 Schematic of your design

 Table containing (w/L) of each transistor
 Table showing DC current in all transistors/, and DC voltages at each node
 Results – ( each result with snapshot e.g Gain result with its labelled simulation BODE
plot snapshot)
 Conclusion--- (all results obtained in Tabular format along with a column giving
specification values)
 Problems faced during the design
 Innovation in the design ( some design innovation, you have thought on your own)
SAVE YOUR REPORT AS (PROBLEM_XX. PDF ) (EXAMPLE--- PROBLEM_55.PDF)
-------------------------------End---------------------------------------

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Analog Design Assignment

Analog & Digital VLSI Design EEE/ INSTR F 313

For students using cadence---

 Library for circuit simulation is with Sections TT_3V, FF_3V, SS_3V

 Problem statement and specifications

First page of report should contain name/ id of all team members

SAVE YOUR REPORT AS (PROBLEM_XX. PDF ) (EXAMPLE--- PROBLEM_55.PDF)

Suggested Design Procedure

iv) Open loop gain(DC gain) ≥ 80 dB

Q5. Design a CMOS OPAMP.

a) Analog schematic for the above model

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

a) Analog schematic for the above model

Q13. Design a CMOS OPAMP.

a) Analog schematic for the above model

Q14. Design a CMOS OPAMP.

Q15. Design a CMOS OPAMP.

a) Analog schematic for the above model

a) Analog schematic for OTA

a) Analog schematic for OTA

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

Q30. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q31. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q32. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q33. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q34. Design a folded Cascode OPAMP as shown in

a) Analysis of all equations of your design, with a

Q35. Design a folded Cascode OPAMP as shown in

a) Analysis of all equations of your design, with a

Q36. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q37. Design a folded Cascode OPAMP as shown in figure;

d) Analysis of all equations of your design, with a

a) Analysis of all equations of your design, with a systematic

Q39. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

Q40. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a systematic

a) Design a high swing telescopic OPAMP.

a) Design a high swing telescopic OPAMP.

a) Analog schematic for OTA.

a) Analog schematic for OTA.

a) Analog schematic for OTA.

Q50. Design a instrumentation amplifier for the following specifications;

Q51. Design an instrumentation amplifier for the following specifications;

Q56. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

a) Analysis of all equations of your design, with a systematic

a) Analog schematic for OTA and VGA

a) Analysis of all equations of your design, with a

a) Analysis of all equations of your design, with a

a) Analysis of all equations of your design, with a

Q76. Design a two-stage CMOS OPAMP as shown in figure;