ELL735: Analog Integrated Circuits

Design Project Handout (Fall 2022)

The project involves the design of fully differential two stage operational transconductance
amplifier (OTA).

Voutp Vinp Vinm Voutm

Fig. 1 Fully differential two stage OTA

• Fully differential two stage operational transconductance (OTA)

• Design the bias circuit
• Design the compensation circuit for stability
• Design the CMFB (common mode feedback) circuit
• Differential and common mode stability check using simulations
• Use it to implement any biquadratic filter
Some example specifications:

Specifications Specifications
Technology Power
Supply CMRR
Load capacitance (CL) PSRR
Input common mode range (ICMR) THD (Total harmonic distortion)
Output common mode range (OCMR) FOM (small signal) = (GBW*Cload)/Power
DC Gain (Open loop) FOM (large signal) = (SR*Cload)/Power
Gain bandwidth product (GBW) Gain margin
Input referred noise I_ota
Slew rate (SR) I_bias
Phase margin Settling time (0.1% accuracy)
CAD options: Cadence Virtuoso (≤65nm), LTSpice (40nm models will be provided)

Interim project report [Marks=20]: Your Interim project report should have theoretical analysis
of your operational amplifier. You should have a comprehensive list of specifications of your block
with desired target. Try to be a little aggressive in your specifications. It is possible that you are
unable to meet specifications in the final design and in that case do include an explanation in your
final report. You may do preliminary circuit simulations to fill your achieved specification targets,
however, this is optional. Include all references.

Final project report [Marks=80]: The final project report should be a comprehensive report with
theoretical analysis of the circuit and full specification table supported with all simulation results.
The report should include simulation plots for different specifications. Discuss the major design
tradeoffs associated with the specifications. In case you are unable to meet design specifications,
justify and explain the constraints. Update your references if needed.

Note:
1) Projects must be done individually.
2) Due date for Interim report : 10th October
3) Due date for Final report : 15th November

References:

Journals:

IEEE Journal of Solid-State Circuits (JSSC)

IEEE Transactions on Circuits and Systems I (TCAS I)
IEEE Transactions on Circuits and Systems II (TCAS II)