Chapter 8: Combinational Logic Modules

Chapter 8: Combinational Logic

Modules

Prof. Ming-Bo Lin

Department of Electronic Engineering

National Taiwan University of Science and Technology

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-1
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-2
 Chapter 8: Combinational Logic Modules

Objectives
After completing this chapter, you will be able to:
Understand the features of decoders
Understand the features of encoders
Understand the features of priority encoders
Understand the features of multiplexers
Understand the features of demultiplexers
Describe how to design comparators and
magnitude comparators
Describe how to design a parameterized module

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-3
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-4
 Chapter 8: Combinational Logic Modules

Basic Combinational Logic Modules

Decoder
Encoder
Multiplexer
Demultiplexer
Comparator
Adder (CLA)
Subtracter (subtractor)
Multiplier -
PLA
Parity Generator
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-5
 Chapter 8: Combinational Logic Modules

Options for Modeling Combinational Logic

Verilog HDL primitives
Continuous assignment
Behavioral statement
Functions
Task without delay or event control
Combinational UDP
Interconnected combinational logic modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-6
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-7
 Chapter 8: Combinational Logic Modules

Decoder Block Diagrams

n-to-m decoders

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-8
 Chapter 8: Combinational Logic Modules

A 2-to-4 Decoder Example

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-9
 Chapter 8: Combinational Logic Modules

A 2-to-4 Decoder Example

// a 2-to-4 decoder with active low output

always @(x or enable_n)
if (enable_n) y = 4'b1111; else [0]

case (x) y28

x[1:0]
[1:0] [1]

un1_y28
2'b00 : y = 4'b1110;
2'b01 : y = 4'b1101; enable
1111
0
[3:0] [3:0]
y[3:0]
2'b10 : y = 4'b1011; [1]
[0]
1
y[3:0]
2'b11 : y = 4'b0111; y27 un1_y27

endcase [0]
[1]

y26 un1_y26

[0]
[1]

y25 un1_y25

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-10
 Chapter 8: Combinational Logic Modules

A 2-to-4 Decoder with Enable Control

// a 2-to-4 decoder with active-high output
always @(x or enable)
if (!enable) y = 4'b0000; else [0]

case (x) x[1:0]

y28
[1:0] [1]

2'b00 : y = 4'b0001;
enable
2'b01 : y = 4'b0010; 0000
0
[3:0] [3:0]
y[3:0]
2'b10 : y = 4'b0100; [1]
[0]
1
y[3:0]
2'b11 : y = 4'b1000; y27

endcase
[0]
[1]

y26

[0]
[1]

y25

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-11
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-12
 Chapter 8: Combinational Logic Modules

Encoder Block Diagrams

m-to-n encoders

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-13
 Chapter 8: Combinational Logic Modules

A 4-to-2 Encoder Example

Q: What is the problem of this encoder?

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-14
 Chapter 8: Combinational Logic Modules

A 4-to-2 Encoder Example

// a 4-to-2 encoder using if ... else structure [0]
[1]

always @(in) begin

[2]
[3:0] [3]
in[3:0]
y22
if (in == 4'b0001) y = 0; else
if (in == 4'b0010) y = 1; else e

if (in == 4'b0100) y = 2; else

[1] 00
d
[0]
[2] e
01

if (in == 4'b1000) y = 3; else

[3] d [1:0] [1:0]
y[1:0]
e
y23 10
d
y = 2'bx; 11
e
d

end y[1:0]
[2]
[0]
[1]
[3]

y24

[3]
[0]
[1]
[2]

y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-15
 Chapter 8: Combinational Logic Modules

Another 4-to-2 Encoder Example

// a 4-to-2 encoder using case structure

[0]
[1]
[2]

always @(in)
[3:0] [3]
in[3:0]
y22
case (in)
4'b0001 : y = 0; [1] 00
e
d

4'b0010 : y = 1;
[0]
[2] e
01
[3] d [1:0] [1:0]
y[1:0]

4'b0100 : y = 2; y23 10
e
d

4'b1000 : y = 3;
e
11
d

y[1:0]
default : y = 2'bx; [2]
[0]

endcase [1]
[3]

y24

[3]
[0]
[1]
[2]

y25

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-16
 Chapter 8: Combinational Logic Modules

A 4-to-2 Priority Encoder

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-17
 Chapter 8: Combinational Logic Modules

A 4-to-2 Priority Encoder Example

// using if ... else structure y[1:0]

assign valid_in = |in;

always @(in) begin [0]
[1]
valid_in
[2]

if (in[3]) y = 3; else [3]

valid_in
if (in[2]) y = 2; else [2]
[3]

if (in[1]) y = 1; else y23

if (in[0]) y = 0; else
[3]
e
1
d
e

y = 2'bx; [1]
0

1
d
e

end
d
y24 e
0
d

y_1[0]

[0]
[1]
[2]
[3:0] [3]
in[3:0]
un1_in_3 y25
un1_in_1

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-18
 Chapter 8: Combinational Logic Modules

Another 4-to-2 Priority Encoder Example

// using casex structure [0]

assign valid_in = |in;

[1]
[2] valid_in
[3]

always @(in) casex (in) valid_in

4'b1xxx: y = 3; in[3:0]
[3:0]
[2]
[3]

4'b01xx: y = 2; y23[0]

4'b001x: y = 1; [3]
11
e

4'b0001: y = 0; d
e
10

default: y = 2'bx; [1]

[2]
d
e
[1:0] [1:0]
y[1:0]
[3] 01
endcase y24[0]
d
e
00
d

y[1:0]

[0]
[1]
[2]
[3]

y25
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-19
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-20
 Chapter 8: Combinational Logic Modules

Multiplexer Block Diagrams

m-to-1 ( m = 2n ) multiplexers

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-21
 Chapter 8: Combinational Logic Modules

A 4-to-1 Multiplexer Example

Gate-based 4-to-1 multiplexers

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-22
 Chapter 8: Combinational Logic Modules

An n-bit 4-to-1 Multiplexer Example

// an N-bit 4-to-1 multiplexer using conditional operator
parameter N = 4; //
input [1:0] select; select[1:0]
[1:0]
[0]
[1]

input [N-1:0] in3, in2, in1, in0; un1_select_2

output [N-1:0] y; in3[3:0]

[3:0]

assign y = select[1] ? [1]

[3:0]
e
d

(select[0] ? in3 : in2) : un1_select_3

[0]
[3:0]
e
d [3:0] [3:0]
y[3:0]

(select[0] ? in1 : in0) ;

e
[3:0]
[3:0] d
in1[3:0]
[3:0]
in2[3:0] e
[3:0] [3:0]
in0[3:0] d

y[3:0]
[0]
[1]

un1_select_4

[0]
[1]

un1_select_5

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-23
 Chapter 8: Combinational Logic Modules

The Second n-bit 4-to- 1 Multiplexer Example

// an N-bit 4-to-1 multiplexer with enable control

parameter N = 4;
input [1:0] select;
input enable;
input [N-1:0] in3, in2, in1, in0;
output reg [N-1:0] y;

always @(select or enable or in0 or in1 or in2 or in3)

if (!enable) y = {N{1b0}};
else y = select[1] ?
(select[0] ? in3 : in2) :
(select[0] ? in1 : in0) ;

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-24
 Chapter 8: Combinational Logic Modules

The Third n-bit 4-to- 1 Multiplexer Example

// an N-bit 4-to-1 multiplexer using case structure
parameter N = 8;
input [1:0] select; select[1:0]
[1:0]
[0]
[1]

input [N-1:0] in3, in2, in1, in0; un1_select_2

output reg [N-1:0] y; in3[7:0]

[7:0]

always @(*) [1]

[7:0]
e
d

case (select) un1_select_3

[0]
[7:0]
e
d [7:0] [7:0]
y[7:0]

2b11: y = in3 ;
e
[7:0]
[7:0] d
in1[7:0]
[7:0]
in2[7:0] e
2b10: y = in2 ; in0[7:0]
[7:0] [7:0]
d

y[7:0]
2b01: y = in1 ; [0]
[1]

2b00: y = in0 ; un1_select_4

endcase [0]
[1]

un1_select_5

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-25
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-26
 Chapter 8: Combinational Logic Modules

DeMultiplexer Block Diagrams

1-to-m ( m = 2n ) demultiplexers

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-27
 Chapter 8: Combinational Logic Modules

A 1-to-4 DeMultiplexer Example

Gate-based 1-to-4 demultiplexers

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-28
 Chapter 8: Combinational Logic Modules

An n-bit 1-to-4 DeMultiplexer Example

// an N-bit 1-to-4 demultiplexer using if ... else structure
parameter N = 4; // default width
input [1:0] select; [0]

input [N-1:0] in; select[1:0]

[1:0] [1]

y37
0000
0
[3:0] [3:0]
y3[3:0]

output reg [N-1:0] y3, y2, y1, y0;

[3:0]
1
y3[3:0]

[1]
[0]

always @(select or in) begin y27

0000

[3:0]
0

1
[3:0] [3:0]
y2[3:0]

if (select == 3) y3 = in; else y3 = {N{1'b0}}; y2[3:0]

if (select == 2) y2 = in; else y2 = {N{1'b0}}; [0]

[1]

if (select == 1) y1 = in; else y1 = {N{1'b0}};

0000
0
y17 [3:0] [3:0]
y1[3:0]
[3:0]
[3:0] 1
in[3:0]

if (select == 0) y0 = in; else y0 = {N{1'b0}};

y1[3:0]

end [0]
[1]
0000
0
y07 [3:0] [3:0]
y0[3:0]
[3:0]
1
y0[3:0]

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-29
 Chapter 8: Combinational Logic Modules

The Second n-bit 1-to-4 DeMultiplexer Example

// an N-bit 1-to-4 demultiplexer with enable control
parameter N = 4; // Default width

output reg [N-1:0] y3, y2, y1, y0;
always @(select or in or enable) begin
if (enable)begin
if (select == 3) y3 = in; else y3 = {N{1'b0}};
if (select == 2) y2 = in; else y2 = {N{1'b0}};
if (select == 1) y1 = in; else y1 = {N{1'b0}};
if (select == 0) y0 = in; else y0 = {N{1'b0}};
end else begin
y3 = {N{1'b0}}; y2 = {N{1'b0}}; y1 = {N{1'b0}}; y0 = {N{1'b0}}; end
end

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-30
 Chapter 8: Combinational Logic Modules

Syllabus
Objectives
Fundamentals of combinational logic modules
Decoders
Encoders
Multiplexers
Demultiplexers
Comparators

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-31
 Chapter 8: Combinational Logic Modules

Comparators
A 4-bit comparator

A 4-bit cascadable comparator block diagram

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-32
 Chapter 8: Combinational Logic Modules

Types of Comparators
Comparator
Cascadable comparator

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-33
 Chapter 8: Combinational Logic Modules

Comparators
An 8-bit comparator

Q: What will happen if you set the input value (010) at

the rightmost end to other values?

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-34
 Chapter 8: Combinational Logic Modules

A Simple Comparator Example

// an N-bit comparator module example
parameter N = 4; // default size
input [N-1:0] a, b;
output cgt, clt, ceq; [3:0] [3:0]
a[3:0]
[3:0] [3:0]
= ceq
b[3:0]
assign cgt = (a > b); ceq
assign clt = (a < b); [3:0]

assign ceq = (a == b); [3:0]

< cgt

cgt

[3:0]

[3:0]
< clt

clt

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-35
 Chapter 8: Combinational Logic Modules

A Cascadable Comparator Example

Iaeqb
[3:0]
Oaeqb
[3:0]
<
Oaeqb
un1_Oagtb

[3:0] [3:0]
a[3:0]
parameter N = 4; b[3:0]
[3:0] [3:0]
= Oagtb

un1_Oaeqb Oagtb
// I/O port declarations Iagtb
un2_Oagtb

input Iagtb, Iaeqb, Ialtb; [3:0]

[3:0]
< Oaltb

input [N-1:0] a, b; un1_Oaltb Oaltb

output Oagtb, Oaeqb, Oaltb;

Ialtb
un2_Oaltb

// dataflow modeling using relation operators

assign Oaeqb = (a == b) && (Iaeqb == 1); // =
assign Oagtb = (a > b) || ((a == b)&& (Iagtb == 1)); // >
assign Oaltb = (a < b) || ((a == b)&& (Ialtb == 1)); // <
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 8-36