NCSU Paul Franzon FlipFlops PDF

ECE 733 Class Notes
Latches and Flip-Flops

Dr. Paul D. Franzon
Outline
Design Goals
Basic Latches and Flip-flops
Optimizing Timing
Single Sided Designs
Differential Designs
Some comparisons
References
Dally & Poulton, Chapters 4, 12.1
Kang & Leblecici, Chs 8-9
Bernstein, Ch. 5
2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 1

ECE 733 Class Notes
Objectives and Motivation

Objectives:
Understand design goals and tradeoffs in flip-flops and how they are
measured
Be able to describe operation of a wide range of flips and recognize how the
roles of individual transistors determine operation
Motivation
Most complex high-speed digital circuit
Constrains performance of logic and I/O

ECE 733 Class Notes
D Q Revision
Ck
Ck
tSetUp thold
D-Latch:
level-sensitive D
tclock-Q
Tracks data while clock high
Q taperture
Stores data while clock low
D-Flip-flop
edge-sensitive Ck
tSetUp thold
Stores data on clock edge
D
tclock-Q
Q taperture
tD-Q

ECE 733 Class Notes
Edge-Triggered Flip-Flops
Created from latches:
Two styles:

ECE 733 Class Notes
Goals of Flip-Flop Design

Timing and Clock Speed:
tclock tck Q max tlog ic max t setup t skew max
Logic
clock
skew
Goal:
Minimize tDQ=tCk-Q + tsetup

ECE 733 Class Notes
Goals
Timing Closure:
Ability to withstand max-min process and
temperature variations depends on how
much of the clock-period is taken up by Register Register
setup and hold times Q1
D1 Comb D2
Goal: Logic Q2
Constrains maximum taperture = tsetup+thold tLogic-delay
clock
clock
+/-tskew
tset-up
tskew thold tskew
clock
D2
tck-Q-max + tlogic-max tck-Q-min-tlogic-min

ECE 733 Class Notes
Goals of flip-flop design

Timing Related:
To get fastest clock period:
Minimize tD-Q =t_su + t_ck-Q
soft clock edge
NOT (or reduce) propagate clock skew to Q
Removes or reduces impact of tskew on clock period
clock clock
skew skew
D D
Q Q
Note : Latches have this property for signals that arrive after clock
rising edge!
Incorporate logic into flip-flop
And remove from before/after flip-flop

ECE 733 Class Notes

Timing Related:
Be able to drive good loads
Typical fan-out: 2-8 FO4 inputs (50 200 fF in 0.18 m)
Minimum susceptibility to clock slope (edge rate)
Most FFs have an max rise/fall time specification

ECE 733 Class Notes

Power Related
Minimize internal power
Minimize clock load
Note : Speed-power tradeoff
Can design to minimize Power.Delay or Energy.Delay Product
Measured in fJ gives minimum energy per transition (and energy-delay

product for constant fclock)
Bit Error Rate Related
Minimize suceptibility to:
Noise on clocks or signals (e.g. due to crosstalk)
Clock edge rate variations
Charge-sharing failures
Charge leakage failures, including alpha particle strikes
Power & ground noise
Other
Facilitate test and debug (Be static & scannable)

ECE 733 Class Notes
Flip-Flop Basics
Generic Flip-Flop:
Sampler storage Output
Static: Dynamic:
etc.
Sampling Stage:
Must ensure input is sampled for both high and low D
Fastest if no DC path from Vdd to Gnd during sampling
Output Stage:
Drives load without disrupting stored state

ECE 733 Class Notes
Basic Bistable Static Storage Element

V1
Cross-coupled inverter pair V1
V2 V1
V3 V2
V3 V1
Inverter loaded with Stable operating point
itself:
Regenerative feedback Unstable (high gain)
Stable operating point
V2 V1 Qualitative View: V2
Energy
V2
ECE 733 Class Notes
Noise Margin
Add noise at one input: V1 Assume nominal V2 =1
V2 V1
Vn
V1
Size of boxes V2
V1 Small Vn
determine NMs
High gain no longer stable
V2
Unity gain
V2
Large Vn
ECE 733 Class Notes
Can replace
Basic Latches INV with logic
To store a logic level (change state): D Q
Must overcome the potential hill
between two stable states
Some Methods:
Use Transmission gates to break feedback Clk
path
D-latch
Break supply current path (RS latch)

Reset/Set
Q Q
D latch:
S R
D
Q
clk R Q
Q
NOR RS latch
S Q

ECE 733 Class Notes
Latch Basics
Other Methods To Change State:
p2
Directly over-powering regenerative p1
feedback in storage cell Q Q

Must generate a negative noise margin D D
by the write (clk=high) n1 n3 n4 n5
In this case: clk clk
Sizes p1, p2 = 2 m / 0.35 m n2 n6
Sizes n3, n4 = 3 m / 0.35 m
Sizes n1, n2, n5, n6 = 5 m / 0.35 m V1

provides sufficient write margin RH inverter (D=0)
LH inverter (D=1)
Negative Voltage Margin

Write
V2

ECE 733 Class Notes
Revision: Flip-flop Design Goals

Timing: t clock t ck Q max t log ic max t setup max t skew max
Logic
clock
skew
Goals :
Minimize tDQ = tclock-Q + tSU
Constrain upper limt for taperture = tsetup + thold

ECE 733 Class Notes
Timing
tclock-Q
Tradeoff between tclock-Q and tsu / thold:
thold
tSU
clock
D
Q
Why? Q
X
Smaller tSU VX smaller
D -Amplification Voltage growth exponential with time
VQe-t/
clk Amplifier delay increases exponentially with decreasing
tSU (I.E. with smaller Vx)
Q metastable during amplification

ECE 733 Class Notes
Doing this in Project

Illustrate for D: 0 1 transition:
Conservative tsu: Aggressive tsu: Failure:
Clock
tsu tck-Q tsu tck-Q <tsu
One point on Another point Failure!

curve on previous page NOT a valid tsu
Reminder: Goal most likely to minimize tDQ, not tsu

ECE 733 Class Notes
Project Characterization
T_hold
Failure: Good:
Ck Ck
D D
Q Q
<thold thold
Failure! Good! (NO change in Q due to D)

NOT a valid thold thold

ECE 733 Class Notes
Timing
Objective : Minimize tD-Q = tSU + tclock-Q
Often results in negative setup time
tSU
clock
D Forbidden
Q
tD-Q 400
tclock-Q
tD-Q 350
(ps)
300
250 -60 -40 -20 0 20 40 60 80

e.g. strong-ARM flip-flop tSU(ps)

ECE 733 Class Notes
Other Timing Parameters

Hold period:
Hold
Forbidden
tSU 400
clock 350
D
300
Hold period
(no transitions 250 -80 -60 -40 -20 0 20 40 60 80 tSU(ps)
allowed)

ECE 733 Class Notes
Other Timing Parameters

Effect of clock edge rate
Flip-flop timing can be sensitive to clock edge rate (slope)
Can cause race-through in Master-Slave
e.g. pass-gate FF:
Q
D Q
T1
clk Vinv
Vt
T2
clk Vt
Clk
T2 open T1 open Clk
Problem if T2 open longer than Tinv-delay past this time

ECE 733 Class Notes
Latches Flip-Flops Characterized

Single-Sided
C2MOS
TSPC
Transmission Gate
Double-Sided (complementary or differential)
DCVS
Single Transistor Clock
Hybrid Latch Flip-flop
Semi Dynamic Flip-flop
Sense Amp Flip Flop
K6 Flip Flop
Comparisons

ECE 733 Class Notes
Common Questions
How is the signal sampled on the clock 0 1 transition?
What determines:
tsetup ?
thold ?
tck-Q ?
How is the data stored?
What prevents false transitions from occuring when
D changes after thold ?
When clock goes low ?

ECE 733 Class Notes
C2MOS Flip-Flop
Edge triggered Master-Slave device: Samples while clk Low
Tri-state inverter Samples while clk High
Clock Buffer
Regenerate when clock high

ECE 733 Class Notes
C2MOS Operation
Track (ck = 0)
=on
Tracking input Recycling previous value
Track (ck 1)
Holding sampled value Sampling input

ECE 733 Class Notes
Timing
What determines t_setup and t_hold?
clk
ckb
ck
D can not change during this interval
tsu
t_hold
What determines t_clock-Q?
Clock buffer delay + delay through second tri-state buffer

ECE 733 Class Notes
True Single Phase Clocked (TSPC) Latches & Flip-Flops

Based on the following dynamic latches:
Transparent while clock high: When clock low:
D clk D clk
clk D clk D
SN PP SP PP
Note : Only clock is needed, not clock or a second clock phase
True single phase lowest skew in distribution
Make latches and flip-flops by mixing stages.
(Source : Yuang and Svenson)

ECE 733 Class Notes
TSPC Flip Flops

Example:
Positive edge triggered static-input flip flop
SP + SP + SN + SN
D b
clk
a
Observation:
SP stage simply inverts a while clk lo
Not needed if Q OK..
Note, nodes a, b, Q float for part of clock D b Q

period
a
Watch for inadvertant charge sharing
Note can put logic in PU and PD chains
clk

ECE 733 Class Notes
Operation
D=0, clk=0 ck 1
1 0 1
D 1
b Q D x1 b Q
a a
clk clk
Note: a/b floats high or low (x0, x1)
D1, clk=1 (Q should not change)
x0 1
D 0 b Q
a
clk

ECE 733 Class Notes
Operation
D=1, clk=0 ck 1
1 x1 0
D 0
b Q D 0 b Q
a a
clk clk
Note: a/b floats high or low (x0, x1)

D0, clk=1 (Q should not change)
x1 0
D x0 b Q
a
clk

ECE 733 Class Notes
TSPC Issues
Timing:
tclock-Q is very quick
Must have logic between stages to prevent hold violation
Can be sensitive to clock slope (next page)

Has floating nodes during evaluate
Very high clock load

ECE 733 Class Notes
Clock Slope
Example : Sensitivity of TSPC flip-flop: p2
D
b p1
a Q
n1
clk
Possible failure: clock
D remains high b
a low when clock low
Q
p1 off p1 & p2
before p2 on On
Possible Fixes : Reduce Wn1; enforce clock slope rules

ECE 733 Class Notes
Transmission Gate Master-Slave

PowerPC 603
Clock Load
High
Power
Low
low power feedback
Positive setup
TG delay determines t_su INV(s) + TG gate determines t_ck-Q

(first INV only matters if tsu very small)
Q buffer makes timing less sensitive to load variations

ECE 733 Class Notes
Differential Latches and Flip Flops

i.e. Requires both D and D
Conventional Latches and Master-Slave Designs

DCVS
True Single Phase Clocked Latch
DSTC and SSTC
Pulse-triggered Latches:
HLFF
DSFF
SAFF
ETL

ECE 733 Class Notes
Differential Cascode Voltage Switch p1 p2
Variants: Q Q
Static RAM style Latch D D

Operation explained earlier n1 n3 n4 n5
Transparent when clk hi

clk
n2
Simple DCVS:
Latch or flip-flop? Latch
p1 p2
Dynamic or static? Dynamic
Q Q
Susceptibility to charge sharing can be D D

reduced by placing inverters on Q and n1 n5
Q clk clk
n2 n6

ECE 733 Class Notes
DCVS
Combine to make Master-Slave Flip-flop
Better than single-sided flip-flops
Fewer gates than C2MOS
Fully static storage
Smaller clock load
Complementary faster operation
clk
p5
p1 p2
Q Q
p3 p4
n1 n3 n4 n5
D D
n6 n7
clk
n2

ECE 733 Class Notes
Operation
Clock = low:
clk
Master turned on p5
p1 p2
One of n1 or n5 turned on Q Q
p3 p4
Clock high
n1 n3 n4 n5
n1 or n5 overpowers latch
D D
n6 n7
clk
n2
Master Slave
After thold, what prevents a false transition?
If D changes, can NOT result in the off n1 or n5 turning ON, as no PU path in
master
D changing can only result in the on transistor turning OFF: OK as latch has
already stored new value

ECE 733 Class Notes
Operation
Ck=0; D=1
clk p5 p1 p2
Q Q
p3 p4
n1 n3 n4 n5
D D
n6
n7
clk
n2
Master Slave

ECE 733 Class Notes
Operation
Ck1; D=1
clk p5 Float Hi p1 p2
Q Q Q=0
p3 p4
n1 n3 n4 n5
D D
n6
n7
clk
n2
Master Slave

ECE 733 Class Notes
Operation
Ck=1; D0
(expect to see no transition)
clk p5 0 p1 p2
Q Q Q=0
p3 p4
n5 off
n1 n3 n4 n5
D D
n6
n6 off n7
clk
n2
Master Slave

ECE 733 Class Notes
DCVS clk
Variant : Ratio insensitive Latch p4
p3
p5
Removes need to overcome X-coupled D D

latch to change state p1 p2
Q Q
Especially hard to overcome nFETs in
X-coupled inverters
Reduces sensitivity to process n1 n3 n5
n4
variations
p5, p4 ensures Vdd/Gnd path broken
when changing stored state clk
n2
p3 ties the on p1 or p2 to Vdd when
clock is low and latch is holding its
outputs
e.g. 0 held: 0 1 1 0
D has not changed: D has changed:
Vdd path

ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
clk clk
p5
p4 HI p5
p4 HI p3
p3
D D D
D p1 p2
p1 p2
Q Q Q Q=1
Q
n1 n3 n4 n5
n1 n3 n4 n5
clk clk
n2
n2
P3 OFF allows latch state to change easilly

ECE 733 Class Notes
Operation
Ck0; D=1 (latch event) Ck=0; D0 (expect no change)
clk
clk
p4
p3
HI p5
p5
p4 HI p3
D D
D D p1 p2
p2
p1
Q Q Q=1
Q Q Q=1
n1 n3 n4 n5
n1 n3 n4 n5
clk
clk n2
n2
P3 ON means latch data is preserved

ECE 733 Class Notes
DCVS latch with pre-charge

Add pre-charge to increase speed:
Simple Latched Dual Rail Domino structure:
latch pair
clk clk clk clk
Q Q Q Q
D D A A B
clk B
clk
Dynamic D latch with pre-charge
D latch with merged logic

ECE 733 Class Notes
Single Transistor Clocked MS latches

Yuan & Svensson 97
p1 p3
p5 p6
p4
p5 X
n9 n10
p2 p3
p2 p4
n3 n4 n4 n5 n6 n8
n1 n2
n1 n2 n3
(Dynamic) (Semi-static)
Min. sizes. Ensures static
Small clock load; charge sharing issues operation if D changes while
clk high.

ECE 733 Class Notes
operation
Ck=0; D=1 Ck1; D=1
p1 p1
p4 p4
p5 p5
p2 p3 p2 p3
n3 n3
n1 n2 n1 n2

ECE 733 Class Notes
Operation
Ck=1; D->0
p1
p4
p5
p2 p3
n3
n1 n2

ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
p3 p3
p5 p6 p5 p6
Hi
n9 n10 n9 n10
p2 p4 p2 p4
Lo Lo
n4 n5 n6 n8 n4 n5 n6 n8
n1 n2 n3 n1 n2 n3

ECE 733 Class Notes
Operation
Ck=1; D 0
p3
p5 p6
Lo
n9 n10
p2 p4
INV and nFETs it drives n4 n5 n6 n8

help discharge floating node
n1 n2 n3

ECE 733 Class Notes
Pulse-triggered Latch
Principle of Operation:
Hybrid Latch Flip-Flop (HLFF) (AMD, K6, Portovi, 1996)
Clocked Transistors p1 p3
p2 p4
X pre-charged (clock low) n3 X
Pulse samples D onto X n6
Storage
n2 n5
n1 n4
Master Slave
ECE 733 Class Notes
HLFF
Operation: Precharge Precharge
Absorbs skew (clock low) (clock high)
Fully static (retains Q)
Negative setup
p1 p3
Allows cycle stealing p2 p4
Can add logic n1 X
thold c.f. tD-Q n4
Storage
n2 n5
n3 n6
D high D low

ECE 733 Class Notes
HLFF Operation
Basic Structure
p1 p2 p3 p4
Precharge dynamic inverter master
Clock-evaluate inverter slave n1 X n4
Clock Low n2 n5
Precharge X
n3 n6
Clock High
n1 on; n3 on for 3 INV delay
D high X low p4 pulls Q hi
D low X charge shared with n1_S; p2 tsu:
turn on, pulling X high Can be negative
After thold Criteria:
p3 (weak) turns on starts pulling X As long as n2 turns on while n1, n3 Hi
high to help precharge
D : Hi Lo : n2 off : no change as n3 off thold
D : Lo Hi : n2 on : no change as n3 off Determined by:
and p3 keeps X high
time n3 on after optimal tsu point

ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
Q=1
p1 p2 p3 p4 p1 p2 p3 p4
X
n4 n1 n4
n1
n5 n2 n5
n2
n6 n3 n6
n3
= turning off Critical path larger transistors

= turning on

ECE 733 Class Notes
Operation
Ck=1; X precharges Ck=1; D0
Q=1
p1 p2 p3 p4 Q=1 p1 p2weak
p3 p4
X
n4 n1 n4
n1
n5 n2 n5
n2
n6 n3 n6
n3
Precharge helps defines size of weak pull-up

ECE 733 Class Notes
Operation
Ck=0; D=0 Ck1; D=0
Q=0
p1 p2 p3 p4 p1 p2weak
p3 p4
X
n1 n4 n1 n4
n2 n5 n2 n5
n3 n6 n3 n6
Easier transition than 01.
Tsu determined by time for RHS sampler to replace role of LHS sampler if D=1
At clock going high, and then changes to 0 during pulse

ECE 733 Class Notes
Operation
Ck=1; X precharges Ck=1; D1
weak p3 reduces dip in X, as a result of
charge-sharing through n2, making
sure p4 does not turn on
Q=1
p1 p2 p3 p4 Q=1 weak
p1 p2 p3 p4
X
n1 n4 n4
n1
n2 n5 n5
n2
n3 n6 n6
n3
Helps defines size of weak pull-up

ECE 733 Class Notes
HLFF Waveforms
charge share X to nfet n1
p1 p2 p3 p4
n1 n4
n2 n5
n3 n6
Weak p3 pulling X high

ECE 733 Class Notes
Semi-Dynamic Flip Flop

Sun UltraSparc, Klass, VLSI Circuits 98
p1
p2
n1
n4
n2
n5
n3

ECE 733 Class Notes
SDFF
Operation p1
X p2
N1
n1 n4
n2
n5
n3
Clk = low : X precharged to 1, N1 is ON
Clk hi : D=0 : X stays high, N1 on then off, Q pulled down; 0 stored

After thold if D 1: N1 is off : No change
D=1: X goes low, leaving N1 on. Pulls Q high
After thold if D 0:
No P/G connection on LHS X latched low by X-coupled inverters)
ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
p1 p1
p2 p2
Q=1
1 1 0
n1 n1
1
n4 1 n4
n2 0 n2 0 1
n5 n5
n3 n3
Defines critical path
Tsu: 3 nfets on long enough for 10 transistion

ECE 733 Class Notes
Operation
Ck=1; D0 D=1; Ck0
p1 Q=1 p1 Q=1
0 p2 0 1 p2
0
n1 1 n1
1
n4 n4
n2 1 n2 0
n5 n5
n3 n3
Q does not change

ECE 733 Class Notes
Operation
Ck=0; D=0 Ck1; D=0
p1 p1
p2
Q=0
1 1 p2
n1 n1 10
1
n4 n4
n2 0 n2 0 1
n5 n5
n3 n3
If D went high while Delayed ck

nFET is turning off, a different Q could result
(i.e. tsu could be negative, and the action
In LHS pull down chain defines tsu)

ECE 733 Class Notes
Operation
Ck=1; D1 Ck0
p1
Q=0 p1
Q=0
1 p2 p2
1
1 1
n1 n1
0 1
n4 n4
n2 1 n2 0
n5 n5
n3 n3
Because top left nFET turned

off, Q does not change

ECE 733 Class Notes
SDFF Timing Waveforms

ECE 733 Class Notes
Sense Amp Flip Flop Clocked T

Matsui, et.al. 1994, DEC Alpha 21264; StrongArm DiffAmp
110 Storage
First stage : Sense Amp
Precharged to Hi when clk=0
p2, p3 : Off
n3, n4 : On
Clk 1
Diff Amp amplfies change in D
p2 or p3 turn on, latching value onto

storage cell
S or R go low
Role of N5
Keeps both INVs grounded even if D
changes
If D changes after thold
N5 reduces swing onto INVs
Strength of N5? Weak

SR latch
Ideal for low-swing inputs

ECE 733 Class Notes
Operation
Ck=0; D=1 Ck1; D=1
1 2 1 2
3 4 3 4
0 1
1 0
Data stored in latch at top center

ECE 733 Class Notes
Operation
Ck=1; D0 Ck0; D=1
1 2 1 2
0 0 4 3 0 0 4
3
0 1 1 1
1 0 1 0
Mn5 prevents change in latch RS latch unaffected as S, R = 1

ECE 733 Class Notes
SAFF Timing
Ck->1
N2 not on long enough to pull down

1 2 tsu 2 long enough to start turning N3 off.
Once N3 is enough, D-> 1 will no longer work
tforbidden
3 4 N3 is sufficiently off to prevent full transition
but on enough to start one
Tck-Q
0 1 N6-N1-N3 pulls 1 down
S->0
Delay in SR latch
1 0

ECE 733 Class Notes
SAFF

ECE 733 Class Notes

ECE 733 Class Notes
Modified SAFF

ECE 733 Class Notes
K6 ETL
p1 p2
p3
p4
n1
n3
n2
n4

ECE 733 Class Notes
Operation
Clock Low:
p1 p2
Nothing
p3
p4
Clock Hi
n1
n3
D or Db sampled onto Q or Qb
n2 n4
by clock pulse
An input of NOR 1
rst Lo, 3 INV delays later
q, qb Hi
rst off
Pulsed output! Self reset, Why?

-Must ensure output pulse
is sufficiently wide Reduces clock load

ECE 733 Class Notes
Flip Flop Comparison

ECE 733 Class Notes
StrongArm
Sense
K6 Amp
SDFF

ECE 733 Class Notes
HLFF
PowerPC
C2MOS

ECE 733 Class Notes
Delay Comparison

ECE 733 Class Notes
Power Delay Product

ECE 733 Class Notes
Clock Power Consumption

ECE 733 Class Notes
General Characteristics

ECE 733 Class Notes
Reduced Clock Swing FlipFlop

Goal : Reduce clock power
Clock 20% - 40% of overall chip power

ECE 733 Class Notes
Low Swing Double-Edge Triggered Flip-Flop

ECE 733 Class Notes
Flip Flop Design Summary

In high performance circuits, what are some of the goals of Flip-Flop design?
Fast total tD-Q = tsu + tclk-Q
Capture tradeoff:
Minimum Power consumption -Power Delay product
(internal + clock load) (=Energy.Delay at constant fclk)
Narrow aperture time (tSU+thold )
Minimize sensitivity to clock slope; charge sharing; crosstalk; Vdd/Gnd noise
What design characteristics tend to produce the best flip-flops?

Use latch concepts in FFs; esp. pulsed clocked latches
- gives narrow aperture WITH negative tSU
Strive for reduced node swings

NCSU Paul Franzon FlipFlops PDF

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ECE 733 Class Notes

Latches and Flip-Flops

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 1

Objectives and Motivation

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 2

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 3

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 4

Goals of Flip-Flop Design

tclock tck Q max tlog ic max t setup t skew max

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 5

tck-Q-max + tlogic-max tck-Q-min-tlogic-min

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 6

Goals of flip-flop design

NOT (or reduce) propagate clock skew to Q

Removes or reduces impact of tskew on clock period

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 7

Goals of Flip-Flop Design

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 8

Goals of Flip-Flop Design

Measured in fJ gives minimum energy per transition (and energy-delay

Clock edge rate variations

Charge leakage failures, including alpha particle strikes

Power & ground noise

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 9

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 10

Basic Bistable Static Storage Element

Stable operating point

Break supply current path (RS latch)

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 13

feedback in storage cell Q Q

Sizes n3, n4 = 3 m / 0.35 m

Sizes n1, n2, n5, n6 = 5 m / 0.35 m V1

Negative Voltage Margin

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 14

Revision: Flip-flop Design Goals

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 15

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 16

Doing this in Project

Conservative tsu: Aggressive tsu: Failure:

tsu tck-Q tsu tck-Q <tsu

One point on Another point Failure!

Reminder: Goal most likely to minimize tDQ, not tsu

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 17

Failure! Good! (NO change in Q due to D)

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 18

250 -60 -40 -20 0 20 40 60 80

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 19

Other Timing Parameters

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 20

Other Timing Parameters

e.g. pass-gate FF:

Problem if T2 open longer than Tinv-delay past this time

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 21

Latches Flip-Flops Characterized

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 22

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 23

Tri-state inverter Samples while clk High

Regenerate when clock high

Tracking input Recycling previous value

Holding sampled value Sampling input

2012, Dr. Paul D. Franzon, www.ece.ncsu.edu/erl/faculty/paulf.html 25

What determines t_clock-Q?

Clock buffer delay + delay through second tri-state buffer