Analysis and Conclusion: For our LBYEC61 project, we designed a positive-edge triggered D flip flop.

We learned in our lecture that all logical circuits can be designed with all XOR, all NAND, or all pass gates. For this project, we used NAND as our main component. The design when looked at individually is simple it is just a two-input NAND. The difficulty comes from joining all the NANDs inputs and outputs and connecting them to their respective ports. There is also a single inverter. The D flip flop we constructed has a master/slave connection. By changing the duty cycle and period of Vd (the input data), we can produce great changes to the output. For example, we had a low then constant high at first and thought it to be strange, but this was all because the rising and falling edge of the clock match that of the data input. We changed the period and produced a proper waveform. The irregularities of the pulse was better in testing or troubleshooting the circuit. Through this project, we got even better at designing since this was more difficult than what we had in the experiments. We also learned that there are many variations of a circuit that revolves just around one concept in this case, it is the D flip flop. The D flip flop we constructed was actually two D flip flops that work as one.