ON-CHIP GHz

CMOS LOW NOISE AMPLIFIER

Prof T K Bhattacharyya
E&ECE Department
IIT Kharagpur
 What is LNA?
An RF amplifier that amplifies signal received from
the antenna.
Generally, the first stage of a receiver.
Provide enough gain to overcome the noise of
subsequent stages.
Add as much low noise as possible.
Present a specific impedance (50) to the source
impedance for maximum power transfer.

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 LNA in a communication system
LNAs are found in radio communications systems, medical instruments and
electronic equipment.
A typical LNA may supply a power gain of 100 (20 decibels (dB)) while
decreasing the signal-to-noise ratio by less than a factor of two (a 3 dB noise
figure).
Although LNAs are primarily concerned with weak signals that are just above
the noise floor, they must also consider the presence of larger signals that cause
intermodulation distortion.
The following diagram shows the position of a LNA in a communication
system, where it drives the down-conversion mixer.

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 LNA parameters

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 Parameters of an LNA (1)

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WHY ON-CHIP ?
4 P-words :
Price : Mass volume production reduces price
Package : Integration reduces No of total pin count
Performance : Improves except few cases
Power : On-chip components dissipate lesser power
Challenges :
Poor quality of passive components (inductor etc.)
Device modeling at RF frequencies
Realizing good analog circuits in digital technology
Meeting stringent performance requirements in
digital environment. Substrate noise coupling is more
critical in mixed signal
 LOW NOISE AMPLIFIERS
Characteristics :
First gain stage in receiver
Received signal very weak (~V)
Gains usually moderate (10-20 dB
typical)
Noise Figure (NF) should be as
low as possible (<3 dB typical)
Linearity is also an issue
Reverse Isolation should be high
Design consideration :
Noise Figure: 2~3dB
Gain: 15~20dB
IIP3: ~ -10dBm
Input/output Impedance: 50
Ohm
Input/output Return Loss: -
15dB
Reverse Isolation: >30dB
Stability Factor >1
 Different structure of CMOS LNA
All structures are narrow-band

Capacitive input impedance.

Lg cancels Capacitive term.
A parallel RS (50 ) is added
to match input source R50.
To reduce the effect of Zout
Common source LNA ac equivalent model (img) on tuning circuit, C
Disadvantage of this circuit :
value should be large
Due to Rextra , the power divide by 2. compared to Zout
NF ~1+ (/) * Rextra/R50 , & Corresponding circuit
(=gm/gdo) are device parameter. NF~3-4
dB.
Due to Cgd reverse isolation(S11)
Bad.
Cgd affects stability due to presence of
zero in transfer function (Vout/Vin)
 Most popular LNA topology
Remedy
Cascode source degeneration common source
Equation for choosing Input matching network
Component

Choosing of device (W/L) & Vgs : determine gm

& Cgs value , then Ls and Lg can be found.
Effect of channel resistance & gate resistance :
modify above equation (Fingering is done in
layout to reduce this value ).
The parasitic of inductor must be considered for
calculating practical component values.
Equation for choosing output matching network component
Gate of M2 is ac ground,
so output cap due to Zout
is Cgd2 only. C value
lesser. Good L, Q is 2 3, then get Rd,
As impedance looking to From Rd find-out equivalent Ld by ASITIC
source of M2 is 1/gm2 as a with maximum possible Q. then calculate C from
result Miller cap effect 0, check whether C is much larger(~10 times of
gets reduced. Cgd)
LNA topologies

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 LNA Design Example

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Power-Constrained Noise Optimized Device Sizing in CS LNA (1)

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Power-Constrained Noise Optimized Device Sizing in CS LNA (2)

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 Noise figure( contd)
Minimum noise figure (Neglecting the gate resistance and
inductor losses & without any power constraints):

Gopt= 20m mho( Gs) Cgs can be calculated from above Eq.
Choose smallest possible length[ to make T(~1/L2) high].
Then find out W, from the relation Cgs= 2/3 Cox. W*L.(in saturation)
This calculation gives a very high W value , which makes large power
consumption, therefore noise minima condition is not
preferable for choosing device geometry.

.. Analysis based on power constraint noise figure calculation :

More complex form( considering all losses)

 Noise (contd)
, , device geometry and scaling
Simplified form dependent constants

Power constraint Without Power constraint

Noise minimum Noise minimum

The FminP differ from Fmin about 0.5dB to 0.7 dB more( <1)
But the FminP are more reliable one from practical circuit design point of view.

It is difficult to achieve maximum gain, minimum power

consumption , minimum noise figure & good input match at a
single value of Wopt & bias ( Vgs)required to develop an
efficient algorithm for setting global optimum for different
constraints.
 LNA topologies

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CS Stage with matching through feedback

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CG Stage

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Cascode CG stage

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 Other LNA Structures
This is a common gate topology. the impedance
looking from source end is 1/(gm+gm-bulk). This should be
made 50ohm for matching (active matching).
The Ls cancels the Cgs value.
The noise figure is poor.
Good linearity.

Common gate LNA structure

This is an inverting amplifier topology.
Large gain {~(gm1+gm2)}.
Bias current reusable.
Relatively small Bias current for identical gain.
The noise figure is poor.
Complementary LNA structure
LNA topologies

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LNA topologies

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LNA topologies

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Differential LNA
The single ended LNA (especially for source degeneration
topology), the ground parasitic inductor is a crucial since
degeneration inductor value is small parasitic dominates in
operation
The ground inductor can be tuned by putting extra cap across
ground line inductor, but any cap in source line produces a negative
resistance in input. This causes stability problem.
Remedy Differential structure
 Cascode CS LNA design example
The adjacent topology is the cascode
common-source LNA.
1 forms the common-source amplifier
followed by the common-gate device 2 .
For noise optimized design, the device size
is large leading to high input capacitance
providing low input impedance.
Input signal will be attenuated because of
low input impedance, hence input matching
network comprising and 1 is
constructed.
and 1 is the output resonating network
tuned to frequency of operation.
1 is the parasitic resistance of the resonant
network determining the gain of the LNA.

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 Cascode CS LNA design example

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 Cascode CS LNA design example
Input impedance looking into the input
of the LNA is
1 1
= + 1 +
1 1
The real part should be matched to 50
and 1 and 1 tuned to operating
frequency.
This constrains the values of , 1 and
1 .
A better solution is to add an inductor
. More freedom in choosing passives
for input matching
1 1
= + 1 + +
1 1

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 Cascode CS LNA design example

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 Cascode CS LNA design example

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 Cascode CS LNA design example

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 Cascode CS LNA design example
Final LNA with all the component values

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 Simulation Results for Cascode CS LNA
Gain Noise Figure

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