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Designing DC/DC Converters Based On SEPIC Topology: by Jeff Falin
Designing DC/DC Converters Based On SEPIC Topology: by Jeff Falin
+
VL1a
L1a CP
VIN + VOUT
+
I L1a
+
C IN I L1b L1b VL1b COUT
+
VL1a
L1a CP D1
VIN + VOUT
I L1a +
+
C IN I L1b L1b VL1b COUT
18
19
not have equal inductance and the ripple currents will not capacitance, but not too much ESR, to meet the applica-
be exactly equal. Regardless, for a desired ripple-current tions requirement for output voltage ripple, VRPL:
value, the inductance required in a coupled inductor is IOUT D(max)
estimated to be half of what would be needed if there VRPL
COUT fSW(min)
were two separate inductors, as shown in Equation 4: (6)
1 VIN(min) D(max) + ESR I L1a(Peak) + I L1b(Peak)
L1a(min) = L1b(min) = (4)
2 I L fSW(min) If very low-ESR (e.g., ceramic) output capacitors are used,
the ESR can be ignored and the equation reduces to
To account for load transients, the coupled inductors
saturation current rating needs to be at least 20% higher IOUT D(max)
COUT , (7)
than the steady-state peak current in the high-side induc- VRPL fSW(min)
tor, as computed in Equation 5:
where fSW(min) is the minimum switching frequency. A
I L
I L1a( Peak ) = I IN + = I IN 1 + 30% (5) minimum capacitance limit may be necessary to meet the
2 2 applications load-transient requirement.
Note that IL1b(Peak) = IOUT + IL /2, which is less than The output capacitor must have an RMS current rating
IL1a(Peak). greater than the capacitors RMS current, as computed in
Figure 5 breaks down the capacitor ripple voltage as Equation 8:
related to the output-capacitor current. When Q1 is on, D(max)
the output capacitor must provide the load current. IC = IOUT (8)
OUT( RMS) 1 D(max)
Therefore, the output capacitor must have at least enough
TS
IIN
ICOUT
D TS (1 D) TS
IOUT
VESR (IL1a + IL1b IOUT)
VRPL_ESR
VESR IOUT
VRPL_COUT
VRPL
VOUT_AC
20
The input capacitor sees fairly low ripple currents due The output diode must be able to handle the same peak
to the input inductor. Like a boost converter, the input- current as Q1, IQ1(Peak). The diode must also be able to
current waveform is continuous and triangular; therefore, withstand a reverse voltage greater than Q1s maximum
the input capacitor needs the RMS current rating, voltage (VIN[max] + VOUT + VFWD) to account for transients
I and ringing. Since the average diode current is the output
IC (RMS) = L . (9) current, the diodes package must be capable of dissipat-
IN
12
ing up to PD_D1 = IOUT VFWD .
The coupling capacitor, CP, sees large RMS current rela- Design example
tive to the output power:
A DC/DC converter is needed that can provide 12 V at
1 D(max) 300 mA (maximum) with 90% efficiency from an input
IC = I IN (10)
P( RMS) D(max) voltage ranging from 9 to 15 V. We select the TPS61170,
which has a 38-V switch, a minimum switch-current limit of
From Figure 3, the maximum voltage across CP is 0.96 A, and a 1.2-MHz nominal (1.0-MHz minimum) switch
VQ1(max) VL1b(max) = VIN + VOUT VOUT = VIN. ing frequency. The maximum output voltage ripple allowed
is 100 mVPP. The maximum ambient temperature is 70C,
The ripple across CP is
and we will use a high-K board. In Reference 1, Ray Ridley
IOUT D(max) explains how to compensate the control loop at the link.
VC = . (11)
P CP fSW Table 1 summarizes the computations using the equa-
tions given earlier. Equations 8 through 11 are not shown
Selecting active components because ceramic capacitors with low ESR, high RMS cur-
rent ratings, and the appropriate voltage ratings were
The power MOSFET, Q1, must be carefully selected so
used. Figure 6 shows the schematic. Figure 7 shows the
that it can handle the peak voltage and currents while
designs efficiency with a Coiltronics DRQ73 inductor and
minimizing power-dissipation losses. The power FETs
a Wurth 744877220. Figure 8 shows the device operation
current rating (or current limit for a converter with an
in deep CCM.
integrated FET) will determine the SEPIC converters
maximum output current. References
As shown in Figure 3, Q1 sees a maximum voltage of 1. Ray Ridley. (Nov. 2006). Analyzing the SEPIC
VIN(max) + VOUT. As shown in Figure 4, Q1 must have a converter. Power Systems Design Europe [Online].
peak-current rating of Available: http://www.powersystemsdesign.com/design_
IQ1( Peak ) = I L1a( Peak ) + I L1b( Peak ) = IIN + IOUT + I L . (12) tips_nov06.pdf
2. Robert W. Erickson and Dragan Maksimovic,
At the ambient temperature of interest, the FETs power- Fundamentals of Power Electronics, 2nd ed. (New
dissipation rating must be greater than the sum of the York: Springer Science+Business Media LLC, 2001).
conductive losses (a function of the FETs rDS[on]) and the 3. John Betten and Robert Kollman. (Jan. 25, 2006). No
switching losses (a function of the FETs gate charge) as need to fear: SEPIC outperforms the flyback. Planet
given in Equation 13: Analog [Online]. Available: http://www.planetanalog.com/
2 showArticle.jhtml?articleID=177103753
PD _ Q1 = IQ 1(RMS) rDS(on ) D(max) + I Q1(Peak)
(13) Related Web sites
t Rise + tFall
VIN(min) + VOUT + VFWD fSW , power.ti.com
2
www.ti.com/sc/device/TPS61170
where tRise is the rise time on the gate of Q1 and can be
computed as Q1s gate-to-drain charge, QGD, divided by the
converters gate-drive current, IDRV. Q1s RMS current is
I IN
IQ1( RMS ) = . (14)
D(max)
21
0 .44 A
(14) I Q1(RMS) = =0 .58 A TPS61170 with 0.96-A-rated switch. Capable
0 .58
of dissipating 825 mW at 70C.
PD_Q1 =(0 .58 A) 2 0 .3 0 .58 +0 .87 A
(13)
(9 V +12 V + 0 .5 V) 10 ns 1 MHz = 246 mW
Figure 6. SEPIC design with 9- to 15-V VIN and 12-V VOUT at 300 mA
CTRL FB
4.99 k
COMP GND R2
10 k
C3
22 nF
22
100
Wurth, VIN = 9 V
95
Wurth, VIN = 15 V
90
85
Coiltronics, VIN = 9 V
Efficiency (%)
80
Coiltronics, VIN = 15 V
75
70
65
60
55
50
0 100 200 300 400
Output Current , IOUT (mA)
SW
(20 V/div)
IL High
(200 mA/div)
IL Low
(200 mA/div)
VOUT _AC
(50 mV/div)
Time, t (1 s/div)
23
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