State machines Model

Lecture 17 : State Machine and VHDL

z The general model of a state machine consists of
three parts:
y a declaration part
y a clocked process
y a combinational process
261321 Computer Hardware Design
z Another model may have different processes:
y an encoding process
Lachana Inchaiwong
y a clocked process
y a combination process

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Moore machine Moore machine in VHDL code

register
CLK ENTITY demo IS
input Logic Logic output
PORT ( clk, in1, reset: IN std_logic;
reset out1: OUT std_logic);
END demo;
current state Block diagram
ARCHITECTURE moore OF demo IS
TYPE state_type IS (s0,s1,s2,s3); -- state declaration
1
S0 S1 SIGNAL state: state_type;
0000 1001
BEGIN
0 0
demo_process: process(clk, reset) -- clocked process
State diagram
S2 1 S3
1111 1100
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Moore machine in VHDL Code Moore machine in VHDL code

BEGIN output_p : PROCESS (state) -- combinational process

IF reset=1 THEN BEGIN
state<=s0; CASE state IS
ELSIF clkEVENT AND clk=1 THEN WHEN s0=> out1<=0000;
CASE state IS WHEN s1=> out1<=1001;
WHEN s0=> IF in1=1 THEN WHEN s2=> out1<=1111;
state<=s1; WHEN s3=> out1<=1100;
END IF; END CASE;
WHEN s1=> (fill the rest of the process yourself) END PROCESS;
END PROCESS; END moore;

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 Another model for Moore machine Another model

ENTITY demo IS BEGIN

PORT ( clk, in1, reset: IN std_logic; CASE state IS
out1: OUT std_logic); WHEN s0=> IF in1=1 THEN
END demo; state<=s1;
END IF;
ARCHITECTURE moore OF demo IS
WHEN s1=> (fill the rest of the process yourself)
TYPE state_type IS (s0,s1,s2,s3); -- state declaration
.
SIGNAL current_state, next_state : state_type;
END PROCESS;
BEGIN
P0: process(state, in1) -- combinational process

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Another model Another model

P1: PROCESS(clk, reset) -- clocked process P3 : PROCESS (current_state) -- combinational process

BEGIN BEGIN
IF reset=1 THEN CASE current_state IS
state<=s0; WHEN s0=> out1<=0000;
ELSIF clkEVENT AND clk=1 THEN WHEN s1=> out1<=1001;
current_state<=next_state; WHEN s2=> out1<=1111;
END IF; WHEN s3=> out1<=1100;
END PROCESS; END CASE;
END PROCESS;
END moore;

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Mealy machine Mealy machine in VHDL code

rest/0000 rest/1001
1/1001 z A Mealy machine is constructed in exactly the
S0 S1 State diagram
same way as a Moore machine. The difference
0/0000 0/1100 is the combinational output signal process, which
S2 1/1111 S3
, according to the definition of a Mealy machine,
rest/1111
should be a function of the state vector and all
rest/1100
the inputs.
register z The clocked process, on the other hand, is
CLK
input Logic identical, regardless of whether a Mealy machine
or a Moore machine is begin designed.
reset
Block diagram
current state
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Mealy machine in VHDL code Solution from last lecture

z Write the VHDL code to describe a Mealy D1 = Q1+D+Q0N

machine as seen in the diagram. D0 = NQ0 +Q0N+Q1 N+Q1 D

OPEN = Q 1Q0

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