AHB trabsfers:single,incremental burst hat do not wrap at adress boundries and wrapping burst that

wrap at particular adress boundries.

Every transfer consist of

adress phase: 1 adress and control cycle

dat phase : 1 or more cycles of the data

Hresp:slave indicates the transfer is sucesss/failure

Hready:master extends the data phase by using Hready, This signal, when LOW, causes wait states to be
inserted into the transfer and enables the slave to have extra time to provide/sample data

Hresetn:active low

HBurst[2:0]:single transfer/burst of 4/8/16/ beats are supported.The burst can be incremental/wrapping.

undefined length of burst that has a burst of length one/single burst for single trasnfer. Incr: incremental
burst of undefined length

HProt[3:0] :The signals indicate if the transfer is an opcode fetch or data access, and if the

transfer is a privileged mode access or user mode access. For masters with a

memory management unit these signals also indicate whether the current access is

cacheable or bufferable.

Hsize[2:0] : Indicates the size of the transfer, that is typically byte, halfword, or word. The

protocol allows for larger transfer sizes up to a maximum of 1024 bits.

Hwrite:This signal indicates a write transfer when high & read when low

Htrans[1:0]: Indicates the transfer type of the current transfer. This can be:IDLE(no transfer) ,BUSy (burst
operations are ongoing),NONSEQUENTIAL(single trasnfer),SEQUENTIAL ( burst)

Hresp :The transfer response, after passing through the multiplexor, provides the master

with additional information on the status of a transfer.

When LOW, the HRESP signal indicates that the transfer status is OKAY.

When HIGH, the HRESP signal indicates that the transfer status is ERROR.

But in Multimaster AHB it us used Split & retry instead of hresp(ok and error)
What is the size of max data can be transferred in single transfer?

A:1024 bits.

When an out of range address is detected the default slave is selected.

It supports up to 16 masters.

Default slave

Whenever a wrong address is issued it answers with the typical 2-cycle error response

http://hardwareverification.weebly.com/specman-basics-and-code.html

complicated bugs:

Extreme randomization, for instance once prog and erase & prog, and encryption & scrambled and
interleaving sequences where boundries are hit.

Stressing on mulitple frequencies

On randomizing frequencies what I have done is sending sof on one frrquency and data on other
freqeuncy and eof on another frequency then master is not respoding for correct sof rather it gets glitch
inside and produced error.

Timer: paused to resume ( start and paus then resume and stop, load timer again and paus then resume
it was missing the clock cycle window.

Gong security macrocel: no command:

Current resposniblities:

I am currently working with ST microelectronics from more than 6 years, I started my verification career
as developing SWP protocol using Specman e then continued with many VIPS and on & off c based
verification. And developed use cases & SOC level verification apart from technical skills I have been
assigned mentoring interns & allowed to be responsible in project management as verif object leader for
one Project. Kind of exposure for project management.

Achievements :

I have always done verification as my passion, and found more than 100 bugs and star award. And gave
multiple times start award.

Early Career:
IN my earlier career I have worked as an FPGA support engineer working on xilinx FPGAs and Tools

Education:

And having a masters degree in Embedded electronics from Sweden.

Outside of my technical skills:

I worked with different organization in multiple countries with multicultural teams and am very easy
going, flexible and I must say that Iuse to integrate very quikly in any given envrionment . I have wored
with swedes,brits,scotts,french, ofcourse indians, chinese etc. And to emphasis I am quick learner.