MC14518B

Dual Up Counters
The MC14518B dual BCD counter and the MC14520B dual binary
counter are constructed with MOS Pchannel and Nchannel
enhancement mode devices in a single monolithic structure. Each
consists of two identical, independent, internally synchronous 4stage
counters. The counter stages are type D flipflops, with
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interchangeable Clock and Enable lines for incrementing on either the
positivegoing or negativegoing transition as required when
cascading multiple stages. Each counter can be cleared by applying a MARKING
high level on the Reset line. In addition, the MC14518B will count out DIAGRAMS
of all undefined states within two clock periods. These complementary 16
MOS up counters find primary use in multistage synchronous or PDIP16
P SUFFIX MC14518BCP
ripple counting applications requiring low power dissipation and/or CASE 648 AWLYYWW
high noise immunity.
1
Diode Protection on All Inputs
16
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Internally Synchronous for High Internal and External Speeds SOIC16 14518B

Logic EdgeClocked Design Incremented on Positive Transition DW SUFFIX

CASE 751G
of Clock or Negative Transition on Enable AWLYYWW
Capable of Driving Two Lowpower TTL Loads or One Lowpower
1
Schottky TTL Load Over the Rated Temperature Range
16
SOEIAJ16
F SUFFIX MC14518B
CASE 966 AWLYWW
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
1
Symbol Parameter Value Unit
VDD DC Supply Voltage Range 0.5 to +18.0 V A = Assembly Location
Vin, Vout Input or Output Voltage Range 0.5 to VDD + 0.5 V WL or L = Wafer Lot
(DC or Transient) YY or Y = Year
WW or W = Work Week
Iin, Iout Input or Output Current 10 mA
(DC or Transient) per Pin
PD Power Dissipation, 500 mW ORDERING INFORMATION
per Package (Note 3.)
Device Package Shipping
TA Operating Temperature Range 55 to +125 C
Tstg Storage Temperature Range 65 to +150 C MC14518BCP PDIP16 2000/Box

TL Lead Temperature 260 C MC14518BDW SOIC16 47/Rail

(8Second Soldering)
MC14518BDWR2 SOIC16 1000/Tape & Reel
2. Maximum Ratings are those values beyond which damage to the device
may occur. MC14518BF SOEIAJ16 See Note 1.
3. Temperature Derating:
Plastic P and D/DW Packages: 7.0 mW/_C From 65_C To 125_C MC14518BFEL SOEIAJ16 See Note 1.

This device contains protection circuitry to guard against damage due to high 1. For ordering information on the EIAJ version of
static voltages or electric fields. However, precautions must be taken to avoid the SOIC packages, please contact your local
applications of any voltage higher than maximum rated voltages to this ON Semiconductor representative.
highimpedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) vVDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2000 1 Publication Order Number:

March, 2000 Rev. 3 MC14518B/D
 MC14518B

PIN ASSIGNMENT
CA 1 16 VDD
EA 2 15 RB
Q0A 3 14 Q3B
Q1A 4 13 Q2B
Q2A 5 12 Q1B
Q3A 6 11 Q0B
RA 7 10 EB
VSS 8 9 CB

BLOCK DIAGRAM
CLOCK
Q0 3
1
Q1 4
C
2 Q2 5
ENABLE Q3 6
R
7
CLOCK 11
Q0
9
Q1 12
C
10 Q2 13
ENABLE Q3 14
R
15
VDD = PIN 16
VSS = PIN 8

TRUTH TABLE
Clock Enable Reset Action
1 0 Increment Counter
0 0 Increment Counter
X 0 No Change
X 0 No Change
0 0 No Change
1 0 No Change
X X 1 Q0 thru Q3 = 0
X = Dont Care

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 MC14518B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

Characteristic Symbol
VDD
Vdc Min
55_C
Max Min
25_C
Typ (4.) Max Min
125_C
Max Unit
Output Voltage 0 Level VOL 5.0 0.05 0 0.05 0.05 Vdc
Vin = VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
1 Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin = 0 or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Input Voltage 0 Level VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 1.5 2.25 1.5 1.5
(VO = 9.0 or 1.0 Vdc) 10 3.0 4.50 3.0 3.0
(VO = 13.5 or 1.5 Vdc) 15 4.0 6.75 4.0 4.0
1 Level VIH Vdc
(VO = 0.5 or 4.5 Vdc) 5.0 3.5 3.5 2.75 3.5
(VO = 1.0 or 9.0 Vdc) 10 7.0 7.0 5.50 7.0
(VO = 1.5 or 13.5 Vdc) 15 11 11 8.25 11

Output Drive Current IOH mAdc

(VOH = 2.5 Vdc) Source 5.0 3.0 2.4 4.2 1.7
(VOH = 4.6 Vdc) 5.0 0.64 0.51 0.88 0.36
(VOH = 9.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOH = 13.5 Vdc) 15 4.2 3.4 8.8 2.4
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 0.51 0.88 0.36 mAdc
(VOL = 0.5 Vdc) 10 1.6 1.3 2.25 0.9
(VOL = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
Input Current Iin 15 0.1 0.00001 0.1 1.0 Adc
Input Capacitance Cin 5.0 7.5 pF
(Vin = 0)
Quiescent Current IDD 5.0 5.0 0.005 5.0 150 Adc
(Per Package) 10 10 0.010 10 300
15 20 0.015 20 600
Total Supply Current (5.) (6.) IT 5.0 IT = (0.6 A/kHz) f + IDD Adc
(Dynamic plus Quiescent, 10 IT = (1.2 A/kHz) f + IDD
Per Package) 15 IT = (1.7 A/kHz) f + IDD
(CL = 50 pF on all outputs, all
buffers switching)
4. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL 50) Vfk
where: IT is in A (per package), CL in pF, V = (VDD VSS) in volts, f in kHz is input frequency, and k = 0.002.

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 MC14518B

SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)

Characteristic Symbol VDD Min

All Types
Typ (8.) Max Unit
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 100 200
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 50 100
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 40 80
Propagation Delay Time tPLH, ns
Clock to Q/Enable to Q tPHL
tPLH, tPHL = (1.7 ns/pF) CL + 215 ns 5.0 280 560
tPLH, tPHL = (0.66 ns/pF) CL + 97 ns 10 115 230
tPLH, tPHL = (0.5 ns/pF) CL + 75 ns 15 80 160
Reset to Q tPHL ns
tPHL = (1.7 ns/pF) CL + 265 ns 5.0 330 650
tPHL = (0.66 ns/pF) CL + 117 ns 10 130 230
tPHL = (0.66 ns/pF) CL + 95 ns 15 90 170
Clock Pulse Width tw(H) 5.0 200 100 ns
tw(L) 10 100 50
15 70 35
Clock Pulse Frequency fcl 5.0 2.5 1.5 MHz
10 6.0 3.0
15 8.0 4.0
Clock or Enable Rise and Fall Time tTHL, tTLH 5.0 15 s
10 5
15 4
Enable Pulse Width tWH(E) 5.0 440 220 ns
10 200 100
15 140 70
Reset Pulse Width tWH(R) 5.0 280 125 ns
10 120 55
15 90 40
Reset Removal Time trem 5.0 5 45 ns
10 15 15
15 20 5
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled Typ is not to be used for design purposes but is intended as an indication of the ICs potential performance.

VDD

0.01 F
500 F ID CERAMIC

PULSE
C Q0
GENERATOR Q1
Q2 CL
E Q3 CL
R CL
CL

VSS

20 ns 20 ns
90%
50%
10%
VSS
VARIABLE
WIDTH

Figure 1. Power Dissipation Test Circuit and Waveform

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 MC14518B

VDD 20 ns 20 ns
90% VDD
CLOCK 50%
PULSE Q0 INPUT 10%
C VSS
GENERATOR tWH tWL
Q1
tPLH tPHL
Q2 CL
E CL 90%
R Q3 CL 50%
CL 10%
VSS Q
tr tf

Figure 2. Switching Time Test Circuit and Waveforms

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

CLOCK
ENABLE

RESET

1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0

Q0

Q1
MC14518B

Q2

Q3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4

Q0

Q1
MC14520B

Q2

Q3

Figure 3. Timing Diagram

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 MC14518B

Q0 Q1 Q2 Q3

D Q D Q D Q D Q

C Q C Q C Q C Q
R R R R
RESET

ENABLE

CLOCK

Figure 4. Decade Counter (MC14518B) Logic Diagram

(1/2 of Device Shown)

Q0 Q1 Q2 Q3

D Q D Q D Q D Q

C Q C Q C Q C Q
R R R R
RESET

ENABLE

CLOCK

Figure 5. Binary Counter (MC14520B) Logic Diagram

(1/2 of Device Shown)

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 MC14518B

PACKAGE DIMENSIONS

PDIP16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 64808 NOTES:
A 1. DIMENSIONING AND TOLERANCING PER ANSI
ISSUE R Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
16 9 3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
B 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 8 5. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
DIM MIN MAX MIN MAX
F C L A 0.740 0.770 18.80 19.55
B 0.250 0.270 6.35 6.85
S C 0.145 0.175 3.69 4.44
D 0.015 0.021 0.39 0.53
SEATING F 0.040 0.70 1.02 1.77
T PLANE G 0.100 BSC 2.54 BSC
H 0.050 BSC 1.27 BSC
H K M J 0.008 0.015 0.21 0.38
J K 0.110 0.130 2.80 3.30
G L 0.295 0.305 7.50 7.74
D 16 PL
M 0_ 10 _ 0_ 10 _
0.25 (0.010) M T A M S 0.020 0.040 0.51 1.01

SOIC16
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G03
ISSUE B
D A
q
16 9 NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
M

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.
B

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

H

h X 45 _
M

PROTRUSION.
E
8X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
1 8 CONDITION.

MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
A

e 1.27 BSC
H 10.05 10.55
h 0.25 0.75
L

SEATING
14X e PLANE L 0.50 0.90
q 0_ 7_
A1

T C

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 MC14518B

PACKAGE DIMENSIONS

SOEIAJ16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE O NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
16 9 LE MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
Q1 OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
E HE M_ 4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
1 8 L DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DETAIL P DIMENSION AT MAXIMUM MATERIAL CONDITION.
Z DAMBAR CANNOT BE LOCATED ON THE LOWER
D RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
VIEW P
e A MILLIMETERS INCHES
c DIM MIN MAX MIN MAX
A 2.05 0.081
A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.18 0.27 0.007 0.011
A1 D 9.90 10.50 0.390 0.413
b E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z 0.78 0.031

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