DYNAMIC CONST LOAD

f = A[B[g]+1]
sll $to, $s1, 2 // g * f
add $t1, $s7, $t0 // B + g * 4
lw $t2, 0($t1) // B[g] = value at address (B + g * 4)
sll $t3, $t2, 2 // B[g] * 4
add $t4, $t3, $s6 // A + B[g] * 4
lw $s0, 4($t4) //value at address (A + 4*B[g] + 4)

PERFORMANCE = 1 / execution time of program MIPS OVERFLOW: No conditional branch to test

CPUexecution time = CPU clock cycle x clock cycle time overflow, but a sequence of MIPS instruction can
! ! = CPU clock cycle for prog / clock rate !
discover overflow and jump to sequence to a
Time = Seconds/Program = Instructions/Program x decide what to do. OR NOT DO ANYTHING
! Clock Cycle / Instruction x Seconds / Clock Cycle
UnitsOfMeasure Sign extension: fill in with most significant bit PIPELINING
CPUexeTime = Seconds for the program 2ʼs complement: flip, +1 >> Time between instructions pipelined = time between instructions non-pipeline /
InstructionCount = Instructions executed for program number of pipe stages
caller sets $a0-a3, $ra = PC+4 or branch
CPI (CyclePerInstruct) = Avg Cycles per Inst >> Improves Performance: increasing instruction throughput, as opposed to
caller sets $v0, v1
ClockCycleTime = Seconds per Clock Cycle decreasing execution time for individual instruction
loading 32-bit constant >> HAZARDS:
MULTIPLY split 32-bit to store in register b/c instruction -> Structural: hardware cannot support combining instructions on same cycle
(1) Start only takes in 16 bit constant -> Data: When one instruction stalls and all others must wait for it to finish
(2) Multiplier == 1, add multiplier to prod & place -> Load-use: data loaded by one instruction that is not ready being requested by
result in PRODUCT reg fetch instruction -> decode instruction -> fetch
another instruction
(3) Shift multiplicand left by 1 operand -> execute -> increment PC (or
-> Control: control decision based on instruction that is not ready (branch/jump)
(4) Shift multiplier right by 1 branch) -> repeat
-> Forwarding/bypass: supply some value to another instruction before the origin
(5) if (32 [31 for signed] reps) {GTFO}, else go to (2) !"#$"%&'%$&()*+,-.!"/0&/*,&*+&1234&50&5*--&*+&123&6*,&*+&(789&,7:;94&<=0&<789&=7>;,.&
instruction even finishes (bypass some parts of data path)
single datapath
DIVISION &
- execute all instruction in one clock cycle
(1) Start 7"& Memory :"&
- no datapath resources can be used more ?*@,>7;&(789&+>A:9@0&BCC@9--&DD&#E&:*,-&
>> Hit time: time to access upper level, including check for Hit/Miss
?*@,>7;&(789&+>A:9@0&BCC@9--&DD&#E&:*,-&
(2) Sub DIVISOR from REMAINDER & place result
than once >> Miss penalty: time to replace block & push
$4&#4&$4&$4&$4&$4&$& data to processor
$4&#4&#4&%4&%4&#4&%&
into REMAINDER
(3) if (REMAINDER >= 0) { shift QUOTIENT left by 1 Floating Points '54&/4&/4&/4&/4&/4&/.&'E&()*+,-.& &'54&<=4&/4&<=&/4&/4&/.&'E&()*+,-.&
>> To find block : ( block address ) mod ( # of blocks in cache)
and set rightmost bit to 1 } (-1)^s x (1 + Fraction) x 2^(exponent - & >> Tag: Used to determine if word in cache& is requested one
(1) ELSE { Restore original value by 127or1023) 123&'E&()*+,-4&,78&7+C&(789&+>A:9@.&
>> Valid bit: indicate whether an entry contains 123&'E&()*+,-.&
anything (set on write/replace)
adding DIVISOR to REMAINDER and make small exponent match larger exponent?7;*C&& >>178&& <6F-*G7;&<789&H>A:9@&
Word/Offset: ?7;*C&& 178&&
Since words aligned to multiples of four<6F-*G7;&<789&
bytes, the two least
when adding #&& ##&& #%&
significant bits of every address are used to specify #&& #&& the #J&
byte part, only for the 32-
place in REMAINDER. Shift
#&& I&& E&
!"#$"%&'#(&)*+,-./&
bit byte address, not binary address #&& %&& #E&
QUOTIENT left, Set least sig bit to 0
MEMORY EXAMPLE: #&& #&&
& #J& #&& J&& M&
(4) Shift divisor right by 1 bit > Cache-Size = 2^n blocks, n = bits for index
- direct mapped cache w/ 16KB data, 4 word 0"&
#&& $&& !& 8"&#&& $&& !&
(5) If (33 rep) { GTFO } ELSE { GOTO (2) } > Block-Size = 2^m words, m = bits used 1+2-304&)056&,378629&:;;26..&<<&#=&8+-.&
1+2-304&)056&,378629&:;;26..&<<&#=&8+-.& for word within block, 2 bits used for the
block & &
byte part so 2^(m+2) bytes
$>&?>&%>&%>&#>&#>&=&@<&&
<789&,7:;9& =>&?>&H>&##>&R>&H>&##@<&&
<789&,7:;9&
Associativity - 16KB/4B = 4K (2^12) words = 2^12 / 4 = $>&###>&$##>&$##>&$$#>&$$#>&$#$&
> Tag-Size = 32 - (n + m + 2)
?7;*C& <6F-*G7;&(789&)@&*+&C*-K& $$#$>&$###>&$#$$>&#$##>&&#$$#>&$#$$>&#$##&
?7;*C&& <6F-*G7;&(789&
>> n-associative cache => # of blocks / n = # of sets 2^10 blocks & > Total-Bites = 2^n * (block size + tag size& +#&valid &!&field size)
>> set containing address = (block number) mod #&& !&
- 2^10 x (4x32 + (32 - 10 - 2 - 2) + 1) = 2^10 ABC9&&x ! ! ABC9&'#$&)*+,-./&
>> Block Size = 2^m#&&x 32,#J& valid bit =1
(number of sets) #&& #J& '#&()*+,.& '"!&()*+,.&
147 Kbit =&D0E&.6-&0..*F+0-+G69&'H&)*+,-./& =&D0E&.6-&0..*F+0-+G69&'H&)*+,-./&
$&& >>L*-K& Write-Through: write cache & memory at#&&same#E& time '"!&()*+,.&
>> selection: index select set, tag for comparison A059&1IJ&<<&#&8+->&&
>>M&Write-Buffer: have buffer of things to write A059&1IJ&<<&#&8+->&
VIRTUAL MEMORY #&&
K,;6L9&B60.-&.+5,+M+F0,-&8+-&*M&1IJ&
#&& to memory
M& (L2)
K,;6L9&B60.-&.+5,+M+F0,-&8+-&*M&1IJ&
Virtual Memory Virtual Address / Page Size = Virtual Page ##&& &
>>N&Write-Back: write only to cache till do replacement
& #&& N& (L1)
- Reference bit: set when page accessed, OS clears (ex 4KB = 4096 byte address for div) #&& > CPU
K,;6L& 104+;&&Time
##& A05&& = IIJ&&
(CPU104+;&&
execution
A05& clock cycle +
#&&memory
K,;6L& stall clock
##& A05&&
104+;&& IIJ&& cycle)
104+;&& *A05&
clock
them once in a while >> Go Through TBL, if not found, replace $&& & cycle IIJ&time
L*-K& & $&& IIJ& C*-K&
- TLB = translation-look-aside-buffer => page table using LRU, set tag to new VP#, and set #&& E&
$& > Memory-stall
#&& $$&& !&&clock#&&cycle$#&&
= read-stall
#H& cycle#&& E&
$& + write-stall
#&& $$#&&cycle
#%&& #&& $#$&& R&
cache Physical Page # to next increment. $& L*-K&
#& > Read-stall
#&& $$&& cycle
#%&& = #&&
reads/program
$#&& N& x read $&& #&&rate
#& miss C*-K&x#$#&&
read#=&
miss #&&
penalty #$$&& #H&
$&&
& L*-K& & $&& C*-K&
>> Tag = PT Index, check if in disk or table. If > Write-stall cycle = (writes/program x write miss rate x write miss penalty) +
PROBLEM: table, PageFault, if table, set that page to the #&& J& buffer stall
O+26F-P70))6;9&'H&)*+,-./&
write #&& J&
O+26F-P70))6;9&'H&)*+,-./&
- what is the ration between total bits required for A059&1IJ&<<&=&8+-.&
#&& #%& A059&1IJ<<=&8+-.&&
#&&x misses/instruction
#%&
TBL > Memory-stall cycle = instructions/program x miss penalty
& K,;6L9&1IJ&7*;&H& K,;6L9&1IJ&7*;&H&
such a cache implementation over the data storage > Average memory access time = time for& a hit + miss rate x miss penalty
& &
bits? 104+;&& 27@89@&(789&-*O9-&7;;)P&Q)@&A)@9&7CC@9--9-&,)&:9&-,)@9C&*+&7&-*+8;9&(7894&(),9+,*7;;F&
A05&& IQE.+F04&I056&J37862& 104+;&& A05&& IQE.+F04&I056&
- 22 extra bits for tag, line size = 16 bytes = 128 bits, #&& C9G@97-*+8&,69&7A)>+,&)Q&(789-&,67,&A>-,&:9&:@)>86,&*+&Q@)A&C*-K&7+C&*+G@97-*+8&,69&G)R9@789&
$&& !& #&& $#&& R&
so 128 + 22 = 150 => 150/128 #&& $&& #%& #&& #$&& #H&
)Q&,69&123"&/)P9R9@4&*Q&7&(@)8@7A&>-9-&7CC@9--9-&*+&7&-(7@-9&Q7-6*)+&'Q)@&9S7A(;9&@7+C)A;F&
PROBLEM: Describe handling of L1 write/miss: #&& $&& #H& #&& $$&& #%&
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#%% #%% #F% #%% G%% ?7;*C&&
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A059&1IJ&<<&#&8+->&& A059&1IJ&<<&#&8+->&
#%% E%% G% #%% E%% #&& G% ##&& #%& #&& #&& #J&
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#%% '%% #G% #%% M%% #&& #G%#&& #J& & #&& J&& M& &
% % #&& $&& !& K,;6L&
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#&& #E& '"!&()*+,.& A059&1IJ<<=&8+-.&&
#%% M% #%% M% #&& M& K,;6L9&1IJ&7*;&H&
#&& M& K,;6L9&1IJ&7*;&H&
#%% ##% #%% ##%#&& N& & #&& N& &
$%% N*-L% $%% #&&
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104+;&& ##& IQE.+F04&I056&J37862& 104+;&& A05&& IQE.+F04&I056&
#%% G% #%% G% $&& L*-K& #&& $&& $&& C*-K&!& #&& $#&& R&
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